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Pankaj Guptaa9e3ac22020-12-09 14:02:40 +05301/*
2 * Copyright 2018-2020 NXP
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 *
6 */
7
8#ifndef PLAT_PSCI_H
9#define PLAT_PSCI_H
10
11 /* core abort current op */
12#define CORE_ABORT_OP 0x1
13
14 /* psci power levels - these are actually affinity levels
15 * in the psci_power_state_t array
16 */
17#define PLAT_CORE_LVL PSCI_CPU_PWR_LVL
18#define PLAT_CLSTR_LVL U(1)
19#define PLAT_SYS_LVL U(2)
20#define PLAT_MAX_LVL PLAT_SYS_LVL
21
22 /* core state */
23 /* OFF states 0x0 - 0xF */
24#define CORE_IN_RESET 0x0
25#define CORE_DISABLED 0x1
26#define CORE_OFF 0x2
27#define CORE_STANDBY 0x3
28#define CORE_PWR_DOWN 0x4
29#define CORE_WFE 0x6
30#define CORE_WFI 0x7
31#define CORE_LAST 0x8
32#define CORE_OFF_PENDING 0x9
33#define CORE_WORKING_INIT 0xA
34#define SYS_OFF_PENDING 0xB
35#define SYS_OFF 0xC
36
37 /* ON states 0x10 - 0x1F */
38#define CORE_PENDING 0x10
39#define CORE_RELEASED 0x11
40#define CORE_WAKEUP 0x12
41 /* highest off state */
42#define CORE_OFF_MAX 0xF
43 /* lowest on state */
44#define CORE_ON_MIN CORE_PENDING
45
46#define DAIF_SET_MASK 0x3C0
47#define SCTLR_I_C_M_MASK 0x00001005
48#define SCTLR_C_MASK 0x00000004
49#define SCTLR_I_MASK 0x00001000
50#define CPUACTLR_L1PCTL_MASK 0x0000E000
51#define DCSR_RCPM2_BASE 0x20170000
52#define CPUECTLR_SMPEN_MASK 0x40
53#define CPUECTLR_SMPEN_EN 0x40
54#define CPUECTLR_RET_MASK 0x7
55#define CPUECTLR_RET_SET 0x2
56#define CPUECTLR_TIMER_MASK 0x7
57#define CPUECTLR_TIMER_8TICKS 0x2
58#define SCR_IRQ_MASK 0x2
59#define SCR_FIQ_MASK 0x4
60
61/* pwr mgmt features supported in the soc-specific code:
62 * value == 0x0, the soc code does not support this feature
63 * value != 0x0, the soc code supports this feature
64 */
65#define SOC_CORE_RELEASE 0x1
66#define SOC_CORE_RESTART 0x1
67#define SOC_CORE_OFF 0x1
68#define SOC_CORE_STANDBY 0x1
69#define SOC_CORE_PWR_DWN 0x1
70#define SOC_CLUSTER_STANDBY 0x1
71#define SOC_CLUSTER_PWR_DWN 0x1
72#define SOC_SYSTEM_STANDBY 0x1
73#define SOC_SYSTEM_PWR_DWN 0x1
74#define SOC_SYSTEM_OFF 0x1
75#define SOC_SYSTEM_RESET 0x1
76#define SOC_SYSTEM_RESET2 0x1
77
78#ifndef __ASSEMBLER__
79
80void __dead2 _psci_system_reset(void);
81void __dead2 _psci_system_off(void);
82int _psci_cpu_on(u_register_t core_mask);
83void _psci_cpu_prep_off(u_register_t core_mask);
84void __dead2 _psci_cpu_off_wfi(u_register_t core_mask,
85 u_register_t wakeup_address);
86void __dead2 _psci_cpu_pwrdn_wfi(u_register_t core_mask,
87 u_register_t wakeup_address);
88void __dead2 _psci_sys_pwrdn_wfi(u_register_t core_mask,
89 u_register_t wakeup_address);
90void _psci_wakeup(u_register_t core_mask);
91void _psci_core_entr_stdby(u_register_t core_mask);
92void _psci_core_prep_stdby(u_register_t core_mask);
93void _psci_core_exit_stdby(u_register_t core_mask);
94void _psci_core_prep_pwrdn(u_register_t core_mask);
95void _psci_core_exit_pwrdn(u_register_t core_mask);
96void _psci_clstr_prep_stdby(u_register_t core_mask);
97void _psci_clstr_exit_stdby(u_register_t core_mask);
98void _psci_clstr_prep_pwrdn(u_register_t core_mask);
99void _psci_clstr_exit_pwrdn(u_register_t core_mask);
100void _psci_sys_prep_stdby(u_register_t core_mask);
101void _psci_sys_exit_stdby(u_register_t core_mask);
102void _psci_sys_prep_pwrdn(u_register_t core_mask);
103void _psci_sys_exit_pwrdn(u_register_t core_mask);
104
105#endif
106
107#endif /* __PLAT_PSCI_H__ */