Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 1 | /* |
Louis Mayencourt | 944ade8 | 2019-08-08 12:03:26 +0100 | [diff] [blame] | 2 | * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved. |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 3 | * |
dp-arm | fa3cf0b | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 4 | * SPDX-License-Identifier: BSD-3-Clause |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 5 | */ |
| 6 | |
Masahiro Yamada | 0b67e56 | 2020-03-09 17:39:48 +0900 | [diff] [blame] | 7 | #include <common/bl_common.ld.h> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 8 | #include <lib/xlat_tables/xlat_tables_defs.h> |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 9 | |
| 10 | OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT) |
| 11 | OUTPUT_ARCH(PLATFORM_LINKER_ARCH) |
Jeenu Viswambharan | 2a30a75 | 2014-03-11 11:06:45 +0000 | [diff] [blame] | 12 | ENTRY(bl2_entrypoint) |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 13 | |
| 14 | MEMORY { |
Juan Castillo | fd8c077 | 2014-09-16 10:40:35 +0100 | [diff] [blame] | 15 | RAM (rwx): ORIGIN = BL2_BASE, LENGTH = BL2_LIMIT - BL2_BASE |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 16 | } |
| 17 | |
| 18 | |
| 19 | SECTIONS |
| 20 | { |
| 21 | . = BL2_BASE; |
Antonio Nino Diaz | 2ce2b09 | 2017-11-15 11:45:35 +0000 | [diff] [blame] | 22 | ASSERT(. == ALIGN(PAGE_SIZE), |
Sandrine Bailleux | 8d69a03 | 2013-11-27 09:38:52 +0000 | [diff] [blame] | 23 | "BL2_BASE address is not aligned on a page boundary.") |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 24 | |
Sandrine Bailleux | f91f144 | 2016-07-08 14:37:40 +0100 | [diff] [blame] | 25 | #if SEPARATE_CODE_AND_RODATA |
| 26 | .text . : { |
| 27 | __TEXT_START__ = .; |
| 28 | *bl2_entrypoint.o(.text*) |
Samuel Holland | 23f5e54 | 2019-10-20 16:11:25 -0500 | [diff] [blame] | 29 | *(SORT_BY_ALIGNMENT(.text*)) |
Sandrine Bailleux | f91f144 | 2016-07-08 14:37:40 +0100 | [diff] [blame] | 30 | *(.vectors) |
Roberto Vargas | d93fde3 | 2018-04-11 11:53:31 +0100 | [diff] [blame] | 31 | . = ALIGN(PAGE_SIZE); |
Sandrine Bailleux | f91f144 | 2016-07-08 14:37:40 +0100 | [diff] [blame] | 32 | __TEXT_END__ = .; |
| 33 | } >RAM |
| 34 | |
Roberto Vargas | 1d04c63 | 2018-05-10 11:01:16 +0100 | [diff] [blame] | 35 | /* .ARM.extab and .ARM.exidx are only added because Clang need them */ |
| 36 | .ARM.extab . : { |
| 37 | *(.ARM.extab* .gnu.linkonce.armextab.*) |
| 38 | } >RAM |
| 39 | |
| 40 | .ARM.exidx . : { |
| 41 | *(.ARM.exidx* .gnu.linkonce.armexidx.*) |
| 42 | } >RAM |
| 43 | |
Sandrine Bailleux | f91f144 | 2016-07-08 14:37:40 +0100 | [diff] [blame] | 44 | .rodata . : { |
| 45 | __RODATA_START__ = .; |
Samuel Holland | 23f5e54 | 2019-10-20 16:11:25 -0500 | [diff] [blame] | 46 | *(SORT_BY_ALIGNMENT(.rodata*)) |
Sandrine Bailleux | f91f144 | 2016-07-08 14:37:40 +0100 | [diff] [blame] | 47 | |
Masahiro Yamada | ac1bfb9 | 2020-03-26 10:51:39 +0900 | [diff] [blame^] | 48 | FCONF_POPULATOR |
| 49 | PARSER_LIB_DESCS |
Sandrine Bailleux | f91f144 | 2016-07-08 14:37:40 +0100 | [diff] [blame] | 50 | |
Roberto Vargas | d93fde3 | 2018-04-11 11:53:31 +0100 | [diff] [blame] | 51 | . = ALIGN(PAGE_SIZE); |
Sandrine Bailleux | f91f144 | 2016-07-08 14:37:40 +0100 | [diff] [blame] | 52 | __RODATA_END__ = .; |
| 53 | } >RAM |
| 54 | #else |
Sandrine Bailleux | 8d69a03 | 2013-11-27 09:38:52 +0000 | [diff] [blame] | 55 | ro . : { |
| 56 | __RO_START__ = .; |
Andrew Thoelke | e01ea34 | 2014-03-18 07:13:52 +0000 | [diff] [blame] | 57 | *bl2_entrypoint.o(.text*) |
Samuel Holland | 23f5e54 | 2019-10-20 16:11:25 -0500 | [diff] [blame] | 58 | *(SORT_BY_ALIGNMENT(.text*)) |
| 59 | *(SORT_BY_ALIGNMENT(.rodata*)) |
Juan Castillo | 8e55d93 | 2015-04-02 09:48:16 +0100 | [diff] [blame] | 60 | |
Masahiro Yamada | ac1bfb9 | 2020-03-26 10:51:39 +0900 | [diff] [blame^] | 61 | FCONF_POPULATOR |
| 62 | PARSER_LIB_DESCS |
Juan Castillo | 8e55d93 | 2015-04-02 09:48:16 +0100 | [diff] [blame] | 63 | |
Achin Gupta | b739f22 | 2014-01-18 16:50:09 +0000 | [diff] [blame] | 64 | *(.vectors) |
Sandrine Bailleux | 8d69a03 | 2013-11-27 09:38:52 +0000 | [diff] [blame] | 65 | __RO_END_UNALIGNED__ = .; |
| 66 | /* |
| 67 | * Memory page(s) mapped to this section will be marked as |
| 68 | * read-only, executable. No RW data from the next section must |
| 69 | * creep in. Ensure the rest of the current memory page is unused. |
| 70 | */ |
Roberto Vargas | d93fde3 | 2018-04-11 11:53:31 +0100 | [diff] [blame] | 71 | . = ALIGN(PAGE_SIZE); |
Sandrine Bailleux | 8d69a03 | 2013-11-27 09:38:52 +0000 | [diff] [blame] | 72 | __RO_END__ = .; |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 73 | } >RAM |
Sandrine Bailleux | f91f144 | 2016-07-08 14:37:40 +0100 | [diff] [blame] | 74 | #endif |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 75 | |
Achin Gupta | e9c4a64 | 2015-09-11 16:03:13 +0100 | [diff] [blame] | 76 | /* |
| 77 | * Define a linker symbol to mark start of the RW memory area for this |
| 78 | * image. |
| 79 | */ |
| 80 | __RW_START__ = . ; |
| 81 | |
Douglas Raillard | 306593d | 2017-02-24 18:14:15 +0000 | [diff] [blame] | 82 | /* |
| 83 | * .data must be placed at a lower address than the stacks if the stack |
| 84 | * protector is enabled. Alternatively, the .data.stack_protector_canary |
| 85 | * section can be placed independently of the main .data section. |
| 86 | */ |
Sandrine Bailleux | 8d69a03 | 2013-11-27 09:38:52 +0000 | [diff] [blame] | 87 | .data . : { |
| 88 | __DATA_START__ = .; |
Samuel Holland | 23f5e54 | 2019-10-20 16:11:25 -0500 | [diff] [blame] | 89 | *(SORT_BY_ALIGNMENT(.data*)) |
Sandrine Bailleux | 8d69a03 | 2013-11-27 09:38:52 +0000 | [diff] [blame] | 90 | __DATA_END__ = .; |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 91 | } >RAM |
| 92 | |
Sandrine Bailleux | 8d69a03 | 2013-11-27 09:38:52 +0000 | [diff] [blame] | 93 | stacks (NOLOAD) : { |
| 94 | __STACKS_START__ = .; |
| 95 | *(tzfw_normal_stacks) |
| 96 | __STACKS_END__ = .; |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 97 | } >RAM |
| 98 | |
Sandrine Bailleux | 8d69a03 | 2013-11-27 09:38:52 +0000 | [diff] [blame] | 99 | /* |
| 100 | * The .bss section gets initialised to 0 at runtime. |
Douglas Raillard | 21362a9 | 2016-12-02 13:51:54 +0000 | [diff] [blame] | 101 | * Its base address should be 16-byte aligned for better performance of the |
| 102 | * zero-initialization code. |
Sandrine Bailleux | 8d69a03 | 2013-11-27 09:38:52 +0000 | [diff] [blame] | 103 | */ |
| 104 | .bss : ALIGN(16) { |
| 105 | __BSS_START__ = .; |
Andrew Thoelke | e01ea34 | 2014-03-18 07:13:52 +0000 | [diff] [blame] | 106 | *(SORT_BY_ALIGNMENT(.bss*)) |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 107 | *(COMMON) |
Sandrine Bailleux | 8d69a03 | 2013-11-27 09:38:52 +0000 | [diff] [blame] | 108 | __BSS_END__ = .; |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 109 | } >RAM |
| 110 | |
Masahiro Yamada | 0b67e56 | 2020-03-09 17:39:48 +0900 | [diff] [blame] | 111 | XLAT_TABLE_SECTION >RAM |
Achin Gupta | a0cd989 | 2014-02-09 13:30:38 +0000 | [diff] [blame] | 112 | |
Soby Mathew | 2ae2043 | 2015-01-08 18:02:44 +0000 | [diff] [blame] | 113 | #if USE_COHERENT_MEM |
Achin Gupta | a0cd989 | 2014-02-09 13:30:38 +0000 | [diff] [blame] | 114 | /* |
Sandrine Bailleux | 8d69a03 | 2013-11-27 09:38:52 +0000 | [diff] [blame] | 115 | * The base address of the coherent memory section must be page-aligned (4K) |
| 116 | * to guarantee that the coherent data are stored on their own pages and |
| 117 | * are not mixed with normal data. This is required to set up the correct |
| 118 | * memory attributes for the coherent data page tables. |
| 119 | */ |
Antonio Nino Diaz | 2ce2b09 | 2017-11-15 11:45:35 +0000 | [diff] [blame] | 120 | coherent_ram (NOLOAD) : ALIGN(PAGE_SIZE) { |
Sandrine Bailleux | 8d69a03 | 2013-11-27 09:38:52 +0000 | [diff] [blame] | 121 | __COHERENT_RAM_START__ = .; |
| 122 | *(tzfw_coherent_mem) |
| 123 | __COHERENT_RAM_END_UNALIGNED__ = .; |
| 124 | /* |
| 125 | * Memory page(s) mapped to this section will be marked |
| 126 | * as device memory. No other unexpected data must creep in. |
| 127 | * Ensure the rest of the current memory page is unused. |
| 128 | */ |
Roberto Vargas | d93fde3 | 2018-04-11 11:53:31 +0100 | [diff] [blame] | 129 | . = ALIGN(PAGE_SIZE); |
Sandrine Bailleux | 8d69a03 | 2013-11-27 09:38:52 +0000 | [diff] [blame] | 130 | __COHERENT_RAM_END__ = .; |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 131 | } >RAM |
Soby Mathew | 2ae2043 | 2015-01-08 18:02:44 +0000 | [diff] [blame] | 132 | #endif |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 133 | |
Achin Gupta | e9c4a64 | 2015-09-11 16:03:13 +0100 | [diff] [blame] | 134 | /* |
| 135 | * Define a linker symbol to mark end of the RW memory area for this |
| 136 | * image. |
| 137 | */ |
| 138 | __RW_END__ = .; |
Sandrine Bailleux | 8d69a03 | 2013-11-27 09:38:52 +0000 | [diff] [blame] | 139 | __BL2_END__ = .; |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 140 | |
Sandrine Bailleux | 8d69a03 | 2013-11-27 09:38:52 +0000 | [diff] [blame] | 141 | __BSS_SIZE__ = SIZEOF(.bss); |
Soby Mathew | 2ae2043 | 2015-01-08 18:02:44 +0000 | [diff] [blame] | 142 | |
| 143 | #if USE_COHERENT_MEM |
Sandrine Bailleux | 8d69a03 | 2013-11-27 09:38:52 +0000 | [diff] [blame] | 144 | __COHERENT_RAM_UNALIGNED_SIZE__ = |
| 145 | __COHERENT_RAM_END_UNALIGNED__ - __COHERENT_RAM_START__; |
Soby Mathew | 2ae2043 | 2015-01-08 18:02:44 +0000 | [diff] [blame] | 146 | #endif |
Sandrine Bailleux | 6c8b359 | 2014-05-22 15:28:26 +0100 | [diff] [blame] | 147 | |
| 148 | ASSERT(. <= BL2_LIMIT, "BL2 image has exceeded its limit.") |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 149 | } |