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Sandrine Bailleuxacde8b02015-05-19 11:54:45 +01001/*
Jiafei Pan43a7bf42018-03-21 07:20:09 +00002 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +01003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +01005 */
6
7#ifndef __EL3_COMMON_MACROS_S__
8#define __EL3_COMMON_MACROS_S__
9
10#include <arch.h>
11#include <asm_macros.S>
12
13 /*
14 * Helper macro to initialise EL3 registers we care about.
15 */
Dimitris Papastamos446f7f12017-11-30 14:53:53 +000016 .macro el3_arch_init_common
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +010017 /* ---------------------------------------------------------------------
David Cunadofee86532017-04-13 22:38:29 +010018 * SCTLR_EL3 has already been initialised - read current value before
19 * modifying.
20 *
21 * SCTLR_EL3.I: Enable the instruction cache.
22 *
23 * SCTLR_EL3.SA: Enable Stack Aligment check. A SP alignment fault
24 * exception is generated if a load or store instruction executed at
25 * EL3 uses the SP as the base address and the SP is not aligned to a
26 * 16-byte boundary.
27 *
28 * SCTLR_EL3.A: Enable Alignment fault checking. All instructions that
29 * load or store one or more registers have an alignment check that the
30 * address being accessed is aligned to the size of the data element(s)
31 * being accessed.
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +010032 * ---------------------------------------------------------------------
33 */
34 mov x1, #(SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT)
35 mrs x0, sctlr_el3
36 orr x0, x0, x1
37 msr sctlr_el3, x0
38 isb
39
Masahiro Yamada441bfdd2016-12-25 23:36:24 +090040#ifdef IMAGE_BL31
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +010041 /* ---------------------------------------------------------------------
42 * Initialise the per-cpu cache pointer to the CPU.
43 * This is done early to enable crash reporting to have access to crash
44 * stack. Since crash reporting depends on cpu_data to report the
45 * unhandled exception, not doing so can lead to recursive exceptions
46 * due to a NULL TPIDR_EL3.
47 * ---------------------------------------------------------------------
48 */
49 bl init_cpu_data_ptr
50#endif /* IMAGE_BL31 */
51
52 /* ---------------------------------------------------------------------
David Cunadofee86532017-04-13 22:38:29 +010053 * Initialise SCR_EL3, setting all fields rather than relying on hw.
54 * All fields are architecturally UNKNOWN on reset. The following fields
55 * do not change during the TF lifetime. The remaining fields are set to
56 * zero here but are updated ahead of transitioning to a lower EL in the
57 * function cm_init_context_common().
58 *
59 * SCR_EL3.TWE: Set to zero so that execution of WFE instructions at
60 * EL2, EL1 and EL0 are not trapped to EL3.
61 *
62 * SCR_EL3.TWI: Set to zero so that execution of WFI instructions at
63 * EL2, EL1 and EL0 are not trapped to EL3.
64 *
65 * SCR_EL3.SIF: Set to one to disable instruction fetches from
66 * Non-secure memory.
67 *
68 * SCR_EL3.SMD: Set to zero to enable SMC calls at EL1 and above, from
69 * both Security states and both Execution states.
70 *
71 * SCR_EL3.EA: Set to one to route External Aborts and SError Interrupts
72 * to EL3 when executing at any EL.
Gerald Lejeune632d6df2016-03-22 09:29:23 +010073 * ---------------------------------------------------------------------
74 */
David Cunadofee86532017-04-13 22:38:29 +010075 mov x0, #((SCR_RESET_VAL | SCR_EA_BIT | SCR_SIF_BIT) \
76 & ~(SCR_TWE_BIT | SCR_TWI_BIT | SCR_SMD_BIT))
Gerald Lejeune632d6df2016-03-22 09:29:23 +010077 msr scr_el3, x0
David Cunado5f55e282016-10-31 17:37:34 +000078
79 /* ---------------------------------------------------------------------
David Cunadofee86532017-04-13 22:38:29 +010080 * Initialise MDCR_EL3, setting all fields rather than relying on hw.
81 * Some fields are architecturally UNKNOWN on reset.
82 *
83 * MDCR_EL3.SDD: Set to one to disable AArch64 Secure self-hosted debug.
84 * Debug exceptions, other than Breakpoint Instruction exceptions, are
85 * disabled from all ELs in Secure state.
86 *
87 * MDCR_EL3.SPD32: Set to 0b10 to disable AArch32 Secure self-hosted
88 * privileged debug from S-EL1.
89 *
90 * MDCR_EL3.TDOSA: Set to zero so that EL2 and EL2 System register
91 * access to the powerdown debug registers do not trap to EL3.
92 *
93 * MDCR_EL3.TDA: Set to zero to allow EL0, EL1 and EL2 access to the
94 * debug registers, other than those registers that are controlled by
95 * MDCR_EL3.TDOSA.
96 *
97 * MDCR_EL3.TPM: Set to zero so that EL0, EL1, and EL2 System register
98 * accesses to all Performance Monitors registers do not trap to EL3.
David Cunado5f55e282016-10-31 17:37:34 +000099 * ---------------------------------------------------------------------
100 */
David Cunadofee86532017-04-13 22:38:29 +0100101 mov_imm x0, ((MDCR_EL3_RESET_VAL | MDCR_SDD_BIT | MDCR_SPD32(MDCR_SPD32_DISABLE)) \
102 & ~(MDCR_TDOSA_BIT | MDCR_TDA_BIT | MDCR_TPM_BIT))
dp-arm595d0d52017-02-08 11:51:50 +0000103 msr mdcr_el3, x0
David Cunado5f55e282016-10-31 17:37:34 +0000104
Gerald Lejeune632d6df2016-03-22 09:29:23 +0100105 /* ---------------------------------------------------------------------
106 * Enable External Aborts and SError Interrupts now that the exception
107 * vectors have been setup.
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +0100108 * ---------------------------------------------------------------------
109 */
110 msr daifclr, #DAIF_ABT_BIT
111
112 /* ---------------------------------------------------------------------
David Cunadofee86532017-04-13 22:38:29 +0100113 * Initialise CPTR_EL3, setting all fields rather than relying on hw.
114 * All fields are architecturally UNKNOWN on reset.
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +0100115 *
David Cunadofee86532017-04-13 22:38:29 +0100116 * CPTR_EL3.TCPAC: Set to zero so that any accesses to CPACR_EL1,
117 * CPTR_EL2, CPACR, or HCPTR do not trap to EL3.
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +0100118 *
David Cunadofee86532017-04-13 22:38:29 +0100119 * CPTR_EL3.TTA: Set to zero so that System register accesses to the
120 * trace registers do not trap to EL3.
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +0100121 *
David Cunadoce88eee2017-10-20 11:30:57 +0100122 * CPTR_EL3.TFP: Set to zero so that accesses to the V- or Z- registers
123 * by Advanced SIMD, floating-point or SVE instructions (if implemented)
124 * do not trap to EL3.
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +0100125 */
David Cunadofee86532017-04-13 22:38:29 +0100126 mov_imm x0, (CPTR_EL3_RESET_VAL & ~(TCPAC_BIT | TTA_BIT | TFP_BIT))
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +0100127 msr cptr_el3, x0
128 .endm
129
130/* -----------------------------------------------------------------------------
131 * This is the super set of actions that need to be performed during a cold boot
Juan Castillo7d199412015-12-14 09:35:25 +0000132 * or a warm boot in EL3. This code is shared by BL1 and BL31.
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +0100133 *
134 * This macro will always perform reset handling, architectural initialisations
135 * and stack setup. The rest of the actions are optional because they might not
136 * be needed, depending on the context in which this macro is called. This is
137 * why this macro is parameterised ; each parameter allows to enable/disable
138 * some actions.
139 *
David Cunadofee86532017-04-13 22:38:29 +0100140 * _init_sctlr:
141 * Whether the macro needs to initialise SCTLR_EL3, including configuring
142 * the endianness of data accesses.
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +0100143 *
144 * _warm_boot_mailbox:
145 * Whether the macro needs to detect the type of boot (cold/warm). The
146 * detection is based on the platform entrypoint address : if it is zero
147 * then it is a cold boot, otherwise it is a warm boot. In the latter case,
148 * this macro jumps on the platform entrypoint address.
149 *
150 * _secondary_cold_boot:
151 * Whether the macro needs to identify the CPU that is calling it: primary
152 * CPU or secondary CPU. The primary CPU will be allowed to carry on with
153 * the platform initialisations, while the secondaries will be put in a
154 * platform-specific state in the meantime.
155 *
156 * If the caller knows this macro will only be called by the primary CPU
157 * then this parameter can be defined to 0 to skip this step.
158 *
159 * _init_memory:
160 * Whether the macro needs to initialise the memory.
161 *
162 * _init_c_runtime:
163 * Whether the macro needs to initialise the C runtime environment.
164 *
165 * _exception_vectors:
166 * Address of the exception vectors to program in the VBAR_EL3 register.
167 * -----------------------------------------------------------------------------
168 */
169 .macro el3_entrypoint_common \
David Cunadofee86532017-04-13 22:38:29 +0100170 _init_sctlr, _warm_boot_mailbox, _secondary_cold_boot, \
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +0100171 _init_memory, _init_c_runtime, _exception_vectors
172
David Cunadofee86532017-04-13 22:38:29 +0100173 .if \_init_sctlr
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +0100174 /* -------------------------------------------------------------
David Cunadofee86532017-04-13 22:38:29 +0100175 * This is the initialisation of SCTLR_EL3 and so must ensure
176 * that all fields are explicitly set rather than relying on hw.
177 * Some fields reset to an IMPLEMENTATION DEFINED value and
178 * others are architecturally UNKNOWN on reset.
179 *
180 * SCTLR.EE: Set the CPU endianness before doing anything that
181 * might involve memory reads or writes. Set to zero to select
182 * Little Endian.
183 *
184 * SCTLR_EL3.WXN: For the EL3 translation regime, this field can
185 * force all memory regions that are writeable to be treated as
186 * XN (Execute-never). Set to zero so that this control has no
187 * effect on memory access permissions.
188 *
189 * SCTLR_EL3.SA: Set to zero to disable Stack Aligment check.
190 *
191 * SCTLR_EL3.A: Set to zero to disable Alignment fault checking.
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +0100192 * -------------------------------------------------------------
193 */
David Cunadofee86532017-04-13 22:38:29 +0100194 mov_imm x0, (SCTLR_RESET_VAL & ~(SCTLR_EE_BIT | SCTLR_WXN_BIT \
195 | SCTLR_SA_BIT | SCTLR_A_BIT))
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +0100196 msr sctlr_el3, x0
197 isb
David Cunadofee86532017-04-13 22:38:29 +0100198 .endif /* _init_sctlr */
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +0100199
200 .if \_warm_boot_mailbox
201 /* -------------------------------------------------------------
202 * This code will be executed for both warm and cold resets.
203 * Now is the time to distinguish between the two.
204 * Query the platform entrypoint address and if it is not zero
205 * then it means it is a warm boot so jump to this address.
206 * -------------------------------------------------------------
207 */
Soby Mathew3700a922015-07-13 11:21:11 +0100208 bl plat_get_my_entrypoint
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +0100209 cbz x0, do_cold_boot
210 br x0
211
212 do_cold_boot:
213 .endif /* _warm_boot_mailbox */
214
Antonio Nino Diaz4357b412016-02-23 12:04:58 +0000215 /* ---------------------------------------------------------------------
Dimitris Papastamos446f7f12017-11-30 14:53:53 +0000216 * Set the exception vectors.
217 * ---------------------------------------------------------------------
218 */
219 adr x0, \_exception_vectors
220 msr vbar_el3, x0
221 isb
222
223 /* ---------------------------------------------------------------------
Antonio Nino Diaz4357b412016-02-23 12:04:58 +0000224 * It is a cold boot.
225 * Perform any processor specific actions upon reset e.g. cache, TLB
226 * invalidations etc.
227 * ---------------------------------------------------------------------
228 */
229 bl reset_handler
230
Dimitris Papastamos446f7f12017-11-30 14:53:53 +0000231 el3_arch_init_common
Antonio Nino Diaz4357b412016-02-23 12:04:58 +0000232
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +0100233 .if \_secondary_cold_boot
234 /* -------------------------------------------------------------
Antonio Nino Diaz4357b412016-02-23 12:04:58 +0000235 * Check if this is a primary or secondary CPU cold boot.
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +0100236 * The primary CPU will set up the platform while the
237 * secondaries are placed in a platform-specific state until the
238 * primary CPU performs the necessary actions to bring them out
239 * of that state and allows entry into the OS.
240 * -------------------------------------------------------------
241 */
Soby Mathew3700a922015-07-13 11:21:11 +0100242 bl plat_is_my_cpu_primary
Soby Matheweb3bbf12015-06-08 12:32:50 +0100243 cbnz w0, do_primary_cold_boot
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +0100244
245 /* This is a cold boot on a secondary CPU */
246 bl plat_secondary_cold_boot_setup
247 /* plat_secondary_cold_boot_setup() is not supposed to return */
Antonio Nino Diaz1f21bcf2016-02-01 13:57:25 +0000248 bl el3_panic
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +0100249
250 do_primary_cold_boot:
251 .endif /* _secondary_cold_boot */
252
253 /* ---------------------------------------------------------------------
Antonio Nino Diaz4357b412016-02-23 12:04:58 +0000254 * Initialize memory now. Secondary CPU initialization won't get to this
255 * point.
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +0100256 * ---------------------------------------------------------------------
257 */
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +0100258
259 .if \_init_memory
260 bl platform_mem_init
261 .endif /* _init_memory */
262
263 /* ---------------------------------------------------------------------
264 * Init C runtime environment:
265 * - Zero-initialise the NOBITS sections. There are 2 of them:
266 * - the .bss section;
267 * - the coherent memory section (if any).
268 * - Relocate the data section from ROM to RAM, if required.
269 * ---------------------------------------------------------------------
270 */
271 .if \_init_c_runtime
Roberto Vargase0e99462017-10-30 14:43:43 +0000272#if defined(IMAGE_BL31) || (defined(IMAGE_BL2) && BL2_AT_EL3)
Achin Guptae9c4a642015-09-11 16:03:13 +0100273 /* -------------------------------------------------------------
274 * Invalidate the RW memory used by the BL31 image. This
275 * includes the data and NOBITS sections. This is done to
276 * safeguard against possible corruption of this memory by
277 * dirty cache lines in a system cache as a result of use by
278 * an earlier boot loader stage.
279 * -------------------------------------------------------------
280 */
Jiafei Pan54f5d672018-03-27 23:00:55 +0800281 ldr x0, =__RW_START__
282 ldr x1, =__RW_END__
Achin Guptae9c4a642015-09-11 16:03:13 +0100283 sub x1, x1, x0
284 bl inv_dcache_range
Roberto Vargase0e99462017-10-30 14:43:43 +0000285#endif
Achin Guptae9c4a642015-09-11 16:03:13 +0100286
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +0100287 ldr x0, =__BSS_START__
288 ldr x1, =__BSS_SIZE__
Douglas Raillard21362a92016-12-02 13:51:54 +0000289 bl zeromem
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +0100290
291#if USE_COHERENT_MEM
292 ldr x0, =__COHERENT_RAM_START__
293 ldr x1, =__COHERENT_RAM_UNALIGNED_SIZE__
Douglas Raillard21362a92016-12-02 13:51:54 +0000294 bl zeromem
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +0100295#endif
296
Jiafei Pan43a7bf42018-03-21 07:20:09 +0000297#if defined(IMAGE_BL1) || (defined(IMAGE_BL2) && BL2_IN_XIP_MEM)
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +0100298 ldr x0, =__DATA_RAM_START__
299 ldr x1, =__DATA_ROM_START__
300 ldr x2, =__DATA_SIZE__
301 bl memcpy16
302#endif
303 .endif /* _init_c_runtime */
304
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +0100305 /* ---------------------------------------------------------------------
306 * Use SP_EL0 for the C runtime stack.
307 * ---------------------------------------------------------------------
308 */
309 msr spsel, #0
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +0100310
311 /* ---------------------------------------------------------------------
312 * Allocate a stack whose memory will be marked as Normal-IS-WBWA when
313 * the MMU is enabled. There is no risk of reading stale stack memory
314 * after enabling the MMU as only the primary CPU is running at the
315 * moment.
316 * ---------------------------------------------------------------------
317 */
Soby Mathew3700a922015-07-13 11:21:11 +0100318 bl plat_set_my_stack
Douglas Raillard306593d2017-02-24 18:14:15 +0000319
320#if STACK_PROTECTOR_ENABLED
321 .if \_init_c_runtime
322 bl update_stack_protector_canary
323 .endif /* _init_c_runtime */
324#endif
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +0100325 .endm
326
327#endif /* __EL3_COMMON_MACROS_S__ */