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Paul Beesleyea225122019-02-11 17:54:45 +00001Trusted Firmware-A Documentation
2================================
Paul Beesley22994f72019-01-23 15:39:39 +00003
4.. toctree::
5 :maxdepth: 1
Paul Beesleya8790092019-03-07 17:03:22 +00006 :hidden:
Paul Beesley22994f72019-01-23 15:39:39 +00007
Paul Beesleycb238022019-03-07 15:25:14 +00008 Home<self>
Paul Beesleyea225122019-02-11 17:54:45 +00009 getting_started/index
10 process/index
11 components/index
12 design/index
13 plat/index
14 perf/index
15 security_advisories/index
Paul Beesley22994f72019-01-23 15:39:39 +000016 change-log
Paul Beesleyea225122019-02-11 17:54:45 +000017 acknowledgements
Paul Beesley606d8072019-03-13 13:58:02 +000018 glossary
Paul Beesleyfc9ee362019-03-07 15:47:15 +000019 maintainers
Paul Beesleycb238022019-03-07 15:25:14 +000020 license
Paul Beesley22994f72019-01-23 15:39:39 +000021
Paul Beesleya8790092019-03-07 17:03:22 +000022.. contents:: On This Page
23 :depth: 3
24
Paul Beesleycb238022019-03-07 15:25:14 +000025Trusted Firmware-A (TF-A) provides a reference implementation of secure world
26software for `Armv7-A and Armv8-A`_, including a `Secure Monitor`_ executing
27at Exception Level 3 (EL3). It implements various Arm interface standards,
28such as:
29
30- The `Power State Coordination Interface (PSCI)`_
31- `Trusted Board Boot Requirements CLIENT (TBBR-CLIENT)`_
32- `SMC Calling Convention`_
33- `System Control and Management Interface (SCMI)`_
34- `Software Delegated Exception Interface (SDEI)`_
35
36Where possible, the code is designed for reuse or porting to other Armv7-A and
37Armv8-A model and hardware platforms.
38
39This release provides a suitable starting point for productization of secure
40world boot and runtime firmware, in either the AArch32 or AArch64 execution
41states.
42
43Users are encouraged to do their own security validation, including penetration
44testing, on any secure world code derived from TF-A.
45
46Arm will continue development in collaboration with interested parties to
47provide a full reference implementation of Secure Monitor code and Arm standards
48to the benefit of all developers working with Armv7-A and Armv8-A TrustZone
49technology.
50
51Functionality
52-------------
53
54- Initialization of the secure world, for example exception vectors, control
55 registers and interrupts for the platform.
56
57- Library support for CPU specific reset and power down sequences. This
58 includes support for errata workarounds and the latest Arm DynamIQ CPUs.
59
60- Drivers to enable standard initialization of Arm System IP, for example
61 Generic Interrupt Controller (GIC), Cache Coherent Interconnect (CCI),
62 Cache Coherent Network (CCN), Network Interconnect (NIC) and TrustZone
63 Controller (TZC).
64
65- A generic `SCMI`_ driver to interface with conforming power controllers, for
66 example the Arm System Control Processor (SCP).
67
68- SMC (Secure Monitor Call) handling, conforming to the `SMC Calling
69 Convention`_ using an EL3 runtime services framework.
70
71- `PSCI`_ library support for CPU, cluster and system power management
72 use-cases.
73 This library is pre-integrated with the AArch64 EL3 Runtime Software, and
74 is also suitable for integration with other AArch32 EL3 Runtime Software,
75 for example an AArch32 Secure OS.
76
77- A minimal AArch32 Secure Payload (SP\_MIN) to demonstrate `PSCI`_ library
78 integration with AArch32 EL3 Runtime Software.
79
80- Secure Monitor library code such as world switching, EL1 context management
81 and interrupt routing.
82 When a Secure-EL1 Payload (SP) is present, for example a Secure OS, the
83 AArch64 EL3 Runtime Software must be integrated with a Secure Payload
84 Dispatcher (SPD) component to customize the interaction with the SP.
85
86- A Test SP and SPD to demonstrate AArch64 Secure Monitor functionality and SP
87 interaction with PSCI.
88
89- SPDs for the `OP-TEE Secure OS`_, `NVIDIA Trusted Little Kernel`_
90 and `Trusty Secure OS`_.
91
92- A Trusted Board Boot implementation, conforming to all mandatory TBBR
93 requirements. This includes image authentication, Firmware Update (or
94 recovery mode), and packaging of the various firmware images into a
95 Firmware Image Package (FIP).
96
97- Pre-integration of TBB with the Arm CryptoCell product, to take advantage of
98 its hardware Root of Trust and crypto acceleration services.
99
100- Reliability, Availability, and Serviceability (RAS) functionality, including
101
102 - A Secure Partition Manager (SPM) to manage Secure Partitions in
103 Secure-EL0, which can be used to implement simple management and
104 security services.
105
Paul Beesley606d8072019-03-13 13:58:02 +0000106 - An |SDEI| dispatcher to route interrupt-based |SDEI| events.
Paul Beesleycb238022019-03-07 15:25:14 +0000107
108 - An Exception Handling Framework (EHF) that allows dispatching of EL3
109 interrupts to their registered handlers, to facilitate firmware-first
110 error handling.
111
112- A dynamic configuration framework that enables each of the firmware images
113 to be configured at runtime if required by the platform. It also enables
114 loading of a hardware configuration (for example, a kernel device tree)
115 as part of the FIP, to be passed through the firmware stages.
116
117- Support for alternative boot flows, for example to support platforms where
118 the EL3 Runtime Software is loaded using other firmware or a separate
119 secure system processor, or where a non-TF-A ROM expects BL2 to be loaded
120 at EL3.
121
122- Support for the GCC, LLVM and Arm Compiler 6 toolchains.
123
124- Support for combining several libraries into a "romlib" image that may be
125 shared across images to reduce memory footprint. The romlib image is stored
126 in ROM but is accessed through a jump-table that may be stored
127 in read-write memory, allowing for the library code to be patched.
128
129- A prototype implementation of a Secure Partition Manager (SPM) that is based
130 on the SPCI Alpha 1 and SPRT draft specifications.
131
132- Support for ARMv8.3 pointer authentication in the normal and secure worlds.
133 The use of pointer authentication in the normal world is enabled whenever
134 architectural support is available, without the need for additional build
135 flags. Use of pointer authentication in the secure world remains an
136 experimental configuration at this time and requires the ``ENABLE_PAUTH``
137 build flag to be set.
138
139- Position-Independent Executable (PIE) support. Initially for BL31 only, with
140 further support to be added in a future release.
141
142For a full description of functionality and implementation details, please
143see the `Firmware Design`_ and supporting documentation. The `Change Log`_
144provides details of changes made since the last release.
145
146Platforms
147---------
148
149Various AArch32 and AArch64 builds of this release have been tested on r0, r1
150and r2 variants of the `Juno Arm Development Platform`_.
151
152The latest version of the AArch64 build of TF-A has been tested on the following
153Arm FVPs without shifted affinities, and that do not support threaded CPU cores
154(64-bit host machine only).
155
Paul Beesleyba3ed402019-03-13 16:20:44 +0000156.. note::
157 The FVP models used are Version 11.5 Build 33, unless otherwise stated.
Paul Beesleycb238022019-03-07 15:25:14 +0000158
159- ``FVP_Base_AEMv8A-AEMv8A``
160- ``FVP_Base_AEMv8A-AEMv8A-AEMv8A-AEMv8A-CCN502``
161- ``FVP_Base_RevC-2xAEMv8A``
162- ``FVP_Base_Cortex-A32x4``
163- ``FVP_Base_Cortex-A35x4``
164- ``FVP_Base_Cortex-A53x4``
165- ``FVP_Base_Cortex-A55x4+Cortex-A75x4``
166- ``FVP_Base_Cortex-A55x4``
167- ``FVP_Base_Cortex-A57x1-A53x1``
168- ``FVP_Base_Cortex-A57x2-A53x4``
169- ``FVP_Base_Cortex-A57x4-A53x4``
170- ``FVP_Base_Cortex-A57x4``
171- ``FVP_Base_Cortex-A72x4-A53x4``
172- ``FVP_Base_Cortex-A72x4``
173- ``FVP_Base_Cortex-A73x4-A53x4``
174- ``FVP_Base_Cortex-A73x4``
175- ``FVP_Base_Cortex-A75x4``
176- ``FVP_Base_Cortex-A76x4``
177- ``FVP_Base_Cortex-A76AEx4`` (Tested with internal model)
178- ``FVP_Base_Cortex-A76AEx8`` (Tested with internal model)
179- ``FVP_Base_Neoverse-N1x4`` (Tested with internal model)
180- ``FVP_Base_Deimos``
181- ``FVP_CSS_SGI-575`` (Version 11.3 build 42)
182- ``FVP_CSS_SGM-775`` (Version 11.3 build 42)
183- ``FVP_RD_E1Edge`` (Version 11.3 build 42)
184- ``FVP_RD_N1Edge`` (Version 11.3 build 42)
185- ``Foundation_Platform``
186
187The latest version of the AArch32 build of TF-A has been tested on the following
188Arm FVPs without shifted affinities, and that do not support threaded CPU cores
189(64-bit host machine only).
190
191- ``FVP_Base_AEMv8A-AEMv8A``
192- ``FVP_Base_Cortex-A32x4``
193
Paul Beesleyba3ed402019-03-13 16:20:44 +0000194.. note::
195 The ``FVP_Base_RevC-2xAEMv8A`` FVP only supports shifted affinities.
Paul Beesleycb238022019-03-07 15:25:14 +0000196
197The Foundation FVP can be downloaded free of charge. The Base FVPs can be
198licensed from Arm. See the `Arm FVP website`_.
199
200All the above platforms have been tested with `Linaro Release 18.04`_.
201
202This release also contains the following platform support:
203
204- Allwinner sun50i_a64 and sun50i_h6
205- Amlogic Meson S905 (GXBB)
206- Arm Juno Software Development Platform
207- Arm Neoverse N1 System Development Platform (N1SDP)
208- Arm Neoverse Reference Design N1 Edge (RD-N1-Edge) FVP
209- Arm Neoverse Reference Design E1 Edge (RD-E1-Edge) FVP
210- Arm SGI-575 and SGM-775
211- Arm Versatile Express FVP
212- HiKey, HiKey960 and Poplar boards
213- Intel Stratix 10 SoC FPGA
214- Marvell Armada 3700 and 8K
215- MediaTek MT6795 and MT8173 SoCs
216- NVIDIA T132, T186 and T210 SoCs
217- NXP QorIQ LS1043A, i.MX8MM, i.MX8MQ, i.MX8QX, i.MX8QM and i.MX7Solo WaRP7
218- QEMU
219- Raspberry Pi 3
220- Renesas R-Car Generation 3
221- RockChip RK3328, RK3368 and RK3399 SoCs
222- Socionext UniPhier SoC family and SynQuacer SC2A11 SoCs
223- STMicroelectronics STM32MP1
224- Texas Instruments K3 SoCs
225- Xilinx Versal and Zynq UltraScale + MPSoC
226
227Still to come
228-------------
229
230- Support for additional platforms.
231
232- Refinements to Position Independent Executable (PIE) support.
233
234- Refinements to the SPCI-based SPM implementation as the draft SPCI and SPRT
235 specifications continue to evolve.
236
237- Documentation enhancements.
238
239- Ongoing support for new architectural features, CPUs and System IP.
240
241- Ongoing support for new Arm system architecture specifications.
242
243- Ongoing security hardening, optimization and quality improvements.
244
245For a full list of detailed issues in the current code, please see the `Change
246Log`_ and the `issue tracker`_.
247
248Getting started
249---------------
250
251See the `User Guide`_ for instructions on how to download, install, build and
252use TF-A with the Arm `FVP`_\ s.
253
254See the `Firmware Design`_ for information on how TF-A works.
255
256See the `Porting Guide`_ as well for information about how to use this
257software on another Armv7-A or Armv8-A platform.
258
259See the `Contributing Guidelines`_ for information on how to contribute to this
260project and the `Acknowledgments`_ file for a list of contributors to the
261project.
262
John Tsichritzis3c57cb02019-06-03 10:51:22 +0100263Contact us
264~~~~~~~~~~
Paul Beesleycb238022019-03-07 15:25:14 +0000265
John Tsichritzis3c57cb02019-06-03 10:51:22 +0100266We welcome any feedback on TF-A. If you think you have found a security
Paul Beesleycb238022019-03-07 15:25:14 +0000267vulnerability, please report this using the process defined in the TF-A
John Tsichritzis3c57cb02019-06-03 10:51:22 +0100268`Security Center`_. For all other feedback, you can use either the
269`issue tracker`_ or our `mailing list`_.
Paul Beesleycb238022019-03-07 15:25:14 +0000270
271Arm licensees may contact Arm directly via their partner managers.
272
273--------------
274
275*Copyright (c) 2013-2019, Arm Limited and Contributors. All rights reserved.*
Paul Beesley22994f72019-01-23 15:39:39 +0000276
Paul Beesleycb238022019-03-07 15:25:14 +0000277.. _Armv7-A and Armv8-A: https://developer.arm.com/products/architecture/a-profile
278.. _Secure Monitor: http://www.arm.com/products/processors/technologies/trustzone/tee-smc.php
279.. _Power State Coordination Interface (PSCI): PSCI_
280.. _PSCI: http://infocenter.arm.com/help/topic/com.arm.doc.den0022d/Power_State_Coordination_Interface_PDD_v1_1_DEN0022D.pdf
281.. _Trusted Board Boot Requirements CLIENT (TBBR-CLIENT): https://developer.arm.com/docs/den0006/latest/trusted-board-boot-requirements-client-tbbr-client-armv8-a
282.. _SMC Calling Convention: http://infocenter.arm.com/help/topic/com.arm.doc.den0028b/ARM_DEN0028B_SMC_Calling_Convention.pdf
283.. _System Control and Management Interface (SCMI): SCMI_
284.. _SCMI: http://infocenter.arm.com/help/topic/com.arm.doc.den0056a/DEN0056A_System_Control_and_Management_Interface.pdf
285.. _Software Delegated Exception Interface (SDEI): SDEI_
286.. _SDEI: http://infocenter.arm.com/help/topic/com.arm.doc.den0054a/ARM_DEN0054A_Software_Delegated_Exception_Interface.pdf
287.. _Juno Arm Development Platform: http://www.arm.com/products/tools/development-boards/versatile-express/juno-arm-development-platform.php
288.. _Arm FVP website: FVP_
289.. _FVP: https://developer.arm.com/products/system-design/fixed-virtual-platforms
290.. _Linaro Release 18.04: https://community.arm.com/dev-platforms/b/documents/posts/linaro-release-notes-deprecated#LinaroRelease18.04
291.. _OP-TEE Secure OS: https://github.com/OP-TEE/optee_os
292.. _NVIDIA Trusted Little Kernel: http://nv-tegra.nvidia.com/gitweb/?p=3rdparty/ote_partner/tlk.git;a=summary
293.. _Trusty Secure OS: https://source.android.com/security/trusty
294.. _trustedfirmware.org: https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git
295.. _issue tracker: https://issues.trustedfirmware.org
John Tsichritzis3c57cb02019-06-03 10:51:22 +0100296.. _mailing list: https://lists.trustedfirmware.org/mailman/listinfo/tf-a
John Tsichritzis2fd3d922019-05-28 13:13:39 +0100297.. _Security Center: ./process/security.rst
Paul Beesleycb238022019-03-07 15:25:14 +0000298.. _license: ./license.rst
John Tsichritzis2fd3d922019-05-28 13:13:39 +0100299.. _Contributing Guidelines: ./process/contributing.rst
Paul Beesleycb238022019-03-07 15:25:14 +0000300.. _Acknowledgments: ./acknowledgements.rst
John Tsichritzis2fd3d922019-05-28 13:13:39 +0100301.. _Firmware Design: ./design/firmware-design.rst
302.. _Change Log: ./change-log.rst
303.. _User Guide: ./getting_started/user-guide.rst
304.. _Porting Guide: ./getting_started/porting-guide.rst