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Paul Beesleyea225122019-02-11 17:54:45 +00001Trusted Firmware-A Documentation
2================================
Paul Beesley22994f72019-01-23 15:39:39 +00003
4.. toctree::
5 :maxdepth: 1
Paul Beesleya8790092019-03-07 17:03:22 +00006 :hidden:
Paul Beesley22994f72019-01-23 15:39:39 +00007
Paul Beesleycb238022019-03-07 15:25:14 +00008 Home<self>
Paul Beesleyea225122019-02-11 17:54:45 +00009 getting_started/index
10 process/index
11 components/index
12 design/index
13 plat/index
14 perf/index
15 security_advisories/index
Paul Beesley22994f72019-01-23 15:39:39 +000016 change-log
Paul Beesleyea225122019-02-11 17:54:45 +000017 acknowledgements
Paul Beesley606d8072019-03-13 13:58:02 +000018 glossary
Paul Beesleyfc9ee362019-03-07 15:47:15 +000019 maintainers
Paul Beesleycb238022019-03-07 15:25:14 +000020 license
Paul Beesley22994f72019-01-23 15:39:39 +000021
Paul Beesleya8790092019-03-07 17:03:22 +000022.. contents:: On This Page
23 :depth: 3
24
Paul Beesleycb238022019-03-07 15:25:14 +000025Trusted Firmware-A (TF-A) provides a reference implementation of secure world
26software for `Armv7-A and Armv8-A`_, including a `Secure Monitor`_ executing
27at Exception Level 3 (EL3). It implements various Arm interface standards,
28such as:
29
30- The `Power State Coordination Interface (PSCI)`_
31- `Trusted Board Boot Requirements CLIENT (TBBR-CLIENT)`_
32- `SMC Calling Convention`_
33- `System Control and Management Interface (SCMI)`_
34- `Software Delegated Exception Interface (SDEI)`_
35
36Where possible, the code is designed for reuse or porting to other Armv7-A and
37Armv8-A model and hardware platforms.
38
39This release provides a suitable starting point for productization of secure
40world boot and runtime firmware, in either the AArch32 or AArch64 execution
41states.
42
43Users are encouraged to do their own security validation, including penetration
44testing, on any secure world code derived from TF-A.
45
46Arm will continue development in collaboration with interested parties to
47provide a full reference implementation of Secure Monitor code and Arm standards
48to the benefit of all developers working with Armv7-A and Armv8-A TrustZone
49technology.
50
51Functionality
52-------------
53
54- Initialization of the secure world, for example exception vectors, control
55 registers and interrupts for the platform.
56
57- Library support for CPU specific reset and power down sequences. This
58 includes support for errata workarounds and the latest Arm DynamIQ CPUs.
59
60- Drivers to enable standard initialization of Arm System IP, for example
61 Generic Interrupt Controller (GIC), Cache Coherent Interconnect (CCI),
62 Cache Coherent Network (CCN), Network Interconnect (NIC) and TrustZone
63 Controller (TZC).
64
65- A generic `SCMI`_ driver to interface with conforming power controllers, for
66 example the Arm System Control Processor (SCP).
67
68- SMC (Secure Monitor Call) handling, conforming to the `SMC Calling
69 Convention`_ using an EL3 runtime services framework.
70
71- `PSCI`_ library support for CPU, cluster and system power management
72 use-cases.
73 This library is pre-integrated with the AArch64 EL3 Runtime Software, and
74 is also suitable for integration with other AArch32 EL3 Runtime Software,
75 for example an AArch32 Secure OS.
76
77- A minimal AArch32 Secure Payload (SP\_MIN) to demonstrate `PSCI`_ library
78 integration with AArch32 EL3 Runtime Software.
79
80- Secure Monitor library code such as world switching, EL1 context management
81 and interrupt routing.
82 When a Secure-EL1 Payload (SP) is present, for example a Secure OS, the
83 AArch64 EL3 Runtime Software must be integrated with a Secure Payload
84 Dispatcher (SPD) component to customize the interaction with the SP.
85
86- A Test SP and SPD to demonstrate AArch64 Secure Monitor functionality and SP
87 interaction with PSCI.
88
89- SPDs for the `OP-TEE Secure OS`_, `NVIDIA Trusted Little Kernel`_
90 and `Trusty Secure OS`_.
91
92- A Trusted Board Boot implementation, conforming to all mandatory TBBR
93 requirements. This includes image authentication, Firmware Update (or
94 recovery mode), and packaging of the various firmware images into a
95 Firmware Image Package (FIP).
96
97- Pre-integration of TBB with the Arm CryptoCell product, to take advantage of
98 its hardware Root of Trust and crypto acceleration services.
99
100- Reliability, Availability, and Serviceability (RAS) functionality, including
101
102 - A Secure Partition Manager (SPM) to manage Secure Partitions in
103 Secure-EL0, which can be used to implement simple management and
104 security services.
105
Paul Beesley606d8072019-03-13 13:58:02 +0000106 - An |SDEI| dispatcher to route interrupt-based |SDEI| events.
Paul Beesleycb238022019-03-07 15:25:14 +0000107
108 - An Exception Handling Framework (EHF) that allows dispatching of EL3
109 interrupts to their registered handlers, to facilitate firmware-first
110 error handling.
111
112- A dynamic configuration framework that enables each of the firmware images
113 to be configured at runtime if required by the platform. It also enables
114 loading of a hardware configuration (for example, a kernel device tree)
115 as part of the FIP, to be passed through the firmware stages.
116
117- Support for alternative boot flows, for example to support platforms where
118 the EL3 Runtime Software is loaded using other firmware or a separate
119 secure system processor, or where a non-TF-A ROM expects BL2 to be loaded
120 at EL3.
121
122- Support for the GCC, LLVM and Arm Compiler 6 toolchains.
123
124- Support for combining several libraries into a "romlib" image that may be
125 shared across images to reduce memory footprint. The romlib image is stored
126 in ROM but is accessed through a jump-table that may be stored
127 in read-write memory, allowing for the library code to be patched.
128
129- A prototype implementation of a Secure Partition Manager (SPM) that is based
130 on the SPCI Alpha 1 and SPRT draft specifications.
131
132- Support for ARMv8.3 pointer authentication in the normal and secure worlds.
133 The use of pointer authentication in the normal world is enabled whenever
134 architectural support is available, without the need for additional build
135 flags. Use of pointer authentication in the secure world remains an
136 experimental configuration at this time and requires the ``ENABLE_PAUTH``
137 build flag to be set.
138
139- Position-Independent Executable (PIE) support. Initially for BL31 only, with
140 further support to be added in a future release.
141
142For a full description of functionality and implementation details, please
143see the `Firmware Design`_ and supporting documentation. The `Change Log`_
144provides details of changes made since the last release.
145
146Platforms
147---------
148
149Various AArch32 and AArch64 builds of this release have been tested on r0, r1
150and r2 variants of the `Juno Arm Development Platform`_.
151
152The latest version of the AArch64 build of TF-A has been tested on the following
153Arm FVPs without shifted affinities, and that do not support threaded CPU cores
154(64-bit host machine only).
155
156The FVP models used are Version 11.5 Build 33, unless otherwise stated.
157
158- ``FVP_Base_AEMv8A-AEMv8A``
159- ``FVP_Base_AEMv8A-AEMv8A-AEMv8A-AEMv8A-CCN502``
160- ``FVP_Base_RevC-2xAEMv8A``
161- ``FVP_Base_Cortex-A32x4``
162- ``FVP_Base_Cortex-A35x4``
163- ``FVP_Base_Cortex-A53x4``
164- ``FVP_Base_Cortex-A55x4+Cortex-A75x4``
165- ``FVP_Base_Cortex-A55x4``
166- ``FVP_Base_Cortex-A57x1-A53x1``
167- ``FVP_Base_Cortex-A57x2-A53x4``
168- ``FVP_Base_Cortex-A57x4-A53x4``
169- ``FVP_Base_Cortex-A57x4``
170- ``FVP_Base_Cortex-A72x4-A53x4``
171- ``FVP_Base_Cortex-A72x4``
172- ``FVP_Base_Cortex-A73x4-A53x4``
173- ``FVP_Base_Cortex-A73x4``
174- ``FVP_Base_Cortex-A75x4``
175- ``FVP_Base_Cortex-A76x4``
176- ``FVP_Base_Cortex-A76AEx4`` (Tested with internal model)
177- ``FVP_Base_Cortex-A76AEx8`` (Tested with internal model)
178- ``FVP_Base_Neoverse-N1x4`` (Tested with internal model)
179- ``FVP_Base_Deimos``
180- ``FVP_CSS_SGI-575`` (Version 11.3 build 42)
181- ``FVP_CSS_SGM-775`` (Version 11.3 build 42)
182- ``FVP_RD_E1Edge`` (Version 11.3 build 42)
183- ``FVP_RD_N1Edge`` (Version 11.3 build 42)
184- ``Foundation_Platform``
185
186The latest version of the AArch32 build of TF-A has been tested on the following
187Arm FVPs without shifted affinities, and that do not support threaded CPU cores
188(64-bit host machine only).
189
190- ``FVP_Base_AEMv8A-AEMv8A``
191- ``FVP_Base_Cortex-A32x4``
192
193NOTE: The ``FVP_Base_RevC-2xAEMv8A`` FVP only supports shifted affinities.
194
195The Foundation FVP can be downloaded free of charge. The Base FVPs can be
196licensed from Arm. See the `Arm FVP website`_.
197
198All the above platforms have been tested with `Linaro Release 18.04`_.
199
200This release also contains the following platform support:
201
202- Allwinner sun50i_a64 and sun50i_h6
203- Amlogic Meson S905 (GXBB)
204- Arm Juno Software Development Platform
205- Arm Neoverse N1 System Development Platform (N1SDP)
206- Arm Neoverse Reference Design N1 Edge (RD-N1-Edge) FVP
207- Arm Neoverse Reference Design E1 Edge (RD-E1-Edge) FVP
208- Arm SGI-575 and SGM-775
209- Arm Versatile Express FVP
210- HiKey, HiKey960 and Poplar boards
211- Intel Stratix 10 SoC FPGA
212- Marvell Armada 3700 and 8K
213- MediaTek MT6795 and MT8173 SoCs
214- NVIDIA T132, T186 and T210 SoCs
215- NXP QorIQ LS1043A, i.MX8MM, i.MX8MQ, i.MX8QX, i.MX8QM and i.MX7Solo WaRP7
216- QEMU
217- Raspberry Pi 3
218- Renesas R-Car Generation 3
219- RockChip RK3328, RK3368 and RK3399 SoCs
220- Socionext UniPhier SoC family and SynQuacer SC2A11 SoCs
221- STMicroelectronics STM32MP1
222- Texas Instruments K3 SoCs
223- Xilinx Versal and Zynq UltraScale + MPSoC
224
225Still to come
226-------------
227
228- Support for additional platforms.
229
230- Refinements to Position Independent Executable (PIE) support.
231
232- Refinements to the SPCI-based SPM implementation as the draft SPCI and SPRT
233 specifications continue to evolve.
234
235- Documentation enhancements.
236
237- Ongoing support for new architectural features, CPUs and System IP.
238
239- Ongoing support for new Arm system architecture specifications.
240
241- Ongoing security hardening, optimization and quality improvements.
242
243For a full list of detailed issues in the current code, please see the `Change
244Log`_ and the `issue tracker`_.
245
246Getting started
247---------------
248
249See the `User Guide`_ for instructions on how to download, install, build and
250use TF-A with the Arm `FVP`_\ s.
251
252See the `Firmware Design`_ for information on how TF-A works.
253
254See the `Porting Guide`_ as well for information about how to use this
255software on another Armv7-A or Armv8-A platform.
256
257See the `Contributing Guidelines`_ for information on how to contribute to this
258project and the `Acknowledgments`_ file for a list of contributors to the
259project.
260
261IRC channel
262~~~~~~~~~~~
263
264Development discussion takes place on the #trusted-firmware-a channel
265on the Freenode IRC network. This is not an official support channel.
266If you have an issue to raise, please use the `issue tracker`_.
267
268Feedback and support
269~~~~~~~~~~~~~~~~~~~~
270
271Arm welcomes any feedback on TF-A. If you think you have found a security
272vulnerability, please report this using the process defined in the TF-A
273`Security Center`_. For all other feedback, please use the
274`issue tracker`_.
275
276Arm licensees may contact Arm directly via their partner managers.
277
278--------------
279
280*Copyright (c) 2013-2019, Arm Limited and Contributors. All rights reserved.*
Paul Beesley22994f72019-01-23 15:39:39 +0000281
Paul Beesleycb238022019-03-07 15:25:14 +0000282.. _Armv7-A and Armv8-A: https://developer.arm.com/products/architecture/a-profile
283.. _Secure Monitor: http://www.arm.com/products/processors/technologies/trustzone/tee-smc.php
284.. _Power State Coordination Interface (PSCI): PSCI_
285.. _PSCI: http://infocenter.arm.com/help/topic/com.arm.doc.den0022d/Power_State_Coordination_Interface_PDD_v1_1_DEN0022D.pdf
286.. _Trusted Board Boot Requirements CLIENT (TBBR-CLIENT): https://developer.arm.com/docs/den0006/latest/trusted-board-boot-requirements-client-tbbr-client-armv8-a
287.. _SMC Calling Convention: http://infocenter.arm.com/help/topic/com.arm.doc.den0028b/ARM_DEN0028B_SMC_Calling_Convention.pdf
288.. _System Control and Management Interface (SCMI): SCMI_
289.. _SCMI: http://infocenter.arm.com/help/topic/com.arm.doc.den0056a/DEN0056A_System_Control_and_Management_Interface.pdf
290.. _Software Delegated Exception Interface (SDEI): SDEI_
291.. _SDEI: http://infocenter.arm.com/help/topic/com.arm.doc.den0054a/ARM_DEN0054A_Software_Delegated_Exception_Interface.pdf
292.. _Juno Arm Development Platform: http://www.arm.com/products/tools/development-boards/versatile-express/juno-arm-development-platform.php
293.. _Arm FVP website: FVP_
294.. _FVP: https://developer.arm.com/products/system-design/fixed-virtual-platforms
295.. _Linaro Release 18.04: https://community.arm.com/dev-platforms/b/documents/posts/linaro-release-notes-deprecated#LinaroRelease18.04
296.. _OP-TEE Secure OS: https://github.com/OP-TEE/optee_os
297.. _NVIDIA Trusted Little Kernel: http://nv-tegra.nvidia.com/gitweb/?p=3rdparty/ote_partner/tlk.git;a=summary
298.. _Trusty Secure OS: https://source.android.com/security/trusty
299.. _trustedfirmware.org: https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git
300.. _issue tracker: https://issues.trustedfirmware.org
301.. _Security Center: ./docs/security-center.rst
302.. _license: ./license.rst
303.. _Contributing Guidelines: ./contributing.rst
304.. _Acknowledgments: ./acknowledgements.rst
305.. _Firmware Design: ./docs/firmware-design.rst
306.. _Change Log: ./docs/change-log.rst
307.. _User Guide: ./docs/user-guide.rst
308.. _Porting Guide: ./docs/porting-guide.rst
309.. _FreeBSD: http://www.freebsd.org
310.. _SCC: http://www.simple-cc.org/
311.. _Security Advisory TFV-1: ./docs/security_advisories/security-advisory-tfv-1.rst
312.. _Security Advisory TFV-2: ./docs/security_advisories/security-advisory-tfv-2.rst
313.. _Security Advisory TFV-3: ./docs/security_advisories/security-advisory-tfv-3.rst
314.. _Security Advisory TFV-4: ./docs/security_advisories/security-advisory-tfv-4.rst
315.. _Security Advisory TFV-5: ./docs/security_advisories/security-advisory-tfv-5.rst
316.. _Security Advisory TFV-6: ./docs/security_advisories/security-advisory-tfv-6.rst
317.. _Security Advisory TFV-7: ./docs/security_advisories/security-advisory-tfv-7.rst
318.. _Security Advisory TFV-8: ./docs/security_advisories/security-advisory-tfv-8.rst