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git01.mediatek.com / filogic / atf / 523e86451e6d7206f9851c06f2c976354cac9cc4 / . / plat / rockchip / rk3399 / drivers / dram / dram.h
blob: 5572b161236c13e9a2d16b2dd5746d8c87957f2f [file] [log] [blame]
Caesar Wang9740bba2016-08-25 08:37:42 +0800[diff] [blame]1/*
2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
3 *
dp-armfa3cf0b2017-05-03 09:38:09 +0100[diff] [blame]4 * SPDX-License-Identifier: BSD-3-Clause
Caesar Wang9740bba2016-08-25 08:37:42 +0800[diff] [blame]5 */
6
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +0000[diff] [blame]7#ifndef DRAM_H
8#define DRAM_H
Xing Zhengb4bcc1d2017-02-24 16:26:11 +0800[diff] [blame]9
Antonio Nino Diaze0f90632018-12-14 00:18:21 +0000[diff] [blame]10#include <stdint.h>
11
Xing Zhengb4bcc1d2017-02-24 16:26:11 +0800[diff] [blame]12#include <dram_regs.h>
Caesar Wanga8456902016-10-27 01:12:34 +0800[diff] [blame]13#include <plat_private.h>
Caesar Wang9740bba2016-08-25 08:37:42 +0800[diff] [blame]14
Caesar Wanga8456902016-10-27 01:12:34 +0800[diff] [blame]15enum {
16 DDR3 = 3,
17 LPDDR2 = 5,
18 LPDDR3 = 6,
19 LPDDR4 = 7,
20 UNUSED = 0xff
21};
Caesar Wang9740bba2016-08-25 08:37:42 +0800[diff] [blame]22
23struct rk3399_ddr_pctl_regs {
Caesar Wanga8456902016-10-27 01:12:34 +0800[diff] [blame]24 uint32_t denali_ctl[CTL_REG_NUM];
Caesar Wang9740bba2016-08-25 08:37:42 +0800[diff] [blame]25};
26
27struct rk3399_ddr_publ_regs {
Derek Basehore6af5af02017-05-05 17:53:33 -0700[diff] [blame]28 /*
Lin Huang94bdbc42017-05-26 16:17:11 +0800[diff] [blame]29 * PHY registers from 0 to 90 for slice1.
30 * These are used to restore slice1-4 on resume.
Derek Basehore6af5af02017-05-05 17:53:33 -0700[diff] [blame]31 */
Lin Huang94bdbc42017-05-26 16:17:11 +0800[diff] [blame]32 uint32_t phy0[91];
Derek Basehore6af5af02017-05-05 17:53:33 -0700[diff] [blame]33 /*
34 * PHY registers from 512 to 895.
35 * Only registers 0-37 of each 128 register range are used.
36 */
37 uint32_t phy512[3][38];
38 uint32_t phy896[63];
Caesar Wang9740bba2016-08-25 08:37:42 +0800[diff] [blame]39};
40
Caesar Wang9740bba2016-08-25 08:37:42 +0800[diff] [blame]41struct rk3399_ddr_pi_regs {
Caesar Wanga8456902016-10-27 01:12:34 +0800[diff] [blame]42 uint32_t denali_pi[PI_REG_NUM];
Caesar Wang9740bba2016-08-25 08:37:42 +0800[diff] [blame]43};
44union noc_ddrtiminga0 {
45 uint32_t d32;
46 struct {
47 unsigned acttoact : 6;
48 unsigned reserved0 : 2;
49 unsigned rdtomiss : 6;
50 unsigned reserved1 : 2;
51 unsigned wrtomiss : 6;
52 unsigned reserved2 : 2;
53 unsigned readlatency : 8;
54 } b;
55};
56
57union noc_ddrtimingb0 {
58 uint32_t d32;
59 struct {
60 unsigned rdtowr : 5;
61 unsigned reserved0 : 3;
62 unsigned wrtord : 5;
63 unsigned reserved1 : 3;
64 unsigned rrd : 4;
65 unsigned reserved2 : 4;
66 unsigned faw : 6;
67 unsigned reserved3 : 2;
68 } b;
69};
70
71union noc_ddrtimingc0 {
72 uint32_t d32;
73 struct {
74 unsigned burstpenalty : 4;
75 unsigned reserved0 : 4;
76 unsigned wrtomwr : 6;
77 unsigned reserved1 : 18;
78 } b;
79};
80
81union noc_devtodev0 {
82 uint32_t d32;
83 struct {
84 unsigned busrdtord : 3;
85 unsigned reserved0 : 1;
86 unsigned busrdtowr : 3;
87 unsigned reserved1 : 1;
88 unsigned buswrtord : 3;
89 unsigned reserved2 : 1;
90 unsigned buswrtowr : 3;
91 unsigned reserved3 : 17;
92 } b;
93};
94
95union noc_ddrmode {
96 uint32_t d32;
97 struct {
98 unsigned autoprecharge : 1;
99 unsigned bypassfiltering : 1;
100 unsigned fawbank : 1;
101 unsigned burstsize : 2;
102 unsigned mwrsize : 2;
103 unsigned reserved2 : 1;
104 unsigned forceorder : 8;
105 unsigned forceorderstate : 8;
106 unsigned reserved3 : 8;
107 } b;
108};
109
Caesar Wang9740bba2016-08-25 08:37:42 +0800[diff] [blame]110struct rk3399_msch_timings {
111 union noc_ddrtiminga0 ddrtiminga0;
112 union noc_ddrtimingb0 ddrtimingb0;
113 union noc_ddrtimingc0 ddrtimingc0;
114 union noc_devtodev0 devtodev0;
115 union noc_ddrmode ddrmode;
116 uint32_t agingx0;
117};
Caesar Wanga8456902016-10-27 01:12:34 +0800[diff] [blame]118
Caesar Wang9740bba2016-08-25 08:37:42 +0800[diff] [blame]119struct rk3399_sdram_channel {
120 unsigned char rank;
121 /* col = 0, means this channel is invalid */
122 unsigned char col;
123 /* 3:8bank, 2:4bank */
124 unsigned char bk;
125 /* channel buswidth, 2:32bit, 1:16bit, 0:8bit */
126 unsigned char bw;
127 /* die buswidth, 2:32bit, 1:16bit, 0:8bit */
128 unsigned char dbw;
129 /* row_3_4 = 1: 6Gb or 12Gb die
130 * row_3_4 = 0: normal die, power of 2
131 */
132 unsigned char row_3_4;
133 unsigned char cs0_row;
134 unsigned char cs1_row;
135 uint32_t ddrconfig;
136 struct rk3399_msch_timings noc_timings;
137};
138
139struct rk3399_sdram_params {
140 struct rk3399_sdram_channel ch[2];
141 uint32_t ddr_freq;
142 unsigned char dramtype;
143 unsigned char num_channels;
144 unsigned char stride;
145 unsigned char odt;
146 struct rk3399_ddr_pctl_regs pctl_regs;
147 struct rk3399_ddr_pi_regs pi_regs;
148 struct rk3399_ddr_publ_regs phy_regs;
Derek Basehore04c74b92017-01-31 00:20:19 -0800[diff] [blame]149 uint32_t rx_cal_dqs[2][4];
Caesar Wang9740bba2016-08-25 08:37:42 +0800[diff] [blame]150};
Caesar Wang9740bba2016-08-25 08:37:42 +0800[diff] [blame]151
Patrick Georgi1a7cadf2021-06-23 21:34:38 +0200[diff] [blame]152extern struct rk3399_sdram_params sdram_config;
Caesar Wang9740bba2016-08-25 08:37:42 +0800[diff] [blame]153
Caesar Wanga8456902016-10-27 01:12:34 +0800[diff] [blame]154void dram_init(void);
Caesar Wang9740bba2016-08-25 08:37:42 +0800[diff] [blame]155
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +0000[diff] [blame]156#endif /* DRAM_H */