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git01.mediatek.com / filogic / atf / fa3cf0bf903ad0d8320713870ca58410e1ab8758 / . / plat / rockchip / rk3399 / drivers / dram / dram.h
blob: 08893d4eaf58e7ad620e813796149a5fe3873adf [file] [log] [blame]
Caesar Wang9740bba2016-08-25 08:37:42 +0800[diff] [blame]1/*
2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
3 *
dp-armfa3cf0b2017-05-03 09:38:09 +0100[diff] [blame^]4 * SPDX-License-Identifier: BSD-3-Clause
Caesar Wang9740bba2016-08-25 08:37:42 +0800[diff] [blame]5 */
6
Caesar Wanga8456902016-10-27 01:12:34 +0800[diff] [blame]7#ifndef __SOC_ROCKCHIP_RK3399_DRAM_H__
8#define __SOC_ROCKCHIP_RK3399_DRAM_H__
Xing Zhengb4bcc1d2017-02-24 16:26:11 +0800[diff] [blame]9
10#include <dram_regs.h>
Caesar Wanga8456902016-10-27 01:12:34 +0800[diff] [blame]11#include <plat_private.h>
12#include <stdint.h>
Caesar Wang9740bba2016-08-25 08:37:42 +0800[diff] [blame]13
Caesar Wanga8456902016-10-27 01:12:34 +0800[diff] [blame]14enum {
15 DDR3 = 3,
16 LPDDR2 = 5,
17 LPDDR3 = 6,
18 LPDDR4 = 7,
19 UNUSED = 0xff
20};
Caesar Wang9740bba2016-08-25 08:37:42 +0800[diff] [blame]21
22struct rk3399_ddr_pctl_regs {
Caesar Wanga8456902016-10-27 01:12:34 +0800[diff] [blame]23 uint32_t denali_ctl[CTL_REG_NUM];
Caesar Wang9740bba2016-08-25 08:37:42 +0800[diff] [blame]24};
25
26struct rk3399_ddr_publ_regs {
Caesar Wanga8456902016-10-27 01:12:34 +0800[diff] [blame]27 uint32_t denali_phy[PHY_REG_NUM];
Caesar Wang9740bba2016-08-25 08:37:42 +0800[diff] [blame]28};
29
Caesar Wang9740bba2016-08-25 08:37:42 +0800[diff] [blame]30struct rk3399_ddr_pi_regs {
Caesar Wanga8456902016-10-27 01:12:34 +0800[diff] [blame]31 uint32_t denali_pi[PI_REG_NUM];
Caesar Wang9740bba2016-08-25 08:37:42 +0800[diff] [blame]32};
33union noc_ddrtiminga0 {
34 uint32_t d32;
35 struct {
36 unsigned acttoact : 6;
37 unsigned reserved0 : 2;
38 unsigned rdtomiss : 6;
39 unsigned reserved1 : 2;
40 unsigned wrtomiss : 6;
41 unsigned reserved2 : 2;
42 unsigned readlatency : 8;
43 } b;
44};
45
46union noc_ddrtimingb0 {
47 uint32_t d32;
48 struct {
49 unsigned rdtowr : 5;
50 unsigned reserved0 : 3;
51 unsigned wrtord : 5;
52 unsigned reserved1 : 3;
53 unsigned rrd : 4;
54 unsigned reserved2 : 4;
55 unsigned faw : 6;
56 unsigned reserved3 : 2;
57 } b;
58};
59
60union noc_ddrtimingc0 {
61 uint32_t d32;
62 struct {
63 unsigned burstpenalty : 4;
64 unsigned reserved0 : 4;
65 unsigned wrtomwr : 6;
66 unsigned reserved1 : 18;
67 } b;
68};
69
70union noc_devtodev0 {
71 uint32_t d32;
72 struct {
73 unsigned busrdtord : 3;
74 unsigned reserved0 : 1;
75 unsigned busrdtowr : 3;
76 unsigned reserved1 : 1;
77 unsigned buswrtord : 3;
78 unsigned reserved2 : 1;
79 unsigned buswrtowr : 3;
80 unsigned reserved3 : 17;
81 } b;
82};
83
84union noc_ddrmode {
85 uint32_t d32;
86 struct {
87 unsigned autoprecharge : 1;
88 unsigned bypassfiltering : 1;
89 unsigned fawbank : 1;
90 unsigned burstsize : 2;
91 unsigned mwrsize : 2;
92 unsigned reserved2 : 1;
93 unsigned forceorder : 8;
94 unsigned forceorderstate : 8;
95 unsigned reserved3 : 8;
96 } b;
97};
98
Caesar Wang9740bba2016-08-25 08:37:42 +0800[diff] [blame]99struct rk3399_msch_timings {
100 union noc_ddrtiminga0 ddrtiminga0;
101 union noc_ddrtimingb0 ddrtimingb0;
102 union noc_ddrtimingc0 ddrtimingc0;
103 union noc_devtodev0 devtodev0;
104 union noc_ddrmode ddrmode;
105 uint32_t agingx0;
106};
Caesar Wanga8456902016-10-27 01:12:34 +0800[diff] [blame]107
Caesar Wang9740bba2016-08-25 08:37:42 +0800[diff] [blame]108struct rk3399_sdram_channel {
109 unsigned char rank;
110 /* col = 0, means this channel is invalid */
111 unsigned char col;
112 /* 3:8bank, 2:4bank */
113 unsigned char bk;
114 /* channel buswidth, 2:32bit, 1:16bit, 0:8bit */
115 unsigned char bw;
116 /* die buswidth, 2:32bit, 1:16bit, 0:8bit */
117 unsigned char dbw;
118 /* row_3_4 = 1: 6Gb or 12Gb die
119 * row_3_4 = 0: normal die, power of 2
120 */
121 unsigned char row_3_4;
122 unsigned char cs0_row;
123 unsigned char cs1_row;
124 uint32_t ddrconfig;
125 struct rk3399_msch_timings noc_timings;
126};
127
128struct rk3399_sdram_params {
129 struct rk3399_sdram_channel ch[2];
130 uint32_t ddr_freq;
131 unsigned char dramtype;
132 unsigned char num_channels;
133 unsigned char stride;
134 unsigned char odt;
135 struct rk3399_ddr_pctl_regs pctl_regs;
136 struct rk3399_ddr_pi_regs pi_regs;
137 struct rk3399_ddr_publ_regs phy_regs;
Derek Basehore04c74b92017-01-31 00:20:19 -0800[diff] [blame]138 uint32_t rx_cal_dqs[2][4];
Caesar Wang9740bba2016-08-25 08:37:42 +0800[diff] [blame]139};
Caesar Wang9740bba2016-08-25 08:37:42 +0800[diff] [blame]140
Caesar Wanga8456902016-10-27 01:12:34 +0800[diff] [blame]141extern __sramdata struct rk3399_sdram_params sdram_config;
Caesar Wang9740bba2016-08-25 08:37:42 +0800[diff] [blame]142
Caesar Wanga8456902016-10-27 01:12:34 +0800[diff] [blame]143void dram_init(void);
Caesar Wang9740bba2016-08-25 08:37:42 +0800[diff] [blame]144
Caesar Wang9740bba2016-08-25 08:37:42 +0800[diff] [blame]145#endif