Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 1 | /* |
Varun Wadekar | 3abd399 | 2020-01-03 14:21:03 -0800 | [diff] [blame] | 2 | * Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved. |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
Anthony Zhou | 10b970c | 2020-02-05 20:42:36 +0800 | [diff] [blame] | 7 | #include <assert.h> |
| 8 | #include <errno.h> |
| 9 | |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 10 | #include <arch.h> |
| 11 | #include <arch_helpers.h> |
| 12 | #include <common/debug.h> |
| 13 | #include <denver.h> |
| 14 | #include <lib/mmio.h> |
Anthony Zhou | 10b970c | 2020-02-05 20:42:36 +0800 | [diff] [blame] | 15 | |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 16 | #include <mce_private.h> |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 17 | #include <platform_def.h> |
| 18 | #include <t194_nvg.h> |
Steven Kao | 4035902 | 2017-06-22 12:54:06 +0800 | [diff] [blame] | 19 | #include <tegra_private.h> |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 20 | |
Varun Wadekar | fc463c5 | 2018-05-25 16:17:53 -0700 | [diff] [blame] | 21 | #define ID_AFR0_EL1_CACHE_OPS_SHIFT U(12) |
| 22 | #define ID_AFR0_EL1_CACHE_OPS_MASK U(0xF) |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 23 | /* |
| 24 | * Reports the major and minor version of this interface. |
| 25 | * |
| 26 | * NVGDATA[0:31]: SW(R) Minor Version |
| 27 | * NVGDATA[32:63]: SW(R) Major Version |
| 28 | */ |
| 29 | uint64_t nvg_get_version(void) |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 30 | { |
Anthony Zhou | c46150f | 2017-09-20 17:18:56 +0800 | [diff] [blame] | 31 | nvg_set_request((uint64_t)TEGRA_NVG_CHANNEL_VERSION); |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 32 | |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 33 | return (uint64_t)nvg_get_result(); |
| 34 | } |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 35 | |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 36 | /* |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 37 | * Set the expected wake time in TSC ticks for the next low-power state the |
| 38 | * core enters. |
| 39 | * |
| 40 | * NVGDATA[0:31]: SW(RW), WAKE_TIME |
| 41 | */ |
| 42 | void nvg_set_wake_time(uint32_t wake_time) |
| 43 | { |
| 44 | /* time (TSC ticks) until the core is expected to get a wake event */ |
Anthony Zhou | c46150f | 2017-09-20 17:18:56 +0800 | [diff] [blame] | 45 | nvg_set_request_data((uint64_t)TEGRA_NVG_CHANNEL_WAKE_TIME, (uint64_t)wake_time); |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 46 | } |
| 47 | |
| 48 | /* |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 49 | * This request allows updating of CLUSTER_CSTATE, CCPLEX_CSTATE and |
| 50 | * SYSTEM_CSTATE values. |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 51 | * |
| 52 | * NVGDATA[0:2]: SW(RW), CLUSTER_CSTATE |
| 53 | * NVGDATA[7]: SW(W), update cluster flag |
Vignesh Radhakrishnan | 706b9fe | 2017-11-04 16:36:23 -0700 | [diff] [blame] | 54 | * NVGDATA[8:10]: SW(RW), CG_CSTATE |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 55 | * NVGDATA[15]: SW(W), update ccplex flag |
| 56 | * NVGDATA[16:19]: SW(RW), SYSTEM_CSTATE |
| 57 | * NVGDATA[23]: SW(W), update system flag |
| 58 | * NVGDATA[31]: SW(W), update wake mask flag |
| 59 | * NVGDATA[32:63]: SW(RW), WAKE_MASK |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 60 | */ |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 61 | void nvg_update_cstate_info(uint32_t cluster, uint32_t ccplex, |
| 62 | uint32_t system, uint32_t wake_mask, uint8_t update_wake_mask) |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 63 | { |
| 64 | uint64_t val = 0; |
| 65 | |
| 66 | /* update CLUSTER_CSTATE? */ |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 67 | if (cluster != 0U) { |
| 68 | val |= ((uint64_t)cluster & CLUSTER_CSTATE_MASK) | |
| 69 | CLUSTER_CSTATE_UPDATE_BIT; |
| 70 | } |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 71 | |
| 72 | /* update CCPLEX_CSTATE? */ |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 73 | if (ccplex != 0U) { |
| 74 | val |= (((uint64_t)ccplex & CCPLEX_CSTATE_MASK) << CCPLEX_CSTATE_SHIFT) | |
| 75 | CCPLEX_CSTATE_UPDATE_BIT; |
| 76 | } |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 77 | |
| 78 | /* update SYSTEM_CSTATE? */ |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 79 | if (system != 0U) { |
| 80 | val |= (((uint64_t)system & SYSTEM_CSTATE_MASK) << SYSTEM_CSTATE_SHIFT) | |
| 81 | SYSTEM_CSTATE_UPDATE_BIT; |
| 82 | } |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 83 | |
| 84 | /* update wake mask value? */ |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 85 | if (update_wake_mask != 0U) { |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 86 | val |= CSTATE_WAKE_MASK_UPDATE_BIT; |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 87 | } |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 88 | |
| 89 | /* set the wake mask */ |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 90 | val |= ((uint64_t)wake_mask & CSTATE_WAKE_MASK_CLEAR) << CSTATE_WAKE_MASK_SHIFT; |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 91 | |
| 92 | /* set the updated cstate info */ |
Anthony Zhou | c46150f | 2017-09-20 17:18:56 +0800 | [diff] [blame] | 93 | nvg_set_request_data((uint64_t)TEGRA_NVG_CHANNEL_CSTATE_INFO, val); |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 94 | } |
| 95 | |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 96 | /* |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 97 | * Return a non-zero value if the CCPLEX is able to enter SC7 |
| 98 | * |
| 99 | * NVGDATA[0]: SW(R), Is allowed result |
| 100 | */ |
| 101 | int32_t nvg_is_sc7_allowed(void) |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 102 | { |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 103 | /* issue command to check if SC7 is allowed */ |
Anthony Zhou | c46150f | 2017-09-20 17:18:56 +0800 | [diff] [blame] | 104 | nvg_set_request((uint64_t)TEGRA_NVG_CHANNEL_IS_SC7_ALLOWED); |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 105 | |
| 106 | /* 1 = SC7 allowed, 0 = SC7 not allowed */ |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 107 | return (int32_t)nvg_get_result(); |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 108 | } |
| 109 | |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 110 | /* |
| 111 | * Wake an offlined logical core. Note that a core is offlined by entering |
| 112 | * a C-state where the WAKE_MASK is all 0. |
| 113 | * |
| 114 | * NVGDATA[0:3]: SW(W) logical core to online |
| 115 | */ |
| 116 | int32_t nvg_online_core(uint32_t core) |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 117 | { |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 118 | int32_t ret = 0; |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 119 | |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 120 | /* sanity check the core ID value */ |
| 121 | if (core > (uint32_t)PLATFORM_CORE_COUNT) { |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 122 | ERROR("%s: unknown core id (%d)\n", __func__, core); |
Varun Wadekar | 3abd399 | 2020-01-03 14:21:03 -0800 | [diff] [blame] | 123 | ret = -EINVAL; |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 124 | } else { |
| 125 | /* get a core online */ |
Anthony Zhou | c46150f | 2017-09-20 17:18:56 +0800 | [diff] [blame] | 126 | nvg_set_request_data((uint64_t)TEGRA_NVG_CHANNEL_ONLINE_CORE, |
| 127 | (uint64_t)core & MCE_CORE_ID_MASK); |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 128 | } |
| 129 | |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 130 | return ret; |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 131 | } |
| 132 | |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 133 | /* |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 134 | * MC GSC (General Security Carveout) register values are expected to be |
| 135 | * changed by TrustZone ARM code after boot. |
| 136 | * |
| 137 | * NVGDATA[0:15] SW(R) GSC enun |
| 138 | */ |
| 139 | int32_t nvg_update_ccplex_gsc(uint32_t gsc_idx) |
| 140 | { |
Varun Wadekar | 3abd399 | 2020-01-03 14:21:03 -0800 | [diff] [blame] | 141 | int32_t ret = 0; |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 142 | |
| 143 | /* sanity check GSC ID */ |
Steven Kao | 6f373a2 | 2017-09-29 18:09:17 +0800 | [diff] [blame] | 144 | if (gsc_idx > (uint32_t)TEGRA_NVG_CHANNEL_UPDATE_GSC_VPR) { |
| 145 | ERROR("%s: unknown gsc_idx (%u)\n", __func__, gsc_idx); |
Varun Wadekar | 3abd399 | 2020-01-03 14:21:03 -0800 | [diff] [blame] | 146 | ret = -EINVAL; |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 147 | } else { |
Anthony Zhou | c46150f | 2017-09-20 17:18:56 +0800 | [diff] [blame] | 148 | nvg_set_request_data((uint64_t)TEGRA_NVG_CHANNEL_UPDATE_CCPLEX_GSC, |
Varun Wadekar | 3abd399 | 2020-01-03 14:21:03 -0800 | [diff] [blame] | 149 | (uint64_t)gsc_idx); |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 150 | } |
| 151 | |
| 152 | return ret; |
| 153 | } |
| 154 | |
| 155 | /* |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 156 | * Cache clean and invalidate, clear TR-bit operation for all CCPLEX caches. |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 157 | */ |
| 158 | int32_t nvg_roc_clean_cache_trbits(void) |
| 159 | { |
Steven Kao | 238d6d2 | 2017-08-16 20:12:00 +0800 | [diff] [blame] | 160 | int32_t ret = 0; |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 161 | |
Steven Kao | 238d6d2 | 2017-08-16 20:12:00 +0800 | [diff] [blame] | 162 | /* check if cache flush through mts is supported */ |
| 163 | if (((read_id_afr0_el1() >> ID_AFR0_EL1_CACHE_OPS_SHIFT) & |
| 164 | ID_AFR0_EL1_CACHE_OPS_MASK) == 1U) { |
| 165 | if (nvg_cache_inval_all() == 0U) { |
| 166 | ERROR("%s: failed\n", __func__); |
Varun Wadekar | 3abd399 | 2020-01-03 14:21:03 -0800 | [diff] [blame] | 167 | ret = -ENODEV; |
Steven Kao | 238d6d2 | 2017-08-16 20:12:00 +0800 | [diff] [blame] | 168 | } |
| 169 | } else { |
Varun Wadekar | 3abd399 | 2020-01-03 14:21:03 -0800 | [diff] [blame] | 170 | ret = -ENOTSUP; |
Steven Kao | 238d6d2 | 2017-08-16 20:12:00 +0800 | [diff] [blame] | 171 | } |
Varun Wadekar | 3abd399 | 2020-01-03 14:21:03 -0800 | [diff] [blame] | 172 | |
Steven Kao | 238d6d2 | 2017-08-16 20:12:00 +0800 | [diff] [blame] | 173 | return ret; |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 174 | } |
| 175 | |
| 176 | /* |
| 177 | * Set the power state for a core |
| 178 | */ |
| 179 | int32_t nvg_enter_cstate(uint32_t state, uint32_t wake_time) |
| 180 | { |
| 181 | int32_t ret = 0; |
Steven Kao | 4035902 | 2017-06-22 12:54:06 +0800 | [diff] [blame] | 182 | uint64_t val = 0ULL; |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 183 | |
| 184 | /* check for allowed power state */ |
| 185 | if ((state != (uint32_t)TEGRA_NVG_CORE_C0) && |
| 186 | (state != (uint32_t)TEGRA_NVG_CORE_C1) && |
| 187 | (state != (uint32_t)TEGRA_NVG_CORE_C6) && |
| 188 | (state != (uint32_t)TEGRA_NVG_CORE_C7)) |
| 189 | { |
Varun Wadekar | 3abd399 | 2020-01-03 14:21:03 -0800 | [diff] [blame] | 190 | ERROR("%s: unknown cstate (%u)\n", __func__, state); |
| 191 | ret = -EINVAL; |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 192 | } else { |
| 193 | /* time (TSC ticks) until the core is expected to get a wake event */ |
| 194 | nvg_set_wake_time(wake_time); |
| 195 | |
| 196 | /* set the core cstate */ |
Steven Kao | 4035902 | 2017-06-22 12:54:06 +0800 | [diff] [blame] | 197 | val = read_actlr_el1() & ~ACTLR_EL1_PMSTATE_MASK; |
| 198 | write_actlr_el1(val | (uint64_t)state); |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 199 | } |
| 200 | |
| 201 | return ret; |
| 202 | } |
Dilan Lee | 4e7a63c | 2017-08-10 16:01:42 +0800 | [diff] [blame] | 203 | |
Steven Kao | 8f4f102 | 2017-12-13 06:39:15 +0800 | [diff] [blame] | 204 | #if ENABLE_STRICT_CHECKING_MODE |
Dilan Lee | 4e7a63c | 2017-08-10 16:01:42 +0800 | [diff] [blame] | 205 | /* |
| 206 | * Enable strict checking mode |
| 207 | * |
| 208 | * NVGDATA[3] strict_check ON + lock |
| 209 | */ |
| 210 | void nvg_enable_strict_checking_mode(void) |
| 211 | { |
| 212 | uint64_t params = (uint64_t)(STRICT_CHECKING_ENABLED_SET | |
| 213 | STRICT_CHECKING_LOCKED_SET); |
| 214 | |
Varun Wadekar | fc463c5 | 2018-05-25 16:17:53 -0700 | [diff] [blame] | 215 | nvg_set_request_data((uint64_t)TEGRA_NVG_CHANNEL_SECURITY_CONFIG, params); |
Dilan Lee | 4e7a63c | 2017-08-10 16:01:42 +0800 | [diff] [blame] | 216 | } |
Anthony Zhou | 10b970c | 2020-02-05 20:42:36 +0800 | [diff] [blame] | 217 | |
| 218 | void nvg_verify_strict_checking_mode(void) |
| 219 | { |
| 220 | uint64_t params = (uint64_t)(STRICT_CHECKING_ENABLED_SET | |
| 221 | STRICT_CHECKING_LOCKED_SET); |
| 222 | |
| 223 | nvg_set_request((uint64_t)TEGRA_NVG_CHANNEL_SECURITY_CONFIG); |
| 224 | assert(params == (uint64_t)nvg_get_result()); |
| 225 | } |
Steven Kao | 8f4f102 | 2017-12-13 06:39:15 +0800 | [diff] [blame] | 226 | #endif |
Vignesh Radhakrishnan | 3ad7983 | 2017-12-11 13:17:58 -0800 | [diff] [blame] | 227 | |
| 228 | /* |
| 229 | * Request a reboot |
| 230 | * |
| 231 | * NVGDATA[0]: reboot command |
| 232 | */ |
| 233 | void nvg_system_reboot(void) |
| 234 | { |
| 235 | /* issue command for reboot */ |
Varun Wadekar | fc463c5 | 2018-05-25 16:17:53 -0700 | [diff] [blame] | 236 | nvg_set_request_data((uint64_t)TEGRA_NVG_CHANNEL_SHUTDOWN, |
| 237 | (uint64_t)TEGRA_NVG_REBOOT); |
Vignesh Radhakrishnan | 3ad7983 | 2017-12-11 13:17:58 -0800 | [diff] [blame] | 238 | } |
| 239 | |
| 240 | /* |
| 241 | * Request a shutdown |
| 242 | * |
| 243 | * NVGDATA[0]: shutdown command |
| 244 | */ |
| 245 | void nvg_system_shutdown(void) |
| 246 | { |
| 247 | /* issue command for shutdown */ |
Varun Wadekar | fc463c5 | 2018-05-25 16:17:53 -0700 | [diff] [blame] | 248 | nvg_set_request_data((uint64_t)TEGRA_NVG_CHANNEL_SHUTDOWN, |
| 249 | (uint64_t)TEGRA_NVG_SHUTDOWN); |
Vignesh Radhakrishnan | 3ad7983 | 2017-12-11 13:17:58 -0800 | [diff] [blame] | 250 | } |
Varun Wadekar | 6718842 | 2019-03-21 08:23:05 -0700 | [diff] [blame] | 251 | |
| 252 | /* |
| 253 | * Request to clear CCPLEX->HSM correctable error signal. |
| 254 | * NVGDATA[1]: A write of 1 clears the CCPLEX->HSM correctable error signal, |
| 255 | * A write of 0 has no effect. |
| 256 | */ |
| 257 | void nvg_clear_hsm_corr_status(void) |
| 258 | { |
| 259 | nvg_hsm_error_ctrl_channel_t status = { .bits = { .corr = 1U, }, }; |
| 260 | |
| 261 | nvg_set_request_data((uint64_t)TEGRA_NVG_CHANNEL_HSM_ERROR_CTRL, status.flat); |
| 262 | } |