Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #include <arch.h> |
| 8 | #include <arch_helpers.h> |
| 9 | #include <common/debug.h> |
| 10 | #include <denver.h> |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 11 | #include <errno.h> |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 12 | #include <lib/mmio.h> |
| 13 | #include <mce_private.h> |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 14 | #include <platform_def.h> |
| 15 | #include <t194_nvg.h> |
Steven Kao | 4035902 | 2017-06-22 12:54:06 +0800 | [diff] [blame] | 16 | #include <tegra_private.h> |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 17 | |
Steven Kao | 238d6d2 | 2017-08-16 20:12:00 +0800 | [diff] [blame] | 18 | #define ID_AFR0_EL1_CACHE_OPS_SHIFT 12 |
| 19 | #define ID_AFR0_EL1_CACHE_OPS_MASK 0xFU |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 20 | /* |
| 21 | * Reports the major and minor version of this interface. |
| 22 | * |
| 23 | * NVGDATA[0:31]: SW(R) Minor Version |
| 24 | * NVGDATA[32:63]: SW(R) Major Version |
| 25 | */ |
| 26 | uint64_t nvg_get_version(void) |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 27 | { |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 28 | nvg_set_request(TEGRA_NVG_CHANNEL_VERSION); |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 29 | |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 30 | return (uint64_t)nvg_get_result(); |
| 31 | } |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 32 | |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 33 | /* |
| 34 | * Enable the perf per watt mode. |
| 35 | * |
| 36 | * NVGDATA[0]: SW(RW), 1 = enable perf per watt mode |
| 37 | */ |
| 38 | int32_t nvg_enable_power_perf_mode(void) |
| 39 | { |
| 40 | nvg_set_request_data(TEGRA_NVG_CHANNEL_POWER_PERF, 1U); |
| 41 | |
| 42 | return 0; |
| 43 | } |
| 44 | |
| 45 | /* |
| 46 | * Disable the perf per watt mode. |
| 47 | * |
| 48 | * NVGDATA[0]: SW(RW), 0 = disable perf per watt mode |
| 49 | */ |
| 50 | int32_t nvg_disable_power_perf_mode(void) |
| 51 | { |
| 52 | nvg_set_request_data(TEGRA_NVG_CHANNEL_POWER_PERF, 0U); |
| 53 | |
| 54 | return 0; |
| 55 | } |
| 56 | |
| 57 | /* |
| 58 | * Enable the battery saver mode. |
| 59 | * |
| 60 | * NVGDATA[2]: SW(RW), 1 = enable battery saver mode |
| 61 | */ |
| 62 | int32_t nvg_enable_power_saver_modes(void) |
| 63 | { |
| 64 | nvg_set_request_data(TEGRA_NVG_CHANNEL_POWER_MODES, 1U); |
| 65 | |
| 66 | return 0; |
| 67 | } |
| 68 | |
| 69 | /* |
| 70 | * Disable the battery saver mode. |
| 71 | * |
| 72 | * NVGDATA[2]: SW(RW), 0 = disable battery saver mode |
| 73 | */ |
| 74 | int32_t nvg_disable_power_saver_modes(void) |
| 75 | { |
| 76 | nvg_set_request_data(TEGRA_NVG_CHANNEL_POWER_MODES, 0U); |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 77 | |
| 78 | return 0; |
| 79 | } |
| 80 | |
| 81 | /* |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 82 | * Set the expected wake time in TSC ticks for the next low-power state the |
| 83 | * core enters. |
| 84 | * |
| 85 | * NVGDATA[0:31]: SW(RW), WAKE_TIME |
| 86 | */ |
| 87 | void nvg_set_wake_time(uint32_t wake_time) |
| 88 | { |
| 89 | /* time (TSC ticks) until the core is expected to get a wake event */ |
| 90 | nvg_set_request_data(TEGRA_NVG_CHANNEL_WAKE_TIME, (uint64_t)wake_time); |
| 91 | } |
| 92 | |
| 93 | /* |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 94 | * This request allows updating of CLUSTER_CSTATE, CCPLEX_CSTATE and |
| 95 | * SYSTEM_CSTATE values. |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 96 | * |
| 97 | * NVGDATA[0:2]: SW(RW), CLUSTER_CSTATE |
| 98 | * NVGDATA[7]: SW(W), update cluster flag |
| 99 | * NVGDATA[8:9]: SW(RW), CG_CSTATE |
| 100 | * NVGDATA[15]: SW(W), update ccplex flag |
| 101 | * NVGDATA[16:19]: SW(RW), SYSTEM_CSTATE |
| 102 | * NVGDATA[23]: SW(W), update system flag |
| 103 | * NVGDATA[31]: SW(W), update wake mask flag |
| 104 | * NVGDATA[32:63]: SW(RW), WAKE_MASK |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 105 | */ |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 106 | void nvg_update_cstate_info(uint32_t cluster, uint32_t ccplex, |
| 107 | uint32_t system, uint32_t wake_mask, uint8_t update_wake_mask) |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 108 | { |
| 109 | uint64_t val = 0; |
| 110 | |
| 111 | /* update CLUSTER_CSTATE? */ |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 112 | if (cluster != 0U) { |
| 113 | val |= ((uint64_t)cluster & CLUSTER_CSTATE_MASK) | |
| 114 | CLUSTER_CSTATE_UPDATE_BIT; |
| 115 | } |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 116 | |
| 117 | /* update CCPLEX_CSTATE? */ |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 118 | if (ccplex != 0U) { |
| 119 | val |= (((uint64_t)ccplex & CCPLEX_CSTATE_MASK) << CCPLEX_CSTATE_SHIFT) | |
| 120 | CCPLEX_CSTATE_UPDATE_BIT; |
| 121 | } |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 122 | |
| 123 | /* update SYSTEM_CSTATE? */ |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 124 | if (system != 0U) { |
| 125 | val |= (((uint64_t)system & SYSTEM_CSTATE_MASK) << SYSTEM_CSTATE_SHIFT) | |
| 126 | SYSTEM_CSTATE_UPDATE_BIT; |
| 127 | } |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 128 | |
| 129 | /* update wake mask value? */ |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 130 | if (update_wake_mask != 0U) { |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 131 | val |= CSTATE_WAKE_MASK_UPDATE_BIT; |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 132 | } |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 133 | |
| 134 | /* set the wake mask */ |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 135 | val |= ((uint64_t)wake_mask & CSTATE_WAKE_MASK_CLEAR) << CSTATE_WAKE_MASK_SHIFT; |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 136 | |
| 137 | /* set the updated cstate info */ |
| 138 | nvg_set_request_data(TEGRA_NVG_CHANNEL_CSTATE_INFO, val); |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 139 | } |
| 140 | |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 141 | /* |
| 142 | * Indices gives MTS the crossover point in TSC ticks for when it becomes |
| 143 | * no longer viable to enter the named state |
| 144 | * |
Steven Kao | 6f373a2 | 2017-09-29 18:09:17 +0800 | [diff] [blame^] | 145 | * Type 5 : NVGDATA[0:31]: C6 Lower bound |
| 146 | * Type 6 : NVGDATA[0:31]: CC6 Lower bound |
| 147 | * Type 8 : NVGDATA[0:31]: CG7 Lower bound |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 148 | */ |
| 149 | int32_t nvg_update_crossover_time(uint32_t type, uint32_t time) |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 150 | { |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 151 | int32_t ret = 0; |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 152 | |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 153 | switch (type) { |
Steven Kao | 6f373a2 | 2017-09-29 18:09:17 +0800 | [diff] [blame^] | 154 | case TEGRA_NVG_CHANNEL_CROSSOVER_C6_LOWER_BOUND: |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 155 | nvg_set_request_data(TEGRA_NVG_CHANNEL_CROSSOVER_C6_LOWER_BOUND, |
| 156 | (uint64_t)time); |
| 157 | break; |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 158 | |
Steven Kao | 6f373a2 | 2017-09-29 18:09:17 +0800 | [diff] [blame^] | 159 | case TEGRA_NVG_CHANNEL_CROSSOVER_CC6_LOWER_BOUND: |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 160 | nvg_set_request_data(TEGRA_NVG_CHANNEL_CROSSOVER_CC6_LOWER_BOUND, |
| 161 | (uint64_t)time); |
| 162 | break; |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 163 | |
Steven Kao | 6f373a2 | 2017-09-29 18:09:17 +0800 | [diff] [blame^] | 164 | case TEGRA_NVG_CHANNEL_CROSSOVER_CG7_LOWER_BOUND: |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 165 | nvg_set_request_data(TEGRA_NVG_CHANNEL_CROSSOVER_CG7_LOWER_BOUND, |
| 166 | (uint64_t)time); |
| 167 | break; |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 168 | |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 169 | default: |
| 170 | ERROR("%s: unknown crossover type (%d)\n", __func__, type); |
| 171 | ret = EINVAL; |
| 172 | break; |
| 173 | } |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 174 | |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 175 | return ret; |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 176 | } |
| 177 | |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 178 | /* |
| 179 | * These NVG calls allow ARM SW to access CSTATE statistical information |
| 180 | * |
| 181 | * NVGDATA[0:3]: SW(RW) Core/cluster/cg id |
| 182 | * NVGDATA[16:31]: SW(RW) Stat id |
| 183 | */ |
| 184 | int32_t nvg_set_cstate_stat_query_value(uint64_t data) |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 185 | { |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 186 | int32_t ret = 0; |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 187 | |
Krishna Sitaraman | 09f6817 | 2017-05-24 17:21:22 -0700 | [diff] [blame] | 188 | /* sanity check stat id and core id*/ |
| 189 | if ((data >> MCE_STAT_ID_SHIFT) > |
| 190 | (uint64_t)NVG_STAT_QUERY_C7_RESIDENCY_SUM) { |
| 191 | ERROR("%s: unknown stat id (%d)\n", __func__, |
| 192 | (uint32_t)(data >> MCE_STAT_ID_SHIFT)); |
| 193 | ret = EINVAL; |
| 194 | } else if ((data & MCE_CORE_ID_MASK) > (uint64_t)PLATFORM_CORE_COUNT) { |
| 195 | ERROR("%s: unknown core id (%d)\n", __func__, |
| 196 | (uint32_t)(data & MCE_CORE_ID_MASK)); |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 197 | ret = EINVAL; |
| 198 | } else { |
| 199 | nvg_set_request_data(TEGRA_NVG_CHANNEL_CSTATE_STAT_QUERY_REQUEST, data); |
| 200 | } |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 201 | |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 202 | return ret; |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 203 | } |
| 204 | |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 205 | /* |
| 206 | * The read-only value associated with the CSTATE_STAT_QUERY_REQUEST |
| 207 | * |
| 208 | * NVGDATA[0:63]: SW(R) Stat count |
| 209 | */ |
| 210 | uint64_t nvg_get_cstate_stat_query_value(void) |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 211 | { |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 212 | nvg_set_request(TEGRA_NVG_CHANNEL_CSTATE_STAT_QUERY_VALUE); |
| 213 | |
| 214 | return (uint64_t)nvg_get_result(); |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 215 | } |
| 216 | |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 217 | /* |
| 218 | * Return a non-zero value if the CCPLEX is able to enter SC7 |
| 219 | * |
| 220 | * NVGDATA[0]: SW(R), Is allowed result |
| 221 | */ |
| 222 | int32_t nvg_is_sc7_allowed(void) |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 223 | { |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 224 | /* issue command to check if SC7 is allowed */ |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 225 | nvg_set_request(TEGRA_NVG_CHANNEL_IS_SC7_ALLOWED); |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 226 | |
| 227 | /* 1 = SC7 allowed, 0 = SC7 not allowed */ |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 228 | return (int32_t)nvg_get_result(); |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 229 | } |
| 230 | |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 231 | /* |
| 232 | * Wake an offlined logical core. Note that a core is offlined by entering |
| 233 | * a C-state where the WAKE_MASK is all 0. |
| 234 | * |
| 235 | * NVGDATA[0:3]: SW(W) logical core to online |
| 236 | */ |
| 237 | int32_t nvg_online_core(uint32_t core) |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 238 | { |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 239 | int32_t ret = 0; |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 240 | |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 241 | /* sanity check the core ID value */ |
| 242 | if (core > (uint32_t)PLATFORM_CORE_COUNT) { |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 243 | ERROR("%s: unknown core id (%d)\n", __func__, core); |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 244 | ret = EINVAL; |
| 245 | } else { |
| 246 | /* get a core online */ |
| 247 | nvg_set_request_data(TEGRA_NVG_CHANNEL_ONLINE_CORE, |
| 248 | (uint64_t)core & MCE_CORE_ID_MASK); |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 249 | } |
| 250 | |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 251 | return ret; |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 252 | } |
| 253 | |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 254 | /* |
| 255 | * Enables and controls the voltage/frequency hint for CC3. CC3 is disabled |
| 256 | * by default. |
| 257 | * |
| 258 | * NVGDATA[7:0] SW(RW) frequency request |
| 259 | * NVGDATA[31:31] SW(RW) enable bit |
| 260 | */ |
| 261 | int32_t nvg_cc3_ctrl(uint32_t freq, uint8_t enable) |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 262 | { |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 263 | uint64_t val = 0; |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 264 | |
| 265 | /* |
| 266 | * If the enable bit is cleared, Auto-CC3 will be disabled by setting |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 267 | * the SW visible frequency request registers for all non |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 268 | * floorswept cores valid independent of StandbyWFI and disabling |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 269 | * the IDLE frequency request register. If set, Auto-CC3 |
| 270 | * will be enabled by setting the ARM SW visible frequency |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 271 | * request registers for all non floorswept cores to be enabled by |
| 272 | * StandbyWFI or the equivalent signal, and always keeping the IDLE |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 273 | * frequency request register enabled. |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 274 | */ |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 275 | if (enable != 0U) { |
| 276 | val = ((uint64_t)freq & MCE_AUTO_CC3_FREQ_MASK) | MCE_AUTO_CC3_ENABLE_BIT; |
| 277 | } |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 278 | nvg_set_request_data(TEGRA_NVG_CHANNEL_CC3_CTRL, val); |
| 279 | |
| 280 | return 0; |
| 281 | } |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 282 | |
| 283 | /* |
| 284 | * MC GSC (General Security Carveout) register values are expected to be |
| 285 | * changed by TrustZone ARM code after boot. |
| 286 | * |
| 287 | * NVGDATA[0:15] SW(R) GSC enun |
| 288 | */ |
| 289 | int32_t nvg_update_ccplex_gsc(uint32_t gsc_idx) |
| 290 | { |
Steven Kao | 6f373a2 | 2017-09-29 18:09:17 +0800 | [diff] [blame^] | 291 | int32_t ret; |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 292 | |
| 293 | /* sanity check GSC ID */ |
Steven Kao | 6f373a2 | 2017-09-29 18:09:17 +0800 | [diff] [blame^] | 294 | if (gsc_idx > (uint32_t)TEGRA_NVG_CHANNEL_UPDATE_GSC_VPR) { |
| 295 | ERROR("%s: unknown gsc_idx (%u)\n", __func__, gsc_idx); |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 296 | ret = EINVAL; |
| 297 | } else { |
| 298 | nvg_set_request_data(TEGRA_NVG_CHANNEL_UPDATE_CCPLEX_GSC, |
| 299 | (uint64_t)gsc_idx); |
| 300 | } |
| 301 | |
| 302 | return ret; |
| 303 | } |
| 304 | |
| 305 | /* |
| 306 | * Cache clean operation for all CCPLEX caches. |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 307 | */ |
| 308 | int32_t nvg_roc_clean_cache(void) |
| 309 | { |
Steven Kao | 238d6d2 | 2017-08-16 20:12:00 +0800 | [diff] [blame] | 310 | int32_t ret = 0; |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 311 | |
Steven Kao | 238d6d2 | 2017-08-16 20:12:00 +0800 | [diff] [blame] | 312 | /* check if cache flush through mts is supported */ |
| 313 | if (((read_id_afr0_el1() >> ID_AFR0_EL1_CACHE_OPS_SHIFT) & |
| 314 | ID_AFR0_EL1_CACHE_OPS_MASK) == 1U) { |
| 315 | if (nvg_cache_clean() == 0U) { |
| 316 | ERROR("%s: failed\n", __func__); |
| 317 | ret = EINVAL; |
| 318 | } |
| 319 | } else { |
| 320 | ret = EINVAL; |
| 321 | } |
| 322 | return ret; |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 323 | } |
| 324 | |
| 325 | /* |
| 326 | * Cache clean and invalidate operation for all CCPLEX caches. |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 327 | */ |
| 328 | int32_t nvg_roc_flush_cache(void) |
| 329 | { |
Steven Kao | 238d6d2 | 2017-08-16 20:12:00 +0800 | [diff] [blame] | 330 | int32_t ret = 0; |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 331 | |
Steven Kao | 238d6d2 | 2017-08-16 20:12:00 +0800 | [diff] [blame] | 332 | /* check if cache flush through mts is supported */ |
| 333 | if (((read_id_afr0_el1() >> ID_AFR0_EL1_CACHE_OPS_SHIFT) & |
| 334 | ID_AFR0_EL1_CACHE_OPS_MASK) == 1U) { |
| 335 | if (nvg_cache_clean_inval() == 0U) { |
| 336 | ERROR("%s: failed\n", __func__); |
| 337 | ret = EINVAL; |
| 338 | } |
| 339 | } else { |
| 340 | ret = EINVAL; |
| 341 | } |
| 342 | return ret; |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 343 | } |
| 344 | |
| 345 | /* |
| 346 | * Cache clean and invalidate, clear TR-bit operation for all CCPLEX caches. |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 347 | */ |
| 348 | int32_t nvg_roc_clean_cache_trbits(void) |
| 349 | { |
Steven Kao | 238d6d2 | 2017-08-16 20:12:00 +0800 | [diff] [blame] | 350 | int32_t ret = 0; |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 351 | |
Steven Kao | 238d6d2 | 2017-08-16 20:12:00 +0800 | [diff] [blame] | 352 | /* check if cache flush through mts is supported */ |
| 353 | if (((read_id_afr0_el1() >> ID_AFR0_EL1_CACHE_OPS_SHIFT) & |
| 354 | ID_AFR0_EL1_CACHE_OPS_MASK) == 1U) { |
| 355 | if (nvg_cache_inval_all() == 0U) { |
| 356 | ERROR("%s: failed\n", __func__); |
| 357 | ret = EINVAL; |
| 358 | } |
| 359 | } else { |
| 360 | ret = EINVAL; |
| 361 | } |
| 362 | return ret; |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 363 | } |
| 364 | |
| 365 | /* |
| 366 | * Set the power state for a core |
| 367 | */ |
| 368 | int32_t nvg_enter_cstate(uint32_t state, uint32_t wake_time) |
| 369 | { |
| 370 | int32_t ret = 0; |
Steven Kao | 4035902 | 2017-06-22 12:54:06 +0800 | [diff] [blame] | 371 | uint64_t val = 0ULL; |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 372 | |
| 373 | /* check for allowed power state */ |
| 374 | if ((state != (uint32_t)TEGRA_NVG_CORE_C0) && |
| 375 | (state != (uint32_t)TEGRA_NVG_CORE_C1) && |
| 376 | (state != (uint32_t)TEGRA_NVG_CORE_C6) && |
| 377 | (state != (uint32_t)TEGRA_NVG_CORE_C7)) |
| 378 | { |
| 379 | ERROR("%s: unknown cstate (%d)\n", __func__, state); |
| 380 | ret = EINVAL; |
| 381 | } else { |
| 382 | /* time (TSC ticks) until the core is expected to get a wake event */ |
| 383 | nvg_set_wake_time(wake_time); |
| 384 | |
| 385 | /* set the core cstate */ |
Steven Kao | 4035902 | 2017-06-22 12:54:06 +0800 | [diff] [blame] | 386 | val = read_actlr_el1() & ~ACTLR_EL1_PMSTATE_MASK; |
| 387 | write_actlr_el1(val | (uint64_t)state); |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 388 | } |
| 389 | |
| 390 | return ret; |
| 391 | } |