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Jeenu Viswambharan615ff392016-10-24 14:31:51 +01001#
Jeenu Viswambharanfca76802017-01-16 16:52:35 +00002# Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved.
Jeenu Viswambharan615ff392016-10-24 14:31:51 +01003#
dp-armfa3cf0b2017-05-03 09:38:09 +01004# SPDX-License-Identifier: BSD-3-Clause
Jeenu Viswambharan615ff392016-10-24 14:31:51 +01005#
6
7# Default, static values for build variables, listed in alphabetic order.
8# Dependencies between build options, if any, are handled in the top-level
9# Makefile, after this file is included. This ensures that the former is better
10# poised to handle dependencies, as all build variables would have a default
11# value by then.
12
13# The AArch32 Secure Payload to be built as BL32 image
14AARCH32_SP := none
15
16# The Target build architecture. Supported values are: aarch64, aarch32.
17ARCH := aarch64
18
Jeenu Viswambharanfca76802017-01-16 16:52:35 +000019# ARM Architecture major and minor versions: 8.0 by default.
20ARM_ARCH_MAJOR := 8
21ARM_ARCH_MINOR := 0
22
Jeenu Viswambharan615ff392016-10-24 14:31:51 +010023# Determine the version of ARM GIC architecture to use for interrupt management
24# in EL3. The platform port can change this value if needed.
25ARM_GIC_ARCH := 2
26
Jeenu Viswambharan615ff392016-10-24 14:31:51 +010027# Base commit to perform code check on
28BASE_COMMIT := origin/master
29
Roberto Vargase0e99462017-10-30 14:43:43 +000030# Execute BL2 at EL3
31BL2_AT_EL3 := 0
32
Jeenu Viswambharan615ff392016-10-24 14:31:51 +010033# By default, consider that the platform may release several CPUs out of reset.
34# The platform Makefile is free to override this value.
35COLD_BOOT_SINGLE_CPU := 0
36
37# For Chain of Trust
38CREATE_KEYS := 1
39
40# Build flag to include AArch32 registers in cpu context save and restore during
41# world switch. This flag must be set to 0 for AArch64-only platforms.
42CTX_INCLUDE_AARCH32_REGS := 1
43
44# Include FP registers in cpu context
45CTX_INCLUDE_FPREGS := 0
46
47# Debug build
48DEBUG := 0
49
50# Build platform
51DEFAULT_PLAT := fvp
52
Jeenu Viswambharan615ff392016-10-24 14:31:51 +010053# Flag to enable Performance Measurement Framework
54ENABLE_PMF := 0
55
56# Flag to enable PSCI STATs functionality
57ENABLE_PSCI_STAT := 0
58
59# Flag to enable runtime instrumentation using PMF
60ENABLE_RUNTIME_INSTRUMENTATION := 0
61
Douglas Raillard306593d2017-02-24 18:14:15 +000062# Flag to enable stack corruption protection
63ENABLE_STACK_PROTECTOR := 0
64
Jeenu Viswambharan10a67272017-09-22 08:32:10 +010065# Flag to enable exception handling in EL3
66EL3_EXCEPTION_HANDLING := 0
67
Jeenu Viswambharan615ff392016-10-24 14:31:51 +010068# Build flag to treat usage of deprecated platform and framework APIs as error.
69ERROR_DEPRECATED := 0
70
Masahiro Yamada4d87eb42016-12-25 13:52:22 +090071# Byte alignment that each component in FIP is aligned to
72FIP_ALIGN := 0
73
Jeenu Viswambharan615ff392016-10-24 14:31:51 +010074# Default FIP file name
75FIP_NAME := fip.bin
76
77# Default FWU_FIP file name
78FWU_FIP_NAME := fwu_fip.bin
79
80# For Chain of Trust
81GENERATE_COT := 0
82
Jeenu Viswambharanc06f05c2017-09-22 08:32:09 +010083# Hint platform interrupt control layer that Group 0 interrupts are for EL3. By
84# default, they are for Secure EL1.
85GICV2_G0_FOR_EL3 := 0
86
Jeenu Viswambharana10d64e2017-01-04 13:51:42 +000087# Whether system coherency is managed in hardware, without explicit software
88# operations.
89HW_ASSISTED_COHERENCY := 0
90
Soby Mathew13b16052017-08-31 11:49:32 +010091# Set the default algorithm for the generation of Trusted Board Boot keys
92KEY_ALG := rsa
93
Jeenu Viswambharan615ff392016-10-24 14:31:51 +010094# Flag to enable new version of image loading
95LOAD_IMAGE_V2 := 0
96
97# NS timer register save and restore
98NS_TIMER_SWITCH := 0
99
100# Build PL011 UART driver in minimal generic UART mode
101PL011_GENERIC_UART := 0
102
103# By default, consider that the platform's reset address is not programmable.
104# The platform Makefile is free to override this value.
105PROGRAMMABLE_RESET_ADDRESS := 0
106
107# Flag used to choose the power state format viz Extended State-ID or the
108# Original format.
109PSCI_EXTENDED_STATE_ID := 0
110
111# By default, BL1 acts as the reset handler, not BL31
112RESET_TO_BL31 := 0
113
114# For Chain of Trust
115SAVE_KEYS := 0
116
Jeenu Viswambharan04e3a7f2017-10-16 08:43:14 +0100117# Software Delegated Exception support
118SDEI_SUPPORT := 0
119
Jeenu Viswambharan615ff392016-10-24 14:31:51 +0100120# Whether code and read-only data should be put on separate memory pages. The
121# platform Makefile is free to override this value.
122SEPARATE_CODE_AND_RODATA := 0
123
124# SPD choice
125SPD := none
126
Antonio Nino Diazc41f2062017-10-24 10:07:35 +0100127# For including the Secure Partition Manager
128ENABLE_SPM := 0
129
Jeenu Viswambharan615ff392016-10-24 14:31:51 +0100130# Flag to introduce an infinite loop in BL1 just before it exits into the next
131# image. This is meant to help debugging the post-BL2 phase.
132SPIN_ON_BL1_EXIT := 0
133
134# Flags to build TF with Trusted Boot support
135TRUSTED_BOARD_BOOT := 0
136
137# Build option to choose whether Trusted firmware uses Coherent memory or not.
138USE_COHERENT_MEM := 1
139
Masahiro Yamadaa27c1662017-05-22 12:11:24 +0900140# Use tbbr_oid.h instead of platform_oid.h
141USE_TBBR_DEFS = $(ERROR_DEPRECATED)
142
Jeenu Viswambharan615ff392016-10-24 14:31:51 +0100143# Build verbosity
144V := 0
Soby Mathew043fe9c2017-04-10 22:35:42 +0100145
146# Whether to enable D-Cache early during warm boot. This is usually
147# applicable for platforms wherein interconnect programming is not
148# required to enable cache coherency after warm reset (eg: single cluster
149# platforms).
150WARMBOOT_ENABLE_DCACHE_EARLY := 0
dp-armee3457b2017-05-23 09:32:49 +0100151
Dimitris Papastamos9da09cd2017-10-13 15:07:45 +0100152# Build option to enable/disable the Statistical Profiling Extensions
dp-armee3457b2017-05-23 09:32:49 +0100153ENABLE_SPE_FOR_LOWER_ELS := 1
154
Dimitris Papastamos9da09cd2017-10-13 15:07:45 +0100155# SPE is only supported on AArch64 so disable it on AArch32.
dp-armee3457b2017-05-23 09:32:49 +0100156ifeq (${ARCH},aarch32)
157 override ENABLE_SPE_FOR_LOWER_ELS := 0
dp-armee3457b2017-05-23 09:32:49 +0100158endif
Dimitris Papastamosfcedb692017-10-16 11:40:10 +0100159
160ENABLE_AMU := 0
David Cunadoce88eee2017-10-20 11:30:57 +0100161
162# By default, enable Scalable Vector Extension if implemented for Non-secure
163# lower ELs
164# Note SVE is only supported on AArch64 - therefore do not enable in AArch32
165ifneq (${ARCH},aarch32)
166 ENABLE_SVE_FOR_NS := 1
167else
168 override ENABLE_SVE_FOR_NS := 0
169endif