Jorge Ramirez-Ortiz | 766263c | 2018-09-23 09:39:56 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #include <debug.h> |
| 8 | #include "emmc_config.h" |
| 9 | #include "emmc_hal.h" |
| 10 | #include "emmc_std.h" |
| 11 | #include "emmc_registers.h" |
| 12 | #include "emmc_def.h" |
| 13 | |
| 14 | static const uint32_t cmd_reg_hw[EMMC_CMD_MAX + 1] = { |
| 15 | 0x00000000, /* CMD0 */ |
| 16 | 0x00000701, /* CMD1 */ |
| 17 | 0x00000002, /* CMD2 */ |
| 18 | 0x00000003, /* CMD3 */ |
| 19 | 0x00000004, /* CMD4 */ |
| 20 | 0x00000505, /* CMD5 */ |
| 21 | 0x00000406, /* CMD6 */ |
| 22 | 0x00000007, /* CMD7 */ |
| 23 | 0x00001C08, /* CMD8 */ |
| 24 | 0x00000009, /* CMD9 */ |
| 25 | 0x0000000A, /* CMD10 */ |
| 26 | 0x00000000, /* reserved */ |
| 27 | 0x0000000C, /* CMD12 */ |
| 28 | 0x0000000D, /* CMD13 */ |
| 29 | 0x00001C0E, /* CMD14 */ |
| 30 | 0x0000000F, /* CMD15 */ |
| 31 | 0x00000010, /* CMD16 */ |
| 32 | 0x00000011, /* CMD17 */ |
| 33 | 0x00007C12, /* CMD18 */ |
| 34 | 0x00000C13, /* CMD19 */ |
| 35 | 0x00000000, |
| 36 | 0x00001C15, /* CMD21 */ |
| 37 | 0x00000000, |
| 38 | 0x00000017, /* CMD23 */ |
| 39 | 0x00000018, /* CMD24 */ |
| 40 | 0x00006C19, /* CMD25 */ |
| 41 | 0x00000C1A, /* CMD26 */ |
| 42 | 0x0000001B, /* CMD27 */ |
| 43 | 0x0000001C, /* CMD28 */ |
| 44 | 0x0000001D, /* CMD29 */ |
| 45 | 0x0000001E, /* CMD30 */ |
| 46 | 0x00001C1F, /* CMD31 */ |
| 47 | 0x00000000, |
| 48 | 0x00000000, |
| 49 | 0x00000000, |
| 50 | 0x00000423, /* CMD35 */ |
| 51 | 0x00000424, /* CMD36 */ |
| 52 | 0x00000000, |
| 53 | 0x00000026, /* CMD38 */ |
| 54 | 0x00000427, /* CMD39 */ |
| 55 | 0x00000428, /* CMD40(send cmd) */ |
| 56 | 0x00000000, |
| 57 | 0x0000002A, /* CMD42 */ |
| 58 | 0x00000000, |
| 59 | 0x00000000, |
| 60 | 0x00000000, |
| 61 | 0x00000000, |
| 62 | 0x00000000, |
| 63 | 0x00000000, |
| 64 | 0x00000C31, |
| 65 | 0x00000000, |
| 66 | 0x00000000, |
| 67 | 0x00000000, |
| 68 | 0x00007C35, |
| 69 | 0x00006C36, |
| 70 | 0x00000037, /* CMD55 */ |
| 71 | 0x00000038, /* CMD56(Read) */ |
| 72 | 0x00000000, |
| 73 | 0x00000000, |
| 74 | 0x00000000, |
| 75 | 0x00000000 |
| 76 | }; |
| 77 | |
| 78 | uint32_t emmc_bit_field(uint8_t *data, uint32_t top, uint32_t bottom) |
| 79 | { |
| 80 | uint32_t value; |
| 81 | |
| 82 | uint32_t index_top = (uint32_t) (15 - (top >> 3)); |
| 83 | uint32_t index_bottom = (uint32_t) (15 - (bottom >> 3)); |
| 84 | |
| 85 | if (index_top == index_bottom) { |
| 86 | value = data[index_top]; |
| 87 | } else if ((index_top + 1) == index_bottom) { |
| 88 | value = |
| 89 | (uint32_t) ((data[index_top] << 8) | data[index_bottom]); |
| 90 | } else if ((index_top + 2) == index_bottom) { |
| 91 | value = |
| 92 | (uint32_t) ((data[index_top] << 16) | |
| 93 | (data[index_top + 1] << 8) | data[index_top + |
| 94 | 2]); |
| 95 | } else { |
| 96 | value = |
| 97 | (uint32_t) ((data[index_top] << 24) | |
| 98 | (data[index_top + 1] << 16) | |
| 99 | (data[index_top + 2] << 8) | data[index_top + |
| 100 | 3]); |
| 101 | } |
| 102 | |
| 103 | value = ((value >> (bottom & 0x07)) & ((1 << (top - bottom + 1)) - 1)); |
| 104 | |
| 105 | return value; |
| 106 | } |
| 107 | |
| 108 | void emmc_write_error_info(uint16_t func_no, EMMC_ERROR_CODE error_code) |
| 109 | { |
| 110 | |
| 111 | mmc_drv_obj.error_info.num = func_no; |
| 112 | mmc_drv_obj.error_info.code = (uint16_t) error_code; |
| 113 | |
| 114 | ERROR("BL2: emmc err:func_no=0x%x code=0x%x\n", func_no, error_code); |
| 115 | } |
| 116 | |
| 117 | void emmc_write_error_info_func_no(uint16_t func_no) |
| 118 | { |
| 119 | |
| 120 | mmc_drv_obj.error_info.num = func_no; |
| 121 | |
| 122 | ERROR("BL2: emmc err:func_no=0x%x\n", func_no); |
| 123 | } |
| 124 | |
| 125 | void emmc_make_nontrans_cmd(HAL_MEMCARD_COMMAND cmd, uint32_t arg) |
| 126 | { |
| 127 | /* command information */ |
| 128 | mmc_drv_obj.cmd_info.cmd = cmd; |
| 129 | mmc_drv_obj.cmd_info.arg = arg; |
| 130 | mmc_drv_obj.cmd_info.dir = HAL_MEMCARD_READ; |
| 131 | mmc_drv_obj.cmd_info.hw = |
| 132 | cmd_reg_hw[cmd & HAL_MEMCARD_COMMAND_INDEX_MASK]; |
| 133 | |
| 134 | /* clear data transfer information */ |
| 135 | mmc_drv_obj.trans_size = 0; |
| 136 | mmc_drv_obj.remain_size = 0; |
| 137 | mmc_drv_obj.buff_address_virtual = NULL; |
| 138 | mmc_drv_obj.buff_address_physical = NULL; |
| 139 | |
| 140 | /* response information */ |
| 141 | mmc_drv_obj.response_length = 6; |
| 142 | |
| 143 | switch (mmc_drv_obj.cmd_info.cmd & HAL_MEMCARD_RESPONSE_TYPE_MASK) { |
| 144 | case HAL_MEMCARD_RESPONSE_NONE: |
| 145 | mmc_drv_obj.response = (uint32_t *) mmc_drv_obj.response_data; |
| 146 | mmc_drv_obj.response_length = 0; |
| 147 | break; |
| 148 | case HAL_MEMCARD_RESPONSE_R1: |
| 149 | mmc_drv_obj.response = &mmc_drv_obj.r1_card_status; |
| 150 | break; |
| 151 | case HAL_MEMCARD_RESPONSE_R1b: |
| 152 | mmc_drv_obj.cmd_info.hw |= BIT10; /* bit10 = R1 busy bit */ |
| 153 | mmc_drv_obj.response = &mmc_drv_obj.r1_card_status; |
| 154 | break; |
| 155 | case HAL_MEMCARD_RESPONSE_R2: |
| 156 | mmc_drv_obj.response = (uint32_t *) mmc_drv_obj.response_data; |
| 157 | mmc_drv_obj.response_length = 17; |
| 158 | break; |
| 159 | case HAL_MEMCARD_RESPONSE_R3: |
| 160 | mmc_drv_obj.response = &mmc_drv_obj.r3_ocr; |
| 161 | break; |
| 162 | case HAL_MEMCARD_RESPONSE_R4: |
| 163 | mmc_drv_obj.response = &mmc_drv_obj.r4_resp; |
| 164 | break; |
| 165 | case HAL_MEMCARD_RESPONSE_R5: |
| 166 | mmc_drv_obj.response = &mmc_drv_obj.r5_resp; |
| 167 | break; |
| 168 | default: |
| 169 | mmc_drv_obj.response = (uint32_t *) mmc_drv_obj.response_data; |
| 170 | break; |
| 171 | } |
| 172 | } |
| 173 | |
| 174 | void emmc_make_trans_cmd(HAL_MEMCARD_COMMAND cmd, uint32_t arg, |
| 175 | uint32_t *buff_address_virtual, |
| 176 | uint32_t len, |
| 177 | HAL_MEMCARD_OPERATION dir, |
| 178 | HAL_MEMCARD_DATA_TRANSFER_MODE transfer_mode) |
| 179 | { |
| 180 | emmc_make_nontrans_cmd(cmd, arg); /* update common information */ |
| 181 | |
| 182 | /* for data transfer command */ |
| 183 | mmc_drv_obj.cmd_info.dir = dir; |
| 184 | mmc_drv_obj.buff_address_virtual = buff_address_virtual; |
| 185 | mmc_drv_obj.buff_address_physical = buff_address_virtual; |
| 186 | mmc_drv_obj.trans_size = len; |
| 187 | mmc_drv_obj.remain_size = len; |
| 188 | mmc_drv_obj.transfer_mode = transfer_mode; |
| 189 | } |
| 190 | |
| 191 | EMMC_ERROR_CODE emmc_send_idle_cmd(uint32_t arg) |
| 192 | { |
| 193 | EMMC_ERROR_CODE result; |
| 194 | uint32_t freq; |
| 195 | |
| 196 | /* initialize state */ |
| 197 | mmc_drv_obj.mount = FALSE; |
| 198 | mmc_drv_obj.selected = FALSE; |
| 199 | mmc_drv_obj.during_transfer = FALSE; |
| 200 | mmc_drv_obj.during_cmd_processing = FALSE; |
| 201 | mmc_drv_obj.during_dma_transfer = FALSE; |
| 202 | mmc_drv_obj.dma_error_flag = FALSE; |
| 203 | mmc_drv_obj.force_terminate = FALSE; |
| 204 | mmc_drv_obj.state_machine_blocking = FALSE; |
| 205 | |
| 206 | mmc_drv_obj.bus_width = HAL_MEMCARD_DATA_WIDTH_1_BIT; |
| 207 | mmc_drv_obj.max_freq = MMC_20MHZ; /* 20MHz */ |
| 208 | mmc_drv_obj.current_state = EMMC_R1_STATE_IDLE; |
| 209 | |
| 210 | /* CMD0 (MMC clock is current frequency. if Data transfer mode, 20MHz or higher.) */ |
| 211 | emmc_make_nontrans_cmd(CMD0_GO_IDLE_STATE, arg); /* CMD0 */ |
| 212 | result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response); |
| 213 | if (result != EMMC_SUCCESS) { |
| 214 | return result; |
| 215 | } |
| 216 | |
| 217 | /* change MMC clock(400KHz) */ |
| 218 | freq = MMC_400KHZ; |
| 219 | result = emmc_set_request_mmc_clock(&freq); |
| 220 | if (result != EMMC_SUCCESS) { |
| 221 | return result; |
| 222 | } |
| 223 | |
| 224 | return EMMC_SUCCESS; |
| 225 | } |