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Chandni Cherukuri626a52d2018-08-16 13:43:23 +05301#
Manish V Badarkhe95e9d742023-04-19 13:27:59 +01002# Copyright (c) 2018-2023, Arm Limited. All rights reserved.
Chandni Cherukuri626a52d2018-08-16 13:43:23 +05303#
4# SPDX-License-Identifier: BSD-3-Clause
5#
6
Manish V Badarkhe95e9d742023-04-19 13:27:59 +01007$(warning Platform ${PLAT} is deprecated. \
8 Some of the features might not work as expected)
9
Chandni Cherukuri626a52d2018-08-16 13:43:23 +053010include plat/arm/css/sgi/sgi-common.mk
11
Chandni Cherukuri533b5542019-02-22 16:44:49 +053012RDE1EDGE_BASE = plat/arm/board/rde1edge
Chandni Cherukuri626a52d2018-08-16 13:43:23 +053013
Chandni Cherukuri533b5542019-02-22 16:44:49 +053014PLAT_INCLUDES += -I${RDE1EDGE_BASE}/include/
Chandni Cherukuri626a52d2018-08-16 13:43:23 +053015
John Tsichritzis16e6d9f2019-02-19 14:01:55 +000016SGI_CPU_SOURCES := lib/cpus/aarch64/neoverse_e1.S
Chandni Cherukuri626a52d2018-08-16 13:43:23 +053017
Aditya Angadi502d0ac2020-11-18 08:27:15 +053018PLAT_BL_COMMON_SOURCES += ${CSS_ENT_BASE}/sgi_plat.c
19
Ambroise Vincentfa42c9e2019-07-04 14:58:45 +010020BL1_SOURCES += ${SGI_CPU_SOURCES} \
21 ${RDE1EDGE_BASE}/rde1edge_err.c
Chandni Cherukuri626a52d2018-08-16 13:43:23 +053022
Chandni Cherukuri533b5542019-02-22 16:44:49 +053023BL2_SOURCES += ${RDE1EDGE_BASE}/rde1edge_plat.c \
24 ${RDE1EDGE_BASE}/rde1edge_security.c \
Ambroise Vincentfa42c9e2019-07-04 14:58:45 +010025 ${RDE1EDGE_BASE}/rde1edge_err.c \
Chandni Cherukuri626a52d2018-08-16 13:43:23 +053026 drivers/arm/tzc/tzc_dmc620.c \
27 lib/utils/mem_region.c \
28 plat/arm/common/arm_nor_psci_mem_protect.c
29
30BL31_SOURCES += ${SGI_CPU_SOURCES} \
Chandni Cherukuri533b5542019-02-22 16:44:49 +053031 ${RDE1EDGE_BASE}/rde1edge_plat.c \
Vijayenthiran Subramaniamf5cb00f2019-12-27 19:27:57 +053032 ${RDE1EDGE_BASE}/rde1edge_topology.c \
Chandni Cherukuri626a52d2018-08-16 13:43:23 +053033 drivers/cfi/v2m/v2m_flash.c \
34 lib/utils/mem_region.c \
35 plat/arm/common/arm_nor_psci_mem_protect.c
36
Max Shvetsov06dba292019-12-06 11:50:12 +000037ifeq (${TRUSTED_BOARD_BOOT}, 1)
38BL1_SOURCES += ${RDE1EDGE_BASE}/rde1edge_trusted_boot.c
39BL2_SOURCES += ${RDE1EDGE_BASE}/rde1edge_trusted_boot.c
40endif
41
Chandni Cherukuri626a52d2018-08-16 13:43:23 +053042# Add the FDT_SOURCES and options for Dynamic Config
Manish V Badarkhe64616a52020-05-31 08:53:40 +010043FDT_SOURCES += ${RDE1EDGE_BASE}/fdts/${PLAT}_fw_config.dts \
44 ${RDE1EDGE_BASE}/fdts/${PLAT}_tb_fw_config.dts
45FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_fw_config.dtb
46TB_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tb_fw_config.dtb
Chandni Cherukuri626a52d2018-08-16 13:43:23 +053047
Manish V Badarkhe64616a52020-05-31 08:53:40 +010048# Add the FW_CONFIG to FIP and specify the same to certtool
Anders Dellien3f694742020-08-23 19:32:48 +010049$(eval $(call TOOL_ADD_PAYLOAD,${FW_CONFIG},--fw-config,${FW_CONFIG}))
Chandni Cherukuri626a52d2018-08-16 13:43:23 +053050# Add the TB_FW_CONFIG to FIP and specify the same to certtool
Anders Dellien3f694742020-08-23 19:32:48 +010051$(eval $(call TOOL_ADD_PAYLOAD,${TB_FW_CONFIG},--tb-fw-config,${TB_FW_CONFIG}))
Chandni Cherukuri626a52d2018-08-16 13:43:23 +053052
Chandni Cherukuri533b5542019-02-22 16:44:49 +053053FDT_SOURCES += ${RDE1EDGE_BASE}/fdts/${PLAT}_nt_fw_config.dts
Chandni Cherukuri626a52d2018-08-16 13:43:23 +053054NT_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_nt_fw_config.dtb
55
56# Add the NT_FW_CONFIG to FIP and specify the same to certtool
Anders Dellien3f694742020-08-23 19:32:48 +010057$(eval $(call TOOL_ADD_PAYLOAD,${NT_FW_CONFIG},--nt-fw-config,${NT_FW_CONFIG}))
Chandni Cherukuri626a52d2018-08-16 13:43:23 +053058
Vijayenthiran Subramaniambc489912019-12-26 17:45:58 +053059ifneq ($(CSS_SGI_CHIP_COUNT),1)
60 $(error "Chip count for RDE1Edge should be 1, currently set to \
61 ${CSS_SGI_CHIP_COUNT}.")
62endif
63
Aditya Angadi06402222021-03-20 12:06:15 +053064ifneq ($(CSS_SGI_PLATFORM_VARIANT),0)
65 $(error "CSS_SGI_PLATFORM_VARIANT for RD-E1-Edge should always be 0, \
66 currently set to ${CSS_SGI_PLATFORM_VARIANT}.")
67endif
68
Chandni Cherukuri626a52d2018-08-16 13:43:23 +053069override CTX_INCLUDE_AARCH32_REGS := 0