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git01.mediatek.com / filogic / atf / 50dbb084af9c54ca02a8a80536ec1e721ac524d3 / . / plat / mediatek / mt8195 / drivers / apusys / mtk_apusys.c
blob: 3ed26a147bcc79ac5e7117646f78953b0996b60e [file] [log] [blame]
developer47917892021-11-01 16:43:47 +0800[diff] [blame]1/*
2 * Copyright (c) 2021, MediaTek Inc. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <common/debug.h>
8#include <drivers/console.h>
9#include <lib/mmio.h>
10
developer80159062021-11-08 16:37:39 +0800[diff] [blame]11#include <apupwr_clkctl.h>
developer47917892021-11-01 16:43:47 +0800[diff] [blame]12#include <mtk_apusys.h>
13#include <plat/common/platform.h>
14
15int32_t apusys_kernel_ctrl(uint64_t x1, uint64_t x2, uint64_t x3, uint64_t x4,
16 uint32_t *ret1)
17{
18 int32_t ret = 0L;
19 uint32_t request_ops;
20
21 request_ops = (uint32_t)x1;
22
23 switch (request_ops) {
24 case MTK_SIP_APU_START_MCU:
25 /* setup addr[33:32] in reviser */
26 mmio_write_32(REVISER_SECUREFW_CTXT, 0U);
27 mmio_write_32(REVISER_USDRFW_CTXT, 0U);
28
29 /* setup secure sideband */
30 mmio_write_32(AO_SEC_FW,
31 (SEC_FW_NON_SECURE << SEC_FW_SHIFT_NS) |
32 (0U << SEC_FW_DOMAIN_SHIFT));
33
34 /* setup boot address */
35 mmio_write_32(AO_MD32_BOOT_CTRL, 0U);
36
37 /* setup pre-define region */
38 mmio_write_32(AO_MD32_PRE_DEFINE,
39 (PRE_DEFINE_CACHE_TCM << PRE_DEFINE_SHIFT_0G) |
40 (PRE_DEFINE_CACHE << PRE_DEFINE_SHIFT_1G) |
41 (PRE_DEFINE_CACHE << PRE_DEFINE_SHIFT_2G) |
42 (PRE_DEFINE_CACHE << PRE_DEFINE_SHIFT_3G));
43
44 /* release runstall */
45 mmio_write_32(AO_MD32_SYS_CTRL, SYS_CTRL_RUN);
46
47 INFO("[APUSYS] rev(0x%08x,0x%08x)\n",
48 mmio_read_32(REVISER_SECUREFW_CTXT),
49 mmio_read_32(REVISER_USDRFW_CTXT));
50 INFO("[APUSYS] ao(0x%08x,0x%08x,0x%08x,0x%08x,0x%08x)\n",
51 mmio_read_32(AO_SEC_FW),
52 mmio_read_32(AO_SEC_USR_FW),
53 mmio_read_32(AO_MD32_BOOT_CTRL),
54 mmio_read_32(AO_MD32_PRE_DEFINE),
55 mmio_read_32(AO_MD32_SYS_CTRL));
56 break;
57 case MTK_SIP_APU_STOP_MCU:
58 /* hold runstall */
59 mmio_write_32(AO_MD32_SYS_CTRL, SYS_CTRL_STALL);
60
61 INFO("[APUSYS] md32_boot_ctrl=0x%08x,runstall=0x%08x\n",
62 mmio_read_32(AO_MD32_BOOT_CTRL),
63 mmio_read_32(AO_MD32_SYS_CTRL));
64 break;
developer80159062021-11-08 16:37:39 +0800[diff] [blame]65 case MTK_SIP_APUPWR_BUS_PROT_CG_ON:
66 apupwr_smc_bus_prot_cg_on();
67 break;
68 case MTK_SIP_APUPWR_BULK_PLL:
69 ret = apupwr_smc_bulk_pll((bool)x2);
70 break;
71 case MTK_SIP_APUPWR_ACC_INIT_ALL:
72 ret = apupwr_smc_acc_init_all();
73 break;
74 case MTK_SIP_APUPWR_ACC_TOP:
75 apupwr_smc_acc_top((bool)x2);
76 break;
developer47917892021-11-01 16:43:47 +0800[diff] [blame]77 default:
78 ERROR("%s, unknown request_ops=0x%x\n", __func__, request_ops);
79 break;
80 }
81
82 return ret;
83}