feat(plat/mediatek/apu): add mt8195 APU clock and pll SiP call
The clock and pll of mt8195 can be locked into security access
by device apc. Add clock and pll related SiP call for the access
from Kernel space.
Change-Id: I0c1f7d6c6abdd3b976492a0b776dc5b1d1f1512b
diff --git a/plat/mediatek/mt8195/drivers/apusys/mtk_apusys.c b/plat/mediatek/mt8195/drivers/apusys/mtk_apusys.c
index 53e3cc8..3ed26a1 100644
--- a/plat/mediatek/mt8195/drivers/apusys/mtk_apusys.c
+++ b/plat/mediatek/mt8195/drivers/apusys/mtk_apusys.c
@@ -8,6 +8,7 @@
#include <drivers/console.h>
#include <lib/mmio.h>
+#include <apupwr_clkctl.h>
#include <mtk_apusys.h>
#include <plat/common/platform.h>
@@ -61,6 +62,18 @@
mmio_read_32(AO_MD32_BOOT_CTRL),
mmio_read_32(AO_MD32_SYS_CTRL));
break;
+ case MTK_SIP_APUPWR_BUS_PROT_CG_ON:
+ apupwr_smc_bus_prot_cg_on();
+ break;
+ case MTK_SIP_APUPWR_BULK_PLL:
+ ret = apupwr_smc_bulk_pll((bool)x2);
+ break;
+ case MTK_SIP_APUPWR_ACC_INIT_ALL:
+ ret = apupwr_smc_acc_init_all();
+ break;
+ case MTK_SIP_APUPWR_ACC_TOP:
+ apupwr_smc_acc_top((bool)x2);
+ break;
default:
ERROR("%s, unknown request_ops=0x%x\n", __func__, request_ops);
break;