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Nishanth Menon0192f892016-10-14 01:13:34 +00001/*
2 * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +00007#ifndef PLATFORM_DEF_H
8#define PLATFORM_DEF_H
Nishanth Menon0192f892016-10-14 01:13:34 +00009
10#include <arch.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000011#include <plat/common/common_def.h>
12
Nishanth Menon0192f892016-10-14 01:13:34 +000013#include <board_def.h>
Nishanth Menon0192f892016-10-14 01:13:34 +000014
15/*******************************************************************************
16 * Generic platform constants
17 ******************************************************************************/
18
19/* Size of cacheable stack */
20#if IMAGE_BL31
21#define PLATFORM_STACK_SIZE 0x800
22#else
23#define PLATFORM_STACK_SIZE 0x1000
24#endif
25
Benjamin Fairf807a342016-10-18 14:32:06 -050026#define PLATFORM_SYSTEM_COUNT 1
27#define PLATFORM_CORE_COUNT (K3_CLUSTER0_CORE_COUNT + \
28 K3_CLUSTER1_CORE_COUNT + \
29 K3_CLUSTER2_CORE_COUNT + \
30 K3_CLUSTER3_CORE_COUNT)
31
Andrew F. Davisb208ae32019-03-27 09:37:10 -050032#define PLATFORM_CLUSTER_COUNT ((K3_CLUSTER0_CORE_COUNT != 0) + \
33 (K3_CLUSTER1_CORE_COUNT != 0) + \
34 (K3_CLUSTER2_CORE_COUNT != 0) + \
35 (K3_CLUSTER3_CORE_COUNT != 0))
Benjamin Fairf807a342016-10-18 14:32:06 -050036
Andrew F. Davis34d8b682018-06-25 12:10:53 -050037#define PLAT_NUM_PWR_DOMAINS (PLATFORM_SYSTEM_COUNT + \
38 PLATFORM_CLUSTER_COUNT + \
Nishanth Menon0192f892016-10-14 01:13:34 +000039 PLATFORM_CORE_COUNT)
Andrew F. Davis34d8b682018-06-25 12:10:53 -050040#define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2
Nishanth Menon0192f892016-10-14 01:13:34 +000041
42/*******************************************************************************
43 * Memory layout constants
44 ******************************************************************************/
45
46/*
47 * ARM-TF lives in SRAM, partition it here
Andrew F. Davis9b9ac452019-01-22 14:00:16 -060048 *
Nishanth Menon0192f892016-10-14 01:13:34 +000049 * BL3-1 specific defines.
50 *
Andrew F. Davis9b9ac452019-01-22 14:00:16 -060051 * Put BL3-1 at the base of the Trusted SRAM.
Nishanth Menon0192f892016-10-14 01:13:34 +000052 */
53#define BL31_BASE SEC_SRAM_BASE
Andrew F. Davis9b9ac452019-01-22 14:00:16 -060054#define BL31_SIZE SEC_SRAM_SIZE
Nishanth Menon0192f892016-10-14 01:13:34 +000055#define BL31_LIMIT (BL31_BASE + BL31_SIZE)
Nishanth Menon0192f892016-10-14 01:13:34 +000056
57/*
Nishanth Menon3ed1b282016-10-14 01:13:45 +000058 * Defines the maximum number of translation tables that are allocated by the
59 * translation table library code. To minimize the amount of runtime memory
60 * used, choose the smallest value needed to map the required virtual addresses
61 * for each BL stage.
62 */
63#define MAX_XLAT_TABLES 8
64
65/*
66 * Defines the maximum number of regions that are allocated by the translation
67 * table library code. A region consists of physical base address, virtual base
68 * address, size and attributes (Device/Memory, RO/RW, Secure/Non-Secure), as
69 * defined in the `mmap_region_t` structure. The platform defines the regions
70 * that should be mapped. Then, the translation table library will create the
71 * corresponding tables and descriptors at runtime. To minimize the amount of
72 * runtime memory used, choose the smallest value needed to register the
73 * required regions for each BL stage.
74 */
Andrew F. Davis537d3ff2018-05-04 19:06:08 +000075#define MAX_MMAP_REGIONS 11
Nishanth Menon3ed1b282016-10-14 01:13:45 +000076
77/*
78 * Defines the total size of the address space in bytes. For example, for a 32
79 * bit address space, this value should be `(1ull << 32)`.
80 */
81#define PLAT_PHY_ADDR_SPACE_SIZE (1ull << 32)
82#define PLAT_VIRT_ADDR_SPACE_SIZE (1ull << 32)
83
84/*
Nishanth Menon0192f892016-10-14 01:13:34 +000085 * Some data must be aligned on the biggest cache line size in the platform.
86 * This is known only to the platform as it might have a combination of
87 * integrated and external caches.
88 */
89#define CACHE_WRITEBACK_SHIFT 6
90#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT)
91
Nishanth Menonce976042016-10-14 01:13:44 +000092/* Platform default console definitions */
Andrew F. Davis42c277b2019-01-22 13:36:48 -060093#ifndef K3_USART_BASE
Jan Kiszkab99c0782020-05-20 07:35:48 +020094#define K3_USART_BASE (0x02800000 + 0x10000 * K3_USART)
Nishanth Menonce976042016-10-14 01:13:44 +000095#endif
96
97/* USART has a default size for address space */
98#define K3_USART_SIZE 0x1000
99
100#ifndef K3_USART_CLK_SPEED
101#define K3_USART_CLK_SPEED 48000000
102#endif
103
Nishanth Menonce976042016-10-14 01:13:44 +0000104/* Crash console defaults */
Andrew F. Davis42c277b2019-01-22 13:36:48 -0600105#define CRASH_CONSOLE_BASE K3_USART_BASE
Nishanth Menonce976042016-10-14 01:13:44 +0000106#define CRASH_CONSOLE_CLK K3_USART_CLK_SPEED
107#define CRASH_CONSOLE_BAUD_RATE K3_USART_BAUD
108
Nishanth Menon1f0b51b2016-10-14 01:13:48 +0000109/* Timer frequency */
110#ifndef SYS_COUNTER_FREQ_IN_TICKS
111#define SYS_COUNTER_FREQ_IN_TICKS 200000000
112#endif
113
Nishanth Menonf97ad372016-10-14 01:13:49 +0000114/* Interrupt numbers */
115#define ARM_IRQ_SEC_PHY_TIMER 29
116
117#define ARM_IRQ_SEC_SGI_0 8
118#define ARM_IRQ_SEC_SGI_1 9
119#define ARM_IRQ_SEC_SGI_2 10
120#define ARM_IRQ_SEC_SGI_3 11
121#define ARM_IRQ_SEC_SGI_4 12
122#define ARM_IRQ_SEC_SGI_5 13
123#define ARM_IRQ_SEC_SGI_6 14
124#define ARM_IRQ_SEC_SGI_7 15
125
126/*
127 * Define properties of Group 1 Secure and Group 0 interrupts as per GICv3
128 * terminology. On a GICv2 system or mode, the lists will be merged and treated
129 * as Group 0 interrupts.
130 */
131#define PLAT_ARM_G1S_IRQ_PROPS(grp) \
132 INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, grp, \
133 GIC_INTR_CFG_LEVEL), \
134 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, grp, \
135 GIC_INTR_CFG_EDGE), \
136 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, grp, \
137 GIC_INTR_CFG_EDGE), \
138 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, grp, \
139 GIC_INTR_CFG_EDGE), \
140 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, grp, \
141 GIC_INTR_CFG_EDGE), \
142 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, grp, \
143 GIC_INTR_CFG_EDGE), \
144 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, grp, \
145 GIC_INTR_CFG_EDGE)
146
147#define PLAT_ARM_G0_IRQ_PROPS(grp) \
148 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY, grp, \
149 GIC_INTR_CFG_EDGE), \
150 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, grp, \
151 GIC_INTR_CFG_EDGE)
152
Nishanth Menon651ff1a2020-12-10 20:51:51 -0600153
154#define K3_GTC_BASE 0x00A90000
155/* We just need 20 byte offset, but simpler to just remap the 64K page in */
156#define K3_GTC_SIZE 0x10000
157#define K3_GTC_CNTCR_OFFSET 0x00
158#define K3_GTC_CNTCR_EN_MASK 0x01
159#define K3_GTC_CNTCR_HDBG_MASK 0x02
160#define K3_GTC_CNTFID0_OFFSET 0x20
161
Andrew F. Davis75ad53f2019-01-22 12:39:31 -0600162#define K3_GIC_BASE 0x01800000
163#define K3_GIC_SIZE 0x200000
Nishanth Menonf97ad372016-10-14 01:13:49 +0000164
Nishanth Menond32de842020-12-10 18:39:41 -0600165#if !K3_SEC_PROXY_LITE
Andrew F. Davis537d3ff2018-05-04 19:06:08 +0000166#define SEC_PROXY_DATA_BASE 0x32C00000
167#define SEC_PROXY_DATA_SIZE 0x80000
168#define SEC_PROXY_SCFG_BASE 0x32800000
169#define SEC_PROXY_SCFG_SIZE 0x80000
170#define SEC_PROXY_RT_BASE 0x32400000
171#define SEC_PROXY_RT_SIZE 0x80000
Nishanth Menond32de842020-12-10 18:39:41 -0600172#else
173#define SEC_PROXY_DATA_BASE 0x4D000000
174#define SEC_PROXY_DATA_SIZE 0x80000
175#define SEC_PROXY_SCFG_BASE 0x4A400000
176#define SEC_PROXY_SCFG_SIZE 0x80000
177#define SEC_PROXY_RT_BASE 0x4A600000
178#define SEC_PROXY_RT_SIZE 0x80000
179#endif /* K3_SEC_PROXY_LITE */
Andrew F. Davis537d3ff2018-05-04 19:06:08 +0000180
181#define SEC_PROXY_TIMEOUT_US 1000000
182#define SEC_PROXY_MAX_MESSAGE_SIZE 56
183
Andrew F. Davisa513b2a2018-05-04 19:06:09 +0000184#define TI_SCI_HOST_ID 10
185#define TI_SCI_MAX_MESSAGE_SIZE 52
186
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +0000187#endif /* PLATFORM_DEF_H */