Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 7 | #include <stdint.h> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 8 | |
| 9 | #include <common/debug.h> |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 10 | |
| 11 | #include "boot_init_dram_regdef_e3.h" |
| 12 | #include "ddr_init_e3.h" |
| 13 | |
| 14 | #include "../dram_sub_func.h" |
| 15 | |
| 16 | /* rev.0.04 add variables */ |
| 17 | /******************************************************************************* |
| 18 | * variables |
| 19 | ******************************************************************************/ |
| 20 | uint32_t ddrBackup; |
| 21 | |
| 22 | /* rev.0.03 add Prototypes */ |
| 23 | /******************************************************************************* |
| 24 | * Prototypes |
| 25 | ******************************************************************************/ |
| 26 | /* static uint32_t init_ddr(void); rev.0.04 */ |
| 27 | /* static uint32_t recovery_from_backup_mode(void); rev.0.04 */ |
| 28 | /* int32_t dram_update_boot_status(uint32_t status); rev.0.04 */ |
| 29 | |
| 30 | /* rev.0.03 add Comment */ |
| 31 | /******************************************************************************* |
| 32 | * register write/read function |
| 33 | ******************************************************************************/ |
| 34 | static void WriteReg_32(uint32_t a, uint32_t v) |
| 35 | { |
| 36 | (*(volatile uint32_t*)(uintptr_t)a) = v; |
| 37 | } /* WriteReg_32 */ |
| 38 | |
| 39 | static uint32_t ReadReg_32(uint32_t a) |
| 40 | { |
| 41 | uint32_t w = (*(volatile uint32_t*)(uintptr_t)a); |
| 42 | return w; |
| 43 | } /* ReadReg_32 */ |
| 44 | |
| 45 | /* rev.0.04 add Comment */ |
| 46 | /******************************************************************************* |
| 47 | * Initialize ddr |
| 48 | ******************************************************************************/ |
| 49 | uint32_t init_ddr(void) |
| 50 | { |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 51 | uint32_t RegVal_R2, RegVal_R5, RegVal_R6, RegVal_R7, RegVal_R12, i; |
| 52 | uint32_t ddr_md; |
| 53 | |
| 54 | /* rev.0.08 */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 55 | uint32_t RegVal, j; |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 56 | uint32_t dqsgd_0c, bdlcount_0c, bdlcount_0c_div2, bdlcount_0c_div4, bdlcount_0c_div8, bdlcount_0c_div16; |
| 57 | uint32_t gatesl_0c, rdqsd_0c, rdqsnd_0c, rbd_0c[4]; |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 58 | uint32_t pdqsr_ctl, lcdl_ctl, lcdl_judge1, lcdl_judge2; |
Marek Vasut | 432d767 | 2018-12-12 18:06:39 +0100 | [diff] [blame] | 59 | /* rev.0.10 */ |
| 60 | uint32_t pdr_ctl; |
| 61 | /* rev.0.11 */ |
| 62 | uint32_t byp_ctl; |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 63 | |
| 64 | /* rev.0.08 */ |
| 65 | if ((ReadReg_32(0xFFF00044) & 0x000000FF) == 0x00000000) { |
| 66 | pdqsr_ctl = 1; |
| 67 | lcdl_ctl = 1; |
Marek Vasut | 432d767 | 2018-12-12 18:06:39 +0100 | [diff] [blame] | 68 | pdr_ctl = 1; /* rev.0.10 */ |
| 69 | byp_ctl = 1; /* rev.0.11 */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 70 | } else { |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 71 | pdqsr_ctl = 0; |
| 72 | lcdl_ctl = 0; |
Marek Vasut | 432d767 | 2018-12-12 18:06:39 +0100 | [diff] [blame] | 73 | pdr_ctl = 0; /* rev.0.10 */ |
| 74 | byp_ctl = 0; /* rev.0.11 */ |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 75 | } |
| 76 | |
| 77 | /* Judge the DDR bit rate (ddr_md : 0 = 1584Mbps, 1 = 1856Mbps) */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 78 | ddr_md = (ReadReg_32(RST_MODEMR) >> 19) & BIT0; |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 79 | |
| 80 | /* 1584Mbps setting */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 81 | if (ddr_md == 0) { |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 82 | /* CPG setting ===============================================*/ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 83 | WriteReg_32(CPG_CPGWPR, 0x5A5AFFFF); |
| 84 | WriteReg_32(CPG_CPGWPCR, 0xA5A50000); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 85 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 86 | WriteReg_32(CPG_SRCR4, 0x20000000); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 87 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 88 | WriteReg_32(0xE61500DC, 0xe2200000); /* Change to 1584Mbps */ |
| 89 | while ((BIT11 & ReadReg_32(CPG_PLLECR)) == 0); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 90 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 91 | WriteReg_32(CPG_SRSTCLR4, 0x20000000); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 92 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 93 | WriteReg_32(CPG_CPGWPCR, 0xA5A50001); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 94 | |
| 95 | /* CPG setting ===============================================*/ |
| 96 | } /* ddr_md */ |
| 97 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 98 | WriteReg_32(DBSC_E3_DBSYSCNT0, 0x00001234); |
| 99 | WriteReg_32(DBSC_E3_DBKIND, 0x00000007); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 100 | |
| 101 | #if RCAR_DRAM_DDR3L_MEMCONF == 0 |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 102 | WriteReg_32(DBSC_E3_DBMEMCONF00, 0x0f030a02); /* 1GB */ |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 103 | #elif RCAR_DRAM_DDR3L_MEMCONF == 1 |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 104 | WriteReg_32(DBSC_E3_DBMEMCONF00, 0x10030a02); /* 2GB(default) */ |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 105 | #elif RCAR_DRAM_DDR3L_MEMCONF == 2 |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 106 | WriteReg_32(DBSC_E3_DBMEMCONF00, 0x10030b02); /* 4GB */ |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 107 | #else |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 108 | WriteReg_32(DBSC_E3_DBMEMCONF00, 0x10030a02); /* 2GB */ |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 109 | #endif |
| 110 | |
| 111 | #if RCAR_DRAM_DDR3L_MEMDUAL == 1 |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 112 | RegVal_R2 = (ReadReg_32(0xE6790614)); |
| 113 | WriteReg_32(0xE6790614, RegVal_R2 | 0x00000003); /* MCS1_N/MODT1 are activated. */ |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 114 | #endif |
| 115 | |
| 116 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 117 | WriteReg_32(DBSC_E3_DBPHYCONF0, 0x00000001); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 118 | |
| 119 | /* Select setting value in bps */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 120 | if (ddr_md == 0) { /* 1584Mbps */ |
| 121 | WriteReg_32(DBSC_E3_DBTR0, 0x0000000B); |
| 122 | WriteReg_32(DBSC_E3_DBTR1, 0x00000008); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 123 | } else { /* 1856Mbps */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 124 | WriteReg_32(DBSC_E3_DBTR0, 0x0000000D); |
| 125 | WriteReg_32(DBSC_E3_DBTR1, 0x00000009); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 126 | } /* ddr_md */ |
| 127 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 128 | WriteReg_32(DBSC_E3_DBTR2, 0x00000000); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 129 | |
| 130 | /* Select setting value in bps */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 131 | if (ddr_md == 0) { /* 1584Mbps */ |
| 132 | WriteReg_32(DBSC_E3_DBTR3, 0x0000000B); |
| 133 | WriteReg_32(DBSC_E3_DBTR4, 0x000B000B); |
| 134 | WriteReg_32(DBSC_E3_DBTR5, 0x00000027); |
| 135 | WriteReg_32(DBSC_E3_DBTR6, 0x0000001C); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 136 | } else { /* 1856Mbps */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 137 | WriteReg_32(DBSC_E3_DBTR3, 0x0000000D); |
| 138 | WriteReg_32(DBSC_E3_DBTR4, 0x000D000D); |
| 139 | WriteReg_32(DBSC_E3_DBTR5, 0x0000002D); |
| 140 | WriteReg_32(DBSC_E3_DBTR6, 0x00000020); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 141 | } /* ddr_md */ |
| 142 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 143 | WriteReg_32(DBSC_E3_DBTR7, 0x00060006); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 144 | |
| 145 | /* Select setting value in bps */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 146 | if (ddr_md == 0) { /* 1584Mbps */ |
| 147 | WriteReg_32(DBSC_E3_DBTR8, 0x00000020); |
| 148 | WriteReg_32(DBSC_E3_DBTR9, 0x00000006); |
| 149 | WriteReg_32(DBSC_E3_DBTR10, 0x0000000C); |
| 150 | WriteReg_32(DBSC_E3_DBTR11, 0x0000000A); |
| 151 | WriteReg_32(DBSC_E3_DBTR12, 0x00120012); |
| 152 | WriteReg_32(DBSC_E3_DBTR13, 0x000000CE); |
| 153 | WriteReg_32(DBSC_E3_DBTR14, 0x00140005); |
| 154 | WriteReg_32(DBSC_E3_DBTR15, 0x00050004); |
| 155 | WriteReg_32(DBSC_E3_DBTR16, 0x071F0305); |
| 156 | WriteReg_32(DBSC_E3_DBTR17, 0x040C0000); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 157 | } else { /* 1856Mbps */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 158 | WriteReg_32(DBSC_E3_DBTR8, 0x00000021); |
| 159 | WriteReg_32(DBSC_E3_DBTR9, 0x00000007); |
| 160 | WriteReg_32(DBSC_E3_DBTR10, 0x0000000E); |
| 161 | WriteReg_32(DBSC_E3_DBTR11, 0x0000000C); |
| 162 | WriteReg_32(DBSC_E3_DBTR12, 0x00140014); |
| 163 | WriteReg_32(DBSC_E3_DBTR13, 0x000000F2); |
| 164 | WriteReg_32(DBSC_E3_DBTR14, 0x00170006); |
| 165 | WriteReg_32(DBSC_E3_DBTR15, 0x00060005); |
| 166 | WriteReg_32(DBSC_E3_DBTR16, 0x09210507); |
| 167 | WriteReg_32(DBSC_E3_DBTR17, 0x040E0000); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 168 | } /* ddr_md */ |
| 169 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 170 | WriteReg_32(DBSC_E3_DBTR18, 0x00000200); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 171 | |
| 172 | /* Select setting value in bps */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 173 | if (ddr_md == 0) { /* 1584Mbps */ |
| 174 | WriteReg_32(DBSC_E3_DBTR19, 0x01000040); |
| 175 | WriteReg_32(DBSC_E3_DBTR20, 0x020000D6); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 176 | } else { /* 1856Mbps */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 177 | WriteReg_32(DBSC_E3_DBTR19, 0x0129004B); |
| 178 | WriteReg_32(DBSC_E3_DBTR20, 0x020000FB); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 179 | } /* ddr_md */ |
| 180 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 181 | WriteReg_32(DBSC_E3_DBTR21, 0x00040004); |
| 182 | WriteReg_32(DBSC_E3_DBBL, 0x00000000); |
| 183 | WriteReg_32(DBSC_E3_DBODT0, 0x00000001); |
| 184 | WriteReg_32(DBSC_E3_DBADJ0, 0x00000001); |
| 185 | WriteReg_32(DBSC_E3_DBSYSCONF1, 0x00000002); |
| 186 | WriteReg_32(DBSC_E3_DBDFICNT0, 0x00000010); |
| 187 | WriteReg_32(DBSC_E3_DBBCAMDIS, 0x00000001); |
| 188 | WriteReg_32(DBSC_E3_DBSCHRW1, 0x00000046); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 189 | |
| 190 | /* Select setting value in bps */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 191 | if (ddr_md == 0) { /* 1584Mbps */ |
| 192 | WriteReg_32(DBSC_E3_SCFCTST0, 0x0D050B03); |
| 193 | WriteReg_32(DBSC_E3_SCFCTST1, 0x0306030C); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 194 | } else { /* 1856Mbps */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 195 | WriteReg_32(DBSC_E3_SCFCTST0, 0x0C050B03); |
| 196 | WriteReg_32(DBSC_E3_SCFCTST1, 0x0305030C); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 197 | } /* ddr_md */ |
| 198 | |
| 199 | /* rev.0.03 add Comment */ |
| 200 | /**************************************************************************** |
| 201 | * Initial_Step0( INITBYP ) |
| 202 | ***************************************************************************/ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 203 | WriteReg_32(DBSC_E3_DBPDLK0, 0x0000A55A); |
| 204 | WriteReg_32(DBSC_E3_DBCMD, 0x01840001); |
| 205 | WriteReg_32(DBSC_E3_DBCMD, 0x08840000); |
Marek Vasut | 432d767 | 2018-12-12 18:06:39 +0100 | [diff] [blame] | 206 | NOTICE("BL2: [COLD_BOOT]\n"); /* rev.0.11 */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 207 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000001); |
| 208 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x80010000); |
| 209 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006); |
| 210 | while ((BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 211 | |
| 212 | /* rev.0.03 add Comment */ |
| 213 | /**************************************************************************** |
| 214 | * Initial_Step1( ZCAL,PLLINIT,DCAL,PHYRST training ) |
| 215 | ***************************************************************************/ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 216 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000008); |
| 217 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x000B8000); |
| 218 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000090); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 219 | |
| 220 | /* Select setting value in bps */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 221 | if (ddr_md == 0) { /* 1584Mbps */ |
| 222 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x04058904); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 223 | } else { /* 1856Mbps */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 224 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x04058A04); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 225 | } /* ddr_md */ |
| 226 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 227 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000091); |
| 228 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x0007BB6B); |
| 229 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000095); |
| 230 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x0007BBAD); |
| 231 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000099); |
| 232 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x0007BB6B); |
| 233 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000090); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 234 | |
| 235 | /* Select setting value in bps */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 236 | if (ddr_md == 0) { /* 1584Mbps */ |
| 237 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x04058900); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 238 | } else { /* 1856Mbps */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 239 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x04058A00); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 240 | } /* ddr_md */ |
| 241 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 242 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000021); |
| 243 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x0024641E); |
| 244 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000001); |
| 245 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x00010073); |
| 246 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006); |
| 247 | while ((BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 248 | |
| 249 | /* rev.0.03 add Comment */ |
| 250 | /**************************************************************************** |
| 251 | * Initial_Step2( DRAMRST/DRAMINT training ) |
| 252 | ***************************************************************************/ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 253 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000090); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 254 | |
| 255 | /* Select setting value in bps */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 256 | if (ddr_md == 0) { /* 1584Mbps */ |
| 257 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x0C058900); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 258 | } else { /* 1856Mbps */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 259 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x0C058A00); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 260 | } /* ddr_md */ |
| 261 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 262 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000090); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 263 | |
| 264 | /* Select setting value in bps */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 265 | if (ddr_md == 0) { /* 1584Mbps */ |
| 266 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x04058900); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 267 | } else { /* 1856Mbps */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 268 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x04058A00); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 269 | } /* ddr_md */ |
| 270 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 271 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006); |
| 272 | while ((BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 273 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 274 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000003); |
Marek Vasut | 432d767 | 2018-12-12 18:06:39 +0100 | [diff] [blame] | 275 | if (byp_ctl == 1) { |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 276 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x0780C720); |
Marek Vasut | 432d767 | 2018-12-12 18:06:39 +0100 | [diff] [blame] | 277 | } else { |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 278 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x0780C700); |
Marek Vasut | 432d767 | 2018-12-12 18:06:39 +0100 | [diff] [blame] | 279 | } |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 280 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000007); |
| 281 | while ((BIT30 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 282 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 283 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000004); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 284 | |
| 285 | /* Select setting value in bps */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 286 | if (ddr_md == 0) { /* 1584Mbps */ |
| 287 | WriteReg_32(DBSC_E3_DBPDRGD0, (uint32_t)(REFRESH_RATE * 792 / 125) - 400 + 0x08B00000); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 288 | } else { /* 1856Mbps */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 289 | WriteReg_32(DBSC_E3_DBPDRGD0, (uint32_t)(REFRESH_RATE * 928 / 125) - 400 + 0x0A300000); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 290 | } /* ddr_md */ |
| 291 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 292 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000022); |
| 293 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x1000040B); |
| 294 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000023); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 295 | |
| 296 | /* Select setting value in bps */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 297 | if (ddr_md == 0) { /* 1584Mbps */ |
| 298 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x2D9C0B66); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 299 | } else { /* 1856Mbps */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 300 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x35A00D77); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 301 | } /* ddr_md */ |
| 302 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 303 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000024); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 304 | |
| 305 | /* Select setting value in bps */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 306 | if (ddr_md == 0) { /* 1584Mbps */ |
| 307 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x2A88B400); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 308 | } else { /* 1856Mbps */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 309 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x2A8A2C28); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 310 | } /* ddr_md */ |
| 311 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 312 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000025); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 313 | |
| 314 | /* Select setting value in bps */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 315 | if (ddr_md == 0) { /* 1584Mbps */ |
| 316 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x30005200); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 317 | } else { /* 1856Mbps */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 318 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x30005E00); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 319 | } /* ddr_md */ |
| 320 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 321 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000026); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 322 | |
| 323 | /* Select setting value in bps */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 324 | if (ddr_md == 0) { /* 1584Mbps */ |
| 325 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x0014A9C9); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 326 | } else { /* 1856Mbps */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 327 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x0014CB49); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 328 | } /* ddr_md */ |
| 329 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 330 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000027); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 331 | |
| 332 | /* Select setting value in bps */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 333 | if (ddr_md == 0) { /* 1584Mbps */ |
| 334 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000D70); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 335 | } else { /* 1856Mbps */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 336 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000F14); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 337 | } /* ddr_md */ |
| 338 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 339 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000028); |
| 340 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000046); |
| 341 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000029); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 342 | |
| 343 | /* Select setting value in bps */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 344 | if (ddr_md == 0) { /* 1584Mbps */ |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 345 | if (REFRESH_RATE > 3900) { |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 346 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000018); /* [7]SRT=0 */ |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 347 | } else { |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 348 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000098); /* [7]SRT=1 */ |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 349 | } |
| 350 | } else { /* 1856Mbps */ |
| 351 | if (REFRESH_RATE > 3900) { |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 352 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000020); /* [7]SRT=0 */ |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 353 | } else { |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 354 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x000000A0); /* [7]SRT=1 */ |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 355 | } /* REFRESH_RATE */ |
| 356 | } /* ddr_md */ |
| 357 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 358 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x0000002C); |
| 359 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x81003047); |
| 360 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000020); |
| 361 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x00181884); |
| 362 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x0000001A); |
| 363 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x33C03C10); |
| 364 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006); |
| 365 | while ((BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 366 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 367 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A7); |
| 368 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x0D0D0D0D); |
| 369 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A8); |
| 370 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x0D0D0D0D); |
| 371 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A9); |
| 372 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x000D0D0D); |
| 373 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C7); |
| 374 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x0D0D0D0D); |
| 375 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C8); |
| 376 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x0D0D0D0D); |
| 377 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C9); |
| 378 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x000D0D0D); |
| 379 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E7); |
| 380 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x0D0D0D0D); |
| 381 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E8); |
| 382 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x0D0D0D0D); |
| 383 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E9); |
| 384 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x000D0D0D); |
| 385 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000107); |
| 386 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x0D0D0D0D); |
| 387 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000108); |
| 388 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x0D0D0D0D); |
| 389 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000109); |
| 390 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x000D0D0D); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 391 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 392 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000001); |
| 393 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x00010181); |
| 394 | WriteReg_32(DBSC_E3_DBCMD, 0x08840001); |
| 395 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006); |
| 396 | while ((BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 397 | |
| 398 | /* rev.0.03 add Comment */ |
| 399 | /**************************************************************************** |
| 400 | * Initial_Step3( WL/QSG training ) |
| 401 | ***************************************************************************/ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 402 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000001); |
| 403 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x00010601); |
| 404 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006); |
| 405 | while ((BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 406 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 407 | for (i = 0; i < 4; i++) { |
| 408 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B1 + i * 0x20); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 409 | RegVal_R5 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0x0000FF00) >> 0x8; |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 410 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B4 + i * 0x20); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 411 | RegVal_R6 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0x000000FF); |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 412 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B3 + i * 0x20); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 413 | RegVal_R7 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0x00000007); |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 414 | if (RegVal_R6 > 0) { |
| 415 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B2 + i * 0x20); |
| 416 | RegVal_R2 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFFF8); |
| 417 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B2 + i * 0x20); |
| 418 | WriteReg_32(DBSC_E3_DBPDRGD0, RegVal_R2 | ((RegVal_R7 + 0x1) & 0x00000007)); |
| 419 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B0 + i * 0x20); |
| 420 | RegVal_R2 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFF00); |
| 421 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B0 + i * 0x20); |
| 422 | WriteReg_32(DBSC_E3_DBPDRGD0, RegVal_R2 | RegVal_R6); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 423 | } else { |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 424 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B2 + i * 0x20); |
| 425 | RegVal_R2 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFFF8); |
| 426 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B2 + i * 0x20); |
| 427 | WriteReg_32(DBSC_E3_DBPDRGD0, RegVal_R2 | RegVal_R7); |
| 428 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B0 + i * 0x20); |
| 429 | RegVal_R2 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFF00); |
| 430 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B0 + i * 0x20); |
| 431 | WriteReg_32(DBSC_E3_DBPDRGD0, RegVal_R2 | ((RegVal_R6 + ((RegVal_R5) << 1)) & 0x000000FF)); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 432 | } /* RegVal_R6 */ |
| 433 | } /* for i */ |
| 434 | |
Marek Vasut | 432d767 | 2018-12-12 18:06:39 +0100 | [diff] [blame] | 435 | /* rev.0.10 move Comment */ |
| 436 | /**************************************************************************** |
| 437 | * Initial_Step4( WLADJ training ) |
| 438 | ***************************************************************************/ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 439 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000005); |
| 440 | WriteReg_32(DBSC_E3_DBPDRGD0, 0xC1AA00C0); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 441 | |
| 442 | /* rev.0.08 */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 443 | if (pdqsr_ctl == 1){} else { |
| 444 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A0); |
| 445 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5); |
| 446 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C0); |
| 447 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5); |
| 448 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E0); |
| 449 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5); |
| 450 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000100); |
| 451 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5); |
Marek Vasut | 432d767 | 2018-12-12 18:06:39 +0100 | [diff] [blame] | 452 | } |
| 453 | |
| 454 | /* PDR always off */ /* rev.0.10 */ |
| 455 | if (pdr_ctl == 1) { |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 456 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A3); |
| 457 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000008); |
| 458 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C3); |
| 459 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000008); |
| 460 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E3); |
| 461 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000008); |
| 462 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000103); |
| 463 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000008); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 464 | } |
| 465 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 466 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000001); |
| 467 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x00010801); |
| 468 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006); |
| 469 | while ((BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 470 | |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 471 | /**************************************************************************** |
Marek Vasut | 432d767 | 2018-12-12 18:06:39 +0100 | [diff] [blame] | 472 | * Initial_Step5(Read Data Bit Deskew) |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 473 | ***************************************************************************/ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 474 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000005); |
| 475 | WriteReg_32(DBSC_E3_DBPDRGD0, 0xC1AA00D8); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 476 | |
| 477 | /* rev.0.08 */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 478 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000001); |
| 479 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x00011001); |
| 480 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006); |
| 481 | while ((BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 482 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 483 | if (pdqsr_ctl == 1) { |
| 484 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A0); |
| 485 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5); |
| 486 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C0); |
| 487 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5); |
| 488 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E0); |
| 489 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5); |
| 490 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000100); |
| 491 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 492 | } |
| 493 | |
Marek Vasut | 432d767 | 2018-12-12 18:06:39 +0100 | [diff] [blame] | 494 | /* PDR dynamic */ /* rev.0.10 */ |
| 495 | if (pdr_ctl == 1) { |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 496 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A3); |
| 497 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000000); |
| 498 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C3); |
| 499 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000000); |
| 500 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E3); |
| 501 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000000); |
| 502 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000103); |
| 503 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000000); |
Marek Vasut | 432d767 | 2018-12-12 18:06:39 +0100 | [diff] [blame] | 504 | } |
| 505 | |
| 506 | /**************************************************************************** |
| 507 | * Initial_Step6(Write Data Bit Deskew) |
| 508 | ***************************************************************************/ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 509 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000001); |
| 510 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x00012001); |
| 511 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006); |
| 512 | while ((BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 513 | |
Marek Vasut | 432d767 | 2018-12-12 18:06:39 +0100 | [diff] [blame] | 514 | /**************************************************************************** |
| 515 | * Initial_Step7(Read Data Eye Training) |
| 516 | ***************************************************************************/ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 517 | if (pdqsr_ctl == 1) { |
| 518 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A0); |
| 519 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C000285); |
| 520 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C0); |
| 521 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C000285); |
| 522 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E0); |
| 523 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C000285); |
| 524 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000100); |
| 525 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C000285); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 526 | } |
| 527 | |
Marek Vasut | 432d767 | 2018-12-12 18:06:39 +0100 | [diff] [blame] | 528 | /* PDR always off */ /* rev.0.10 */ |
| 529 | if (pdr_ctl == 1) { |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 530 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A3); |
| 531 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000008); |
| 532 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C3); |
| 533 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000008); |
| 534 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E3); |
| 535 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000008); |
| 536 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000103); |
| 537 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000008); |
Marek Vasut | 432d767 | 2018-12-12 18:06:39 +0100 | [diff] [blame] | 538 | } |
| 539 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 540 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000001); |
| 541 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x00014001); |
| 542 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006); |
| 543 | while ((BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 544 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 545 | if (pdqsr_ctl == 1) { |
| 546 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A0); |
| 547 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5); |
| 548 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C0); |
| 549 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5); |
| 550 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E0); |
| 551 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5); |
| 552 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000100); |
| 553 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 554 | } |
| 555 | |
Marek Vasut | 432d767 | 2018-12-12 18:06:39 +0100 | [diff] [blame] | 556 | /* PDR dynamic */ /* rev.0.10 */ |
| 557 | if (pdr_ctl == 1) { |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 558 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A3); |
| 559 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000000); |
| 560 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C3); |
| 561 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000000); |
| 562 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E3); |
| 563 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000000); |
| 564 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000103); |
| 565 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000000); |
Marek Vasut | 432d767 | 2018-12-12 18:06:39 +0100 | [diff] [blame] | 566 | } |
| 567 | |
| 568 | /**************************************************************************** |
| 569 | * Initial_Step8(Write Data Eye Training) |
| 570 | ***************************************************************************/ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 571 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000001); |
| 572 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x00018001); |
| 573 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006); |
| 574 | while ((BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 575 | |
| 576 | /* rev.0.03 add Comment */ |
| 577 | /**************************************************************************** |
| 578 | * Initial_Step3_2( DQS Gate Training ) |
| 579 | ***************************************************************************/ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 580 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A0); |
| 581 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C000285); |
| 582 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C0); |
| 583 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C000285); |
| 584 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E0); |
| 585 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C000285); |
| 586 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000100); |
| 587 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C000285); |
| 588 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x0000002C); |
| 589 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x81003087); |
| 590 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000001); |
| 591 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x00010401); |
| 592 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006); |
| 593 | while ((BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 594 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 595 | for (i = 0; i < 4; i++) { |
| 596 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B1 + i * 0x20); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 597 | RegVal_R5 = ((ReadReg_32(DBSC_E3_DBPDRGD0) & 0x0000FF00) >> 0x8); |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 598 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B4 + i * 0x20); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 599 | RegVal_R6 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0x000000FF); |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 600 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B3 + i * 0x20); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 601 | RegVal_R7 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0x00000007); |
| 602 | RegVal_R12 = (RegVal_R5 >> 0x2); |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 603 | if (RegVal_R12 < RegVal_R6) { |
| 604 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B2 + i * 0x20); |
| 605 | RegVal_R2 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFFF8); |
| 606 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B2 + i * 0x20); |
| 607 | WriteReg_32(DBSC_E3_DBPDRGD0, RegVal_R2 | ((RegVal_R7 + 0x1) & 0x00000007)); |
| 608 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B0 + i * 0x20); |
| 609 | RegVal_R2 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFF00); |
| 610 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B0 + i * 0x20); |
| 611 | WriteReg_32(DBSC_E3_DBPDRGD0, RegVal_R2 | ((RegVal_R6 - (RegVal_R12)) & 0x000000FF)); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 612 | } else { |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 613 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B2 + i * 0x20); |
| 614 | RegVal_R2 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFFF8); |
| 615 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B2 + i * 0x20); |
| 616 | WriteReg_32(DBSC_E3_DBPDRGD0, RegVal_R2 | (RegVal_R7 & 0x00000007)); |
| 617 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B0 + i * 0x20); |
| 618 | RegVal_R2 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFF00); |
| 619 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B0 + i * 0x20); |
| 620 | WriteReg_32(DBSC_E3_DBPDRGD0, RegVal_R2 | ((RegVal_R6 + (RegVal_R5) + ((RegVal_R5) >> 1) + (RegVal_R12)) & 0x000000FF)); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 621 | } /* RegVal_R12 < RegVal_R6 */ |
| 622 | } /* for i */ |
| 623 | |
Marek Vasut | 432d767 | 2018-12-12 18:06:39 +0100 | [diff] [blame] | 624 | /* rev.0.10 move Comment */ |
| 625 | /**************************************************************************** |
| 626 | * Initial_Step5-2_7-2( Rd bit Rd eye ) |
| 627 | ***************************************************************************/ |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 628 | /* rev.0.08 */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 629 | if (pdqsr_ctl == 1){} else { |
| 630 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A0); |
| 631 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5); |
| 632 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C0); |
| 633 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5); |
| 634 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E0); |
| 635 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5); |
| 636 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000100); |
| 637 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5); |
Marek Vasut | 432d767 | 2018-12-12 18:06:39 +0100 | [diff] [blame] | 638 | } |
| 639 | |
| 640 | /* PDR always off */ /* rev.0.10 */ |
| 641 | if (pdr_ctl == 1) { |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 642 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A3); |
| 643 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000008); |
| 644 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C3); |
| 645 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000008); |
| 646 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E3); |
| 647 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000008); |
| 648 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000103); |
| 649 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000008); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 650 | } |
| 651 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 652 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000001); |
| 653 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x00015001); |
| 654 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006); |
| 655 | while ((BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 656 | |
| 657 | /* rev.0.08 */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 658 | if (lcdl_ctl == 1) { |
| 659 | for (i = 0; i < 4; i++) { |
| 660 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B0 + i * 0x20); |
| 661 | dqsgd_0c = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0x000000FF); |
| 662 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B1 + i * 0x20); |
| 663 | bdlcount_0c = ((ReadReg_32(DBSC_E3_DBPDRGD0) & 0x0000FF00) >> 8); |
| 664 | bdlcount_0c_div2 = (bdlcount_0c >> 1); |
| 665 | bdlcount_0c_div4 = (bdlcount_0c >> 2); |
| 666 | bdlcount_0c_div8 = (bdlcount_0c >> 3); |
| 667 | bdlcount_0c_div16 = (bdlcount_0c >> 4); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 668 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 669 | if (ddr_md == 0) { /* 1584Mbps */ |
| 670 | lcdl_judge1 = bdlcount_0c_div2 + bdlcount_0c_div4 + bdlcount_0c_div8; |
| 671 | lcdl_judge2 = bdlcount_0c + bdlcount_0c_div4 + bdlcount_0c_div16; |
| 672 | } else { /* 1856Mbps */ |
| 673 | lcdl_judge1 = bdlcount_0c_div2 + bdlcount_0c_div4; |
| 674 | lcdl_judge2 = bdlcount_0c + bdlcount_0c_div4; |
| 675 | } /* ddr_md */ |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 676 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 677 | if (dqsgd_0c > lcdl_judge1) { |
| 678 | if (dqsgd_0c <= lcdl_judge2) { |
| 679 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B0 + i * 0x20); |
| 680 | RegVal = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFF00); |
| 681 | WriteReg_32(DBSC_E3_DBPDRGD0, ((dqsgd_0c - bdlcount_0c_div8) | RegVal)); |
| 682 | } else { |
| 683 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B0 + i * 0x20); |
| 684 | RegVal = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFF00); |
| 685 | WriteReg_32(DBSC_E3_DBPDRGD0, RegVal); |
| 686 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B2 + i * 0x20); |
| 687 | gatesl_0c = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0x00000007); |
| 688 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B2 + i * 0x20); |
| 689 | RegVal = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFFF8); |
| 690 | WriteReg_32(DBSC_E3_DBPDRGD0, (RegVal | (gatesl_0c + 1))); |
| 691 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000AF + i * 0x20); |
| 692 | RegVal = (ReadReg_32(DBSC_E3_DBPDRGD0)); |
| 693 | rdqsd_0c = (RegVal & 0x0000FF00) >> 8; |
| 694 | rdqsnd_0c = (RegVal & 0x00FF0000) >> 16; |
| 695 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000AF + i * 0x20); |
| 696 | WriteReg_32(DBSC_E3_DBPDRGD0, ((RegVal & 0xFF0000FF) | ((rdqsd_0c + bdlcount_0c_div4) << 8) | ((rdqsnd_0c + bdlcount_0c_div4) << 16))); |
| 697 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000AA + i * 0x20); |
| 698 | RegVal = (ReadReg_32(DBSC_E3_DBPDRGD0)); |
| 699 | rbd_0c[0] = (RegVal) &0x0000001f; |
| 700 | rbd_0c[1] = (RegVal >> 8) & 0x0000001f; |
| 701 | rbd_0c[2] = (RegVal >> 16) & 0x0000001f; |
| 702 | rbd_0c[3] = (RegVal >> 24) & 0x0000001f; |
| 703 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000AA + i * 0x20); |
| 704 | RegVal = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xE0E0E0E0); |
| 705 | for (j = 0; j < 4; j++) { |
| 706 | rbd_0c[j] = (rbd_0c[j] + bdlcount_0c_div4); |
| 707 | if (rbd_0c[j] > 0x1F) rbd_0c[j] = 0x1F; |
| 708 | RegVal = RegVal | (rbd_0c[j] << 8 * j); |
| 709 | } |
| 710 | WriteReg_32(DBSC_E3_DBPDRGD0, RegVal); |
| 711 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000AB + i * 0x20); |
| 712 | RegVal = (ReadReg_32(DBSC_E3_DBPDRGD0)); |
| 713 | rbd_0c[0] = (RegVal) &0x0000001f; |
| 714 | rbd_0c[1] = (RegVal >> 8) & 0x0000001f; |
| 715 | rbd_0c[2] = (RegVal >> 16) & 0x0000001f; |
| 716 | rbd_0c[3] = (RegVal >> 24) & 0x0000001f; |
| 717 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000AB + i * 0x20); |
| 718 | RegVal = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xE0E0E0E0); |
| 719 | for (j = 0; j < 4; j++) { |
| 720 | rbd_0c[j] = (rbd_0c[j] + bdlcount_0c_div4); |
| 721 | if (rbd_0c[j] > 0x1F) rbd_0c[j] = 0x1F; |
| 722 | RegVal = RegVal | (rbd_0c[j] << 8 * j); |
| 723 | } |
| 724 | WriteReg_32(DBSC_E3_DBPDRGD0, RegVal); |
| 725 | } |
| 726 | } |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 727 | } |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 728 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000002); |
| 729 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x07D81E37); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 730 | } |
| 731 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 732 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000003); |
Marek Vasut | 432d767 | 2018-12-12 18:06:39 +0100 | [diff] [blame] | 733 | if (byp_ctl == 1) { |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 734 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x0380C720); |
Marek Vasut | 432d767 | 2018-12-12 18:06:39 +0100 | [diff] [blame] | 735 | } else { |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 736 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x0380C700); |
Marek Vasut | 432d767 | 2018-12-12 18:06:39 +0100 | [diff] [blame] | 737 | } |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 738 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000007); |
| 739 | while ((BIT30 & ReadReg_32(DBSC_E3_DBPDRGD0)) != 0); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 740 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 741 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000021); |
| 742 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x0024643E); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 743 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 744 | WriteReg_32(DBSC_E3_DBBUS0CNF1, 0x00000010); |
| 745 | WriteReg_32(DBSC_E3_DBCALCNF, (uint32_t)(64000000 / REFRESH_RATE) + 0x01000000); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 746 | /* Select setting value in bps */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 747 | if (ddr_md == 0) { /* 1584Mbps */ |
| 748 | WriteReg_32(DBSC_E3_DBRFCNF1, (uint32_t)(REFRESH_RATE * 99 / 125) + 0x00080000); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 749 | } else { /* 1856Mbps */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 750 | WriteReg_32(DBSC_E3_DBRFCNF1, (uint32_t)(REFRESH_RATE * 116 / 125) + 0x00080000); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 751 | } /* ddr_md */ |
| 752 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 753 | WriteReg_32(DBSC_E3_DBRFCNF2, 0x00010000); |
| 754 | WriteReg_32(DBSC_E3_DBDFICUPDCNF, 0x40100001); |
| 755 | WriteReg_32(DBSC_E3_DBRFEN, 0x00000001); |
| 756 | WriteReg_32(DBSC_E3_DBACEN, 0x00000001); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 757 | |
| 758 | /* rev.0.08 */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 759 | if (pdqsr_ctl == 1) { |
| 760 | WriteReg_32(0xE67F0018, 0x00000001); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 761 | RegVal = ReadReg_32(0x40000000); |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 762 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000000); |
| 763 | WriteReg_32(DBSC_E3_DBPDRGD0, RegVal); |
| 764 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A0); |
| 765 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5); |
| 766 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C0); |
| 767 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5); |
| 768 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E0); |
| 769 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5); |
| 770 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000100); |
| 771 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 772 | } |
| 773 | |
Marek Vasut | 432d767 | 2018-12-12 18:06:39 +0100 | [diff] [blame] | 774 | /* PDR dynamic */ /* rev.0.10 */ |
| 775 | if (pdr_ctl == 1) { |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 776 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A3); |
| 777 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000000); |
| 778 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C3); |
| 779 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000000); |
| 780 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E3); |
| 781 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000000); |
| 782 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000103); |
| 783 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000000); |
Marek Vasut | 432d767 | 2018-12-12 18:06:39 +0100 | [diff] [blame] | 784 | } |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 785 | |
| 786 | /* rev.0.03 add Comment */ |
| 787 | /**************************************************************************** |
| 788 | * Initial_Step9( Initial End ) |
| 789 | ***************************************************************************/ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 790 | WriteReg_32(DBSC_E3_DBPDLK0, 0x00000000); |
| 791 | WriteReg_32(DBSC_E3_DBSYSCNT0, 0x00000000); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 792 | |
| 793 | #ifdef ddr_qos_init_setting /* only for non qos_init */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 794 | WriteReg_32(DBSC_E3_DBSYSCNT0, 0x00001234); |
| 795 | WriteReg_32(DBSC_E3_DBCAM0CNF1, 0x00043218); |
| 796 | WriteReg_32(DBSC_E3_DBCAM0CNF2, 0x000000F4); |
| 797 | WriteReg_32(DBSC_E3_DBSCHCNT0, 0x000f0037); |
| 798 | WriteReg_32(DBSC_E3_DBSCHSZ0, 0x00000001); |
| 799 | WriteReg_32(DBSC_E3_DBSCHRW0, 0x22421111); |
| 800 | WriteReg_32(DBSC_E3_SCFCTST2, 0x012F1123); |
| 801 | WriteReg_32(DBSC_E3_DBSCHQOS00, 0x00000F00); |
| 802 | WriteReg_32(DBSC_E3_DBSCHQOS01, 0x00000B00); |
| 803 | WriteReg_32(DBSC_E3_DBSCHQOS02, 0x00000000); |
| 804 | WriteReg_32(DBSC_E3_DBSCHQOS03, 0x00000000); |
| 805 | WriteReg_32(DBSC_E3_DBSCHQOS40, 0x00000300); |
| 806 | WriteReg_32(DBSC_E3_DBSCHQOS41, 0x000002F0); |
| 807 | WriteReg_32(DBSC_E3_DBSCHQOS42, 0x00000200); |
| 808 | WriteReg_32(DBSC_E3_DBSCHQOS43, 0x00000100); |
| 809 | WriteReg_32(DBSC_E3_DBSCHQOS90, 0x00000100); |
| 810 | WriteReg_32(DBSC_E3_DBSCHQOS91, 0x000000F0); |
| 811 | WriteReg_32(DBSC_E3_DBSCHQOS92, 0x000000A0); |
| 812 | WriteReg_32(DBSC_E3_DBSCHQOS93, 0x00000040); |
| 813 | WriteReg_32(DBSC_E3_DBSCHQOS130, 0x00000100); |
| 814 | WriteReg_32(DBSC_E3_DBSCHQOS131, 0x000000F0); |
| 815 | WriteReg_32(DBSC_E3_DBSCHQOS132, 0x000000A0); |
| 816 | WriteReg_32(DBSC_E3_DBSCHQOS133, 0x00000040); |
| 817 | WriteReg_32(DBSC_E3_DBSCHQOS140, 0x000000C0); |
| 818 | WriteReg_32(DBSC_E3_DBSCHQOS141, 0x000000B0); |
| 819 | WriteReg_32(DBSC_E3_DBSCHQOS142, 0x00000080); |
| 820 | WriteReg_32(DBSC_E3_DBSCHQOS143, 0x00000040); |
| 821 | WriteReg_32(DBSC_E3_DBSCHQOS150, 0x00000040); |
| 822 | WriteReg_32(DBSC_E3_DBSCHQOS151, 0x00000030); |
| 823 | WriteReg_32(DBSC_E3_DBSCHQOS152, 0x00000020); |
| 824 | WriteReg_32(DBSC_E3_DBSCHQOS153, 0x00000010); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 825 | |
| 826 | /* rev.0.08 */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 827 | if (pdqsr_ctl == 1){} else { |
| 828 | WriteReg_32(0xE67F0018, 0x00000001); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 829 | } |
| 830 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 831 | WriteReg_32(DBSC_E3_DBSYSCNT0, 0x00000000); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 832 | #endif |
| 833 | |
| 834 | return 1; /* rev.0.04 Restore the return code */ |
| 835 | |
| 836 | } /* init_ddr */ |
| 837 | |
| 838 | /* rev.0.04 add function */ |
| 839 | uint32_t recovery_from_backup_mode(void) |
| 840 | { |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 841 | /**************************************************************************** |
| 842 | * recovery_Step0(DBSC Setting 1) / same "init_ddr" |
| 843 | ***************************************************************************/ |
| 844 | uint32_t RegVal_R2, RegVal_R5, RegVal_R6, RegVal_R7, RegVal_R12, i; |
| 845 | uint32_t ddr_md; |
| 846 | uint32_t err; |
| 847 | |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 848 | /* rev.0.08 */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 849 | uint32_t RegVal, j; |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 850 | uint32_t dqsgd_0c, bdlcount_0c, bdlcount_0c_div2, bdlcount_0c_div4, bdlcount_0c_div8, bdlcount_0c_div16; |
| 851 | uint32_t gatesl_0c, rdqsd_0c, rdqsnd_0c, rbd_0c[4]; |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 852 | uint32_t pdqsr_ctl, lcdl_ctl, lcdl_judge1, lcdl_judge2; |
Marek Vasut | 432d767 | 2018-12-12 18:06:39 +0100 | [diff] [blame] | 853 | /* rev.0.10 */ |
| 854 | uint32_t pdr_ctl; |
| 855 | /* rev.0.11 */ |
| 856 | uint32_t byp_ctl; |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 857 | |
| 858 | /* rev.0.08 */ |
| 859 | if ((ReadReg_32(0xFFF00044) & 0x000000FF) == 0x00000000) { |
| 860 | pdqsr_ctl = 1; |
| 861 | lcdl_ctl = 1; |
Marek Vasut | 432d767 | 2018-12-12 18:06:39 +0100 | [diff] [blame] | 862 | pdr_ctl = 1; /* rev.0.10 */ |
| 863 | byp_ctl = 1; /* rev.0.11 */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 864 | } else { |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 865 | pdqsr_ctl = 0; |
| 866 | lcdl_ctl = 0; |
Marek Vasut | 432d767 | 2018-12-12 18:06:39 +0100 | [diff] [blame] | 867 | pdr_ctl = 0; /* rev.0.10 */ |
| 868 | byp_ctl = 0; /* rev.0.11 */ |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 869 | } |
| 870 | |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 871 | /* Judge the DDR bit rate (ddr_md : 0 = 1584Mbps, 1 = 1856Mbps) */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 872 | ddr_md = (ReadReg_32(RST_MODEMR) >> 19) & BIT0; |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 873 | |
| 874 | /* 1584Mbps setting */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 875 | if (ddr_md == 0) { |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 876 | /* CPG setting ===============================================*/ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 877 | WriteReg_32(CPG_CPGWPR, 0x5A5AFFFF); |
| 878 | WriteReg_32(CPG_CPGWPCR, 0xA5A50000); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 879 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 880 | WriteReg_32(CPG_SRCR4, 0x20000000); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 881 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 882 | WriteReg_32(0xE61500DC, 0xe2200000); /* Change to 1584Mbps */ |
| 883 | while ((BIT11 & ReadReg_32(CPG_PLLECR)) == 0); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 884 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 885 | WriteReg_32(CPG_SRSTCLR4, 0x20000000); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 886 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 887 | WriteReg_32(CPG_CPGWPCR, 0xA5A50001); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 888 | |
| 889 | /* CPG setting ===============================================*/ |
| 890 | } /* ddr_md */ |
| 891 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 892 | WriteReg_32(DBSC_E3_DBSYSCNT0, 0x00001234); |
| 893 | WriteReg_32(DBSC_E3_DBKIND, 0x00000007); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 894 | |
| 895 | #if RCAR_DRAM_DDR3L_MEMCONF == 0 |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 896 | WriteReg_32(DBSC_E3_DBMEMCONF00, 0x0f030a02); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 897 | #elif RCAR_DRAM_DDR3L_MEMCONF == 1 |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 898 | WriteReg_32(DBSC_E3_DBMEMCONF00, 0x10030a02); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 899 | #elif RCAR_DRAM_DDR3L_MEMCONF == 2 |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 900 | WriteReg_32(DBSC_E3_DBMEMCONF00, 0x10030b02); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 901 | #else |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 902 | WriteReg_32(DBSC_E3_DBMEMCONF00, 0x10030a02); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 903 | #endif |
| 904 | |
| 905 | /* rev.0.08 */ |
| 906 | #if RCAR_DRAM_DDR3L_MEMDUAL == 1 |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 907 | RegVal_R2 = (ReadReg_32(0xE6790614)); |
| 908 | WriteReg_32(0xE6790614, RegVal_R2 | 0x00000003); /* MCS1_N/MODT1 are activated. */ |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 909 | #endif |
| 910 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 911 | WriteReg_32(DBSC_E3_DBPHYCONF0, 0x00000001); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 912 | |
| 913 | /* Select setting value in bps */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 914 | if (ddr_md == 0) { /* 1584Mbps */ |
| 915 | WriteReg_32(DBSC_E3_DBTR0, 0x0000000B); |
| 916 | WriteReg_32(DBSC_E3_DBTR1, 0x00000008); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 917 | } else { /* 1856Mbps */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 918 | WriteReg_32(DBSC_E3_DBTR0, 0x0000000D); |
| 919 | WriteReg_32(DBSC_E3_DBTR1, 0x00000009); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 920 | } /* ddr_md */ |
| 921 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 922 | WriteReg_32(DBSC_E3_DBTR2, 0x00000000); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 923 | |
| 924 | /* Select setting value in bps */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 925 | if (ddr_md == 0) { /* 1584Mbps */ |
| 926 | WriteReg_32(DBSC_E3_DBTR3, 0x0000000B); |
| 927 | WriteReg_32(DBSC_E3_DBTR4, 0x000B000B); |
| 928 | WriteReg_32(DBSC_E3_DBTR5, 0x00000027); |
| 929 | WriteReg_32(DBSC_E3_DBTR6, 0x0000001C); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 930 | } else { /* 1856Mbps */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 931 | WriteReg_32(DBSC_E3_DBTR3, 0x0000000D); |
| 932 | WriteReg_32(DBSC_E3_DBTR4, 0x000D000D); |
| 933 | WriteReg_32(DBSC_E3_DBTR5, 0x0000002D); |
| 934 | WriteReg_32(DBSC_E3_DBTR6, 0x00000020); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 935 | } /* ddr_md */ |
| 936 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 937 | WriteReg_32(DBSC_E3_DBTR7, 0x00060006); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 938 | |
| 939 | /* Select setting value in bps */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 940 | if (ddr_md == 0) { /* 1584Mbps */ |
| 941 | WriteReg_32(DBSC_E3_DBTR8, 0x00000020); |
| 942 | WriteReg_32(DBSC_E3_DBTR9, 0x00000006); |
| 943 | WriteReg_32(DBSC_E3_DBTR10, 0x0000000C); |
| 944 | WriteReg_32(DBSC_E3_DBTR11, 0x0000000A); |
| 945 | WriteReg_32(DBSC_E3_DBTR12, 0x00120012); |
| 946 | WriteReg_32(DBSC_E3_DBTR13, 0x000000CE); |
| 947 | WriteReg_32(DBSC_E3_DBTR14, 0x00140005); |
| 948 | WriteReg_32(DBSC_E3_DBTR15, 0x00050004); |
| 949 | WriteReg_32(DBSC_E3_DBTR16, 0x071F0305); |
| 950 | WriteReg_32(DBSC_E3_DBTR17, 0x040C0000); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 951 | } else { /* 1856Mbps */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 952 | WriteReg_32(DBSC_E3_DBTR8, 0x00000021); |
| 953 | WriteReg_32(DBSC_E3_DBTR9, 0x00000007); |
| 954 | WriteReg_32(DBSC_E3_DBTR10, 0x0000000E); |
| 955 | WriteReg_32(DBSC_E3_DBTR11, 0x0000000C); |
| 956 | WriteReg_32(DBSC_E3_DBTR12, 0x00140014); |
| 957 | WriteReg_32(DBSC_E3_DBTR13, 0x000000F2); |
| 958 | WriteReg_32(DBSC_E3_DBTR14, 0x00170006); |
| 959 | WriteReg_32(DBSC_E3_DBTR15, 0x00060005); |
| 960 | WriteReg_32(DBSC_E3_DBTR16, 0x09210507); |
| 961 | WriteReg_32(DBSC_E3_DBTR17, 0x040E0000); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 962 | } /* ddr_md */ |
| 963 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 964 | WriteReg_32(DBSC_E3_DBTR18, 0x00000200); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 965 | |
| 966 | /* Select setting value in bps */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 967 | if (ddr_md == 0) { /* 1584Mbps */ |
| 968 | WriteReg_32(DBSC_E3_DBTR19, 0x01000040); |
| 969 | WriteReg_32(DBSC_E3_DBTR20, 0x020000D6); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 970 | } else { /* 1856Mbps */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 971 | WriteReg_32(DBSC_E3_DBTR19, 0x0129004B); |
| 972 | WriteReg_32(DBSC_E3_DBTR20, 0x020000FB); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 973 | } /* ddr_md */ |
| 974 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 975 | WriteReg_32(DBSC_E3_DBTR21, 0x00040004); |
| 976 | WriteReg_32(DBSC_E3_DBBL, 0x00000000); |
| 977 | WriteReg_32(DBSC_E3_DBODT0, 0x00000001); |
| 978 | WriteReg_32(DBSC_E3_DBADJ0, 0x00000001); |
| 979 | WriteReg_32(DBSC_E3_DBSYSCONF1, 0x00000002); |
| 980 | WriteReg_32(DBSC_E3_DBDFICNT0, 0x00000010); |
| 981 | WriteReg_32(DBSC_E3_DBBCAMDIS, 0x00000001); |
| 982 | WriteReg_32(DBSC_E3_DBSCHRW1, 0x00000046); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 983 | |
| 984 | /* Select setting value in bps */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 985 | if (ddr_md == 0) { /* 1584Mbps */ |
| 986 | WriteReg_32(DBSC_E3_SCFCTST0, 0x0D050B03); |
| 987 | WriteReg_32(DBSC_E3_SCFCTST1, 0x0306030C); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 988 | } else { /* 1856Mbps */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 989 | WriteReg_32(DBSC_E3_SCFCTST0, 0x0C050B03); |
| 990 | WriteReg_32(DBSC_E3_SCFCTST1, 0x0305030C); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 991 | } /* ddr_md */ |
| 992 | |
| 993 | /**************************************************************************** |
| 994 | * recovery_Step1(PHY setting 1) |
| 995 | ***************************************************************************/ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 996 | WriteReg_32(DBSC_E3_DBPDLK0, 0x0000A55A); |
| 997 | WriteReg_32(DBSC_E3_DBCMD, 0x01840001); |
| 998 | WriteReg_32(DBSC_E3_DBCMD, 0x0A840000); |
| 999 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000008); /* DDR_PLLCR */ |
| 1000 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x000B8000); |
| 1001 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000003); /* DDR_PGCR1 */ |
Marek Vasut | 432d767 | 2018-12-12 18:06:39 +0100 | [diff] [blame] | 1002 | if (byp_ctl == 1) { |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1003 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x0780C720); |
Marek Vasut | 432d767 | 2018-12-12 18:06:39 +0100 | [diff] [blame] | 1004 | } else { |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1005 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x0780C700); |
Marek Vasut | 432d767 | 2018-12-12 18:06:39 +0100 | [diff] [blame] | 1006 | } |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1007 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000020); /* DDR_DXCCR */ |
| 1008 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x00181884); |
| 1009 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x0000001A); /* DDR_ACIOCR0 */ |
| 1010 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x33C03C10); |
| 1011 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000007); |
| 1012 | while ((BIT30 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1013 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1014 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000004); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1015 | |
| 1016 | /* Select setting value in bps */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1017 | if (ddr_md == 0) { /* 1584Mbps */ |
| 1018 | WriteReg_32(DBSC_E3_DBPDRGD0, (uint32_t)(REFRESH_RATE * 792 / 125) - 400 + 0x08B00000); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1019 | } else { /* 1856Mbps */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1020 | WriteReg_32(DBSC_E3_DBPDRGD0, (uint32_t)(REFRESH_RATE * 928 / 125) - 400 + 0x0A300000); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1021 | } /* ddr_md */ |
| 1022 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1023 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000022); |
| 1024 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x1000040B); |
| 1025 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000023); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1026 | |
| 1027 | /* Select setting value in bps */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1028 | if (ddr_md == 0) { /* 1584Mbps */ |
| 1029 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x2D9C0B66); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1030 | } else { /* 1856Mbps */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1031 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x35A00D77); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1032 | } /* ddr_md */ |
| 1033 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1034 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000024); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1035 | |
| 1036 | /* Select setting value in bps */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1037 | if (ddr_md == 0) { /* 1584Mbps */ |
| 1038 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x2A88B400); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1039 | } else { /* 1856Mbps */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1040 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x2A8A2C28); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1041 | } /* ddr_md */ |
| 1042 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1043 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000025); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1044 | |
| 1045 | /* Select setting value in bps */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1046 | if (ddr_md == 0) { /* 1584Mbps */ |
| 1047 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x30005200); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1048 | } else { /* 1856Mbps */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1049 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x30005E00); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1050 | } /* ddr_md */ |
| 1051 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1052 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000026); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1053 | |
| 1054 | /* Select setting value in bps */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1055 | if (ddr_md == 0) { /* 1584Mbps */ |
| 1056 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x0014A9C9); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1057 | } else { /* 1856Mbps */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1058 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x0014CB49); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1059 | } /* ddr_md */ |
| 1060 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1061 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000027); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1062 | |
| 1063 | /* Select setting value in bps */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1064 | if (ddr_md == 0) { /* 1584Mbps */ |
| 1065 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000D70); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1066 | } else { /* 1856Mbps */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1067 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000F14); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1068 | } /* ddr_md */ |
| 1069 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1070 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000028); |
| 1071 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000046); |
| 1072 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000029); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1073 | |
| 1074 | /* Select setting value in bps */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1075 | if (ddr_md == 0) { /* 1584Mbps */ |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1076 | if (REFRESH_RATE > 3900) { |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1077 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000018); /* [7]SRT=0 */ |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1078 | } else { |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1079 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000098); /* [7]SRT=1 */ |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1080 | } |
| 1081 | } else { /* 1856Mbps */ |
| 1082 | if (REFRESH_RATE > 3900) { |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1083 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000020); /* [7]SRT=0 */ |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1084 | } else { |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1085 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x000000A0); /* [7]SRT=1 */ |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1086 | } /* REFRESH_RATE */ |
| 1087 | } /* ddr_md */ |
| 1088 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1089 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x0000002C); |
| 1090 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x81003047); |
| 1091 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000091); |
| 1092 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x0007BB6B); |
| 1093 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000095); |
| 1094 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x0007BBAD); |
| 1095 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000099); |
| 1096 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x0007BB6B); |
| 1097 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000021); /* DDR_DSGCR */ |
| 1098 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x0024641E); |
| 1099 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006); /* DDR_PGSR0 */ |
| 1100 | while ((BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1101 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1102 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000001); /* DDR_PIR */ |
| 1103 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x40010000); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1104 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1105 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006); /* DDR_PGSR0 */ |
| 1106 | while ((BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1107 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1108 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000092); /* DDR_ZQ0DR */ |
| 1109 | WriteReg_32(DBSC_E3_DBPDRGD0, 0xC2C59AB5); |
| 1110 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000096); /* DDR_ZQ1DR */ |
| 1111 | WriteReg_32(DBSC_E3_DBPDRGD0, 0xC4285FBF); |
| 1112 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x0000009A); /* DDR_ZQ2DR */ |
| 1113 | WriteReg_32(DBSC_E3_DBPDRGD0, 0xC2C59AB5); |
| 1114 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000090); /* DDR_ZQCR */ |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1115 | |
| 1116 | /* Select setting value in bps */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1117 | if (ddr_md == 0) { /* 1584Mbps */ |
| 1118 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x0C058900); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1119 | } else { /* 1856Mbps */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1120 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x0C058A00); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1121 | } /* ddr_md */ |
| 1122 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1123 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000090); /* DDR_ZQCR */ |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1124 | |
| 1125 | /* Select setting value in bps */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1126 | if (ddr_md == 0) { /* 1584Mbps */ |
| 1127 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x04058900); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1128 | } else { /* 1856Mbps */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1129 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x04058A00); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1130 | } /* ddr_md */ |
| 1131 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1132 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000001); /* DDR_PIR */ |
| 1133 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x00050001); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1134 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1135 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006); /* DDR_PGSR0 */ |
| 1136 | while ((BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1137 | |
| 1138 | /* ddr backupmode end */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1139 | if (ddrBackup) { |
Marek Vasut | 5651989 | 2019-01-21 23:11:33 +0100 | [diff] [blame] | 1140 | NOTICE("BL2: [WARM_BOOT]\n"); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1141 | } else { |
Marek Vasut | 5651989 | 2019-01-21 23:11:33 +0100 | [diff] [blame] | 1142 | NOTICE("BL2: [COLD_BOOT]\n"); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1143 | } /* ddrBackup */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1144 | err = rcar_dram_update_boot_status(ddrBackup); |
| 1145 | if (err) { |
Marek Vasut | 5651989 | 2019-01-21 23:11:33 +0100 | [diff] [blame] | 1146 | NOTICE("BL2: [BOOT_STATUS_UPDATE_ERROR]\n"); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1147 | return INITDRAM_ERR_I; |
| 1148 | } /* err */ |
| 1149 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1150 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000092); /* DDR_ZQ0DR */ |
| 1151 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x02C59AB5); |
| 1152 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000096); /* DDR_ZQ1DR */ |
| 1153 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x04285FBF); |
| 1154 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x0000009A); /* DDR_ZQ2DR */ |
| 1155 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x02C59AB5); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1156 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1157 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000001); /* DDR_PIR */ |
| 1158 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x08000000); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1159 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1160 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000001); /* DDR_PIR */ |
| 1161 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000003); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1162 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1163 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006); /* DDR_PGSR0 */ |
| 1164 | while ((BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1165 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1166 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000001); /* DDR_PIR */ |
| 1167 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x80010000); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1168 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1169 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006); /* DDR_PGSR0 */ |
| 1170 | while ((BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1171 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1172 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000001); /* DDR_PIR */ |
| 1173 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x00010073); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1174 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1175 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006); /* DDR_PGSR0 */ |
| 1176 | while ((BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1177 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1178 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000090); /* DDR_ZQCR */ |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1179 | |
| 1180 | /* Select setting value in bps */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1181 | if (ddr_md == 0) { /* 1584Mbps */ |
| 1182 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x0C058900); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1183 | } else { /* 1856Mbps */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1184 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x0C058A00); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1185 | } /* ddr_md */ |
| 1186 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1187 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000090); /* DDR_ZQCR */ |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1188 | |
| 1189 | /* Select setting value in bps */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1190 | if (ddr_md == 0) { /* 1584Mbps */ |
| 1191 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x04058900); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1192 | } else { /* 1856Mbps */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1193 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x04058A00); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1194 | } /* ddr_md */ |
| 1195 | |
| 1196 | /* rev0.08 */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1197 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x0000000C); |
| 1198 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x18000040); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1199 | |
| 1200 | /**************************************************************************** |
| 1201 | * recovery_Step2(PHY setting 2) |
| 1202 | ***************************************************************************/ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1203 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006); |
| 1204 | while ((BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1205 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1206 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A7); |
| 1207 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x0D0D0D0D); |
| 1208 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A8); |
| 1209 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x0D0D0D0D); |
| 1210 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A9); |
| 1211 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x000D0D0D); |
| 1212 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C7); |
| 1213 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x0D0D0D0D); |
| 1214 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C8); |
| 1215 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x0D0D0D0D); |
| 1216 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C9); |
| 1217 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x000D0D0D); |
| 1218 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E7); |
| 1219 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x0D0D0D0D); |
| 1220 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E8); |
| 1221 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x0D0D0D0D); |
| 1222 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E9); |
| 1223 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x000D0D0D); |
| 1224 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000107); |
| 1225 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x0D0D0D0D); |
| 1226 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000108); |
| 1227 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x0D0D0D0D); |
| 1228 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000109); |
| 1229 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x000D0D0D); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1230 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1231 | WriteReg_32(DBSC_E3_DBCALCNF, (uint32_t)(64000000 / REFRESH_RATE) + 0x01000000); |
| 1232 | WriteReg_32(DBSC_E3_DBBUS0CNF1, 0x00000010); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1233 | |
| 1234 | /* Select setting value in bps */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1235 | if (ddr_md == 0) { /* 1584Mbps */ |
| 1236 | WriteReg_32(DBSC_E3_DBRFCNF1, (uint32_t)(REFRESH_RATE * 99 / 125) + 0x00080000); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1237 | } else { /* 1856Mbps */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1238 | WriteReg_32(DBSC_E3_DBRFCNF1, (uint32_t)(REFRESH_RATE * 116 / 125) + 0x00080000); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1239 | } /* ddr_md */ |
| 1240 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1241 | WriteReg_32(DBSC_E3_DBRFCNF2, 0x00010000); |
| 1242 | WriteReg_32(DBSC_E3_DBRFEN, 0x00000001); |
| 1243 | WriteReg_32(DBSC_E3_DBCMD, 0x0A840001); |
| 1244 | while ((BIT0 & ReadReg_32(DBSC_E3_DBWAIT)) != 0); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1245 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1246 | WriteReg_32(DBSC_E3_DBCMD, 0x00000000); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1247 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1248 | WriteReg_32(DBSC_E3_DBCMD, 0x04840010); |
| 1249 | while ((BIT0 & ReadReg_32(DBSC_E3_DBWAIT)) != 0); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1250 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1251 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006); /* DDR_PGSR0 */ |
| 1252 | while ((BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1253 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1254 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000001); /* DDR_PIR */ |
| 1255 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x00010701); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1256 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1257 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006); /* DDR_PGSR0 */ |
| 1258 | while ((BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1259 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1260 | for (i = 0; i < 4; i++) |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1261 | { |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1262 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B1 + i * 0x20); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1263 | RegVal_R5 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0x0000FF00) >> 0x8; |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1264 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B4 + i * 0x20); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1265 | RegVal_R6 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0x000000FF); |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1266 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B3 + i * 0x20); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1267 | RegVal_R7 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0x00000007); |
| 1268 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1269 | if (RegVal_R6 > 0) { |
| 1270 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B2 + i * 0x20); |
| 1271 | RegVal_R2 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFFF8); |
| 1272 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B2 + i * 0x20); |
| 1273 | WriteReg_32(DBSC_E3_DBPDRGD0, RegVal_R2 | ((RegVal_R7 + 0x1) & 0x00000007)); |
| 1274 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B0 + i * 0x20); |
| 1275 | RegVal_R2 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFF00); |
| 1276 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B0 + i * 0x20); |
| 1277 | WriteReg_32(DBSC_E3_DBPDRGD0, RegVal_R2 | RegVal_R6); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1278 | } else { |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1279 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B2 + i * 0x20); |
| 1280 | RegVal_R2 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFFF8); |
| 1281 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B2 + i * 0x20); |
| 1282 | WriteReg_32(DBSC_E3_DBPDRGD0, RegVal_R2 | RegVal_R7); |
| 1283 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B0 + i * 0x20); |
| 1284 | RegVal_R2 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFF00); |
| 1285 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B0 + i * 0x20); |
| 1286 | WriteReg_32(DBSC_E3_DBPDRGD0, RegVal_R2 | ((RegVal_R6 + ((RegVal_R5) << 1)) & 0x000000FF)); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1287 | } /* RegVal_R6 */ |
| 1288 | } /* for i */ |
| 1289 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1290 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000005); |
| 1291 | WriteReg_32(DBSC_E3_DBPDRGD0, 0xC1AA00C0); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1292 | |
| 1293 | /* rev.0.08 */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1294 | if (pdqsr_ctl == 1){} else { |
| 1295 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A0); |
| 1296 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5); |
| 1297 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C0); |
| 1298 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5); |
| 1299 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E0); |
| 1300 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5); |
| 1301 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000100); |
| 1302 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5); |
Marek Vasut | 432d767 | 2018-12-12 18:06:39 +0100 | [diff] [blame] | 1303 | } |
| 1304 | |
| 1305 | /* PDR always off */ /* rev.0.10 */ |
| 1306 | if (pdr_ctl == 1) { |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1307 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A3); |
| 1308 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000008); |
| 1309 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C3); |
| 1310 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000008); |
| 1311 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E3); |
| 1312 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000008); |
| 1313 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000103); |
| 1314 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000008); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1315 | } |
| 1316 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1317 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000001); |
| 1318 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x00010801); |
| 1319 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006); |
| 1320 | while ((BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1321 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1322 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000005); |
| 1323 | WriteReg_32(DBSC_E3_DBPDRGD0, 0xC1AA00D8); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1324 | |
| 1325 | /* rev.0.08 */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1326 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000001); |
| 1327 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x00011001); |
| 1328 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006); |
| 1329 | while ((BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1330 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1331 | if (pdqsr_ctl == 1) { |
| 1332 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A0); |
| 1333 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5); |
| 1334 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C0); |
| 1335 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5); |
| 1336 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E0); |
| 1337 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5); |
| 1338 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000100); |
| 1339 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1340 | } |
| 1341 | |
Marek Vasut | 432d767 | 2018-12-12 18:06:39 +0100 | [diff] [blame] | 1342 | /* PDR dynamic */ /* rev.0.10 */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1343 | if (pdr_ctl == 1) { |
| 1344 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A3); |
| 1345 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000000); |
| 1346 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C3); |
| 1347 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000000); |
| 1348 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E3); |
| 1349 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000000); |
| 1350 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000103); |
| 1351 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000000); |
Marek Vasut | 432d767 | 2018-12-12 18:06:39 +0100 | [diff] [blame] | 1352 | } |
| 1353 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1354 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000001); |
| 1355 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x00012001); |
| 1356 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006); |
| 1357 | while ((BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1358 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1359 | if (pdqsr_ctl == 1) { |
| 1360 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A0); |
| 1361 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C000285); |
| 1362 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C0); |
| 1363 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C000285); |
| 1364 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E0); |
| 1365 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C000285); |
| 1366 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000100); |
| 1367 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C000285); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1368 | } |
| 1369 | |
Marek Vasut | 432d767 | 2018-12-12 18:06:39 +0100 | [diff] [blame] | 1370 | /* PDR always off */ /* rev.0.10 */ |
| 1371 | if (pdr_ctl == 1) { |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1372 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A3); |
| 1373 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000008); |
| 1374 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C3); |
| 1375 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000008); |
| 1376 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E3); |
| 1377 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000008); |
| 1378 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000103); |
| 1379 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000008); |
Marek Vasut | 432d767 | 2018-12-12 18:06:39 +0100 | [diff] [blame] | 1380 | } |
| 1381 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1382 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000001); |
| 1383 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x00014001); |
| 1384 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006); |
| 1385 | while ((BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1386 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1387 | if (pdqsr_ctl == 1) { |
| 1388 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A0); |
| 1389 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5); |
| 1390 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C0); |
| 1391 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5); |
| 1392 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E0); |
| 1393 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5); |
| 1394 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000100); |
| 1395 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1396 | } |
| 1397 | |
Marek Vasut | 432d767 | 2018-12-12 18:06:39 +0100 | [diff] [blame] | 1398 | /* PDR dynamic */ /* rev.0.10 */ |
| 1399 | if (pdr_ctl == 1) { |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1400 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A3); |
| 1401 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000000); |
| 1402 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C3); |
| 1403 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000000); |
| 1404 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E3); |
| 1405 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000000); |
| 1406 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000103); |
| 1407 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000000); |
Marek Vasut | 432d767 | 2018-12-12 18:06:39 +0100 | [diff] [blame] | 1408 | } |
| 1409 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1410 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000001); |
| 1411 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x00018001); |
| 1412 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006); |
| 1413 | while ((BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1414 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1415 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A0); |
| 1416 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C000285); |
| 1417 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C0); |
| 1418 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C000285); |
| 1419 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E0); |
| 1420 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C000285); |
| 1421 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000100); |
| 1422 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C000285); |
| 1423 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x0000002C); |
| 1424 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x81003087); |
| 1425 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000001); |
| 1426 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x00010401); |
| 1427 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006); |
| 1428 | while ((BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1429 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1430 | for (i = 0; i < 4; i++) { |
| 1431 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B1 + i * 0x20); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1432 | RegVal_R5 = ((ReadReg_32(DBSC_E3_DBPDRGD0) & 0x0000FF00) >> 0x8); |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1433 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B4 + i * 0x20); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1434 | RegVal_R6 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0x000000FF); |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1435 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B3 + i * 0x20); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1436 | RegVal_R7 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0x00000007); |
| 1437 | RegVal_R12 = (RegVal_R5 >> 0x2); |
| 1438 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1439 | if (RegVal_R12 < RegVal_R6) { |
| 1440 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B2 + i * 0x20); |
| 1441 | RegVal_R2 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFFF8); |
| 1442 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B2 + i * 0x20); |
| 1443 | WriteReg_32(DBSC_E3_DBPDRGD0, RegVal_R2 | ((RegVal_R7 + 0x1) & 0x00000007)); |
| 1444 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B0 + i * 0x20); |
| 1445 | RegVal_R2 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFF00); |
| 1446 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B0 + i * 0x20); |
| 1447 | WriteReg_32(DBSC_E3_DBPDRGD0, RegVal_R2 | ((RegVal_R6 - (RegVal_R12)) & 0x000000FF)); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1448 | } else { |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1449 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B2 + i * 0x20); |
| 1450 | RegVal_R2 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFFF8); |
| 1451 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B2 + i * 0x20); |
| 1452 | WriteReg_32(DBSC_E3_DBPDRGD0, RegVal_R2 | (RegVal_R7 & 0x00000007)); |
| 1453 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B0 + i * 0x20); |
| 1454 | RegVal_R2 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFF00); |
| 1455 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B0 + i * 0x20); |
| 1456 | WriteReg_32(DBSC_E3_DBPDRGD0, RegVal_R2 | ((RegVal_R6 + (RegVal_R5) + ((RegVal_R5) >> 1) + (RegVal_R12)) & 0x000000FF)); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1457 | } /* RegVal_R12 < RegVal_R6 */ |
| 1458 | } /* for i */ |
| 1459 | |
| 1460 | /* rev.0.08 */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1461 | if (pdqsr_ctl == 1){} else { |
| 1462 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A0); |
| 1463 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5); |
| 1464 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C0); |
| 1465 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5); |
| 1466 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E0); |
| 1467 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5); |
| 1468 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000100); |
| 1469 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1470 | } |
| 1471 | |
Marek Vasut | 432d767 | 2018-12-12 18:06:39 +0100 | [diff] [blame] | 1472 | /* PDR always off */ /* rev.0.10 */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1473 | if (pdr_ctl == 1) { |
| 1474 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A3); |
| 1475 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000008); |
| 1476 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C3); |
| 1477 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000008); |
| 1478 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E3); |
| 1479 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000008); |
| 1480 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000103); |
| 1481 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000008); |
Marek Vasut | 432d767 | 2018-12-12 18:06:39 +0100 | [diff] [blame] | 1482 | } |
| 1483 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1484 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000001); |
| 1485 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x00015001); |
| 1486 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006); |
| 1487 | while ((BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1488 | |
| 1489 | /* rev.0.08 */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1490 | if (lcdl_ctl == 1) { |
| 1491 | for (i = 0; i < 4; i++) { |
| 1492 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B0 + i * 0x20); |
| 1493 | dqsgd_0c = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0x000000FF); |
| 1494 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B1 + i * 0x20); |
| 1495 | bdlcount_0c = ((ReadReg_32(DBSC_E3_DBPDRGD0) & 0x0000FF00) >> 8); |
| 1496 | bdlcount_0c_div2 = (bdlcount_0c >> 1); |
| 1497 | bdlcount_0c_div4 = (bdlcount_0c >> 2); |
| 1498 | bdlcount_0c_div8 = (bdlcount_0c >> 3); |
| 1499 | bdlcount_0c_div16 = (bdlcount_0c >> 4); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1500 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1501 | if (ddr_md == 0) { /* 1584Mbps */ |
| 1502 | lcdl_judge1 = bdlcount_0c_div2 + bdlcount_0c_div4 + bdlcount_0c_div8; |
| 1503 | lcdl_judge2 = bdlcount_0c + bdlcount_0c_div4 + bdlcount_0c_div16; |
| 1504 | } else { /* 1856Mbps */ |
| 1505 | lcdl_judge1 = bdlcount_0c_div2 + bdlcount_0c_div4; |
| 1506 | lcdl_judge2 = bdlcount_0c + bdlcount_0c_div4; |
| 1507 | } /* ddr_md */ |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1508 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1509 | if (dqsgd_0c > lcdl_judge1) { |
| 1510 | if (dqsgd_0c <= lcdl_judge2) { |
| 1511 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B0 + i * 0x20); |
| 1512 | RegVal = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFF00); |
| 1513 | WriteReg_32(DBSC_E3_DBPDRGD0, ((dqsgd_0c - bdlcount_0c_div8) | RegVal)); |
| 1514 | } else { |
| 1515 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B0 + i * 0x20); |
| 1516 | RegVal = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFF00); |
| 1517 | WriteReg_32(DBSC_E3_DBPDRGD0, RegVal); |
| 1518 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B2 + i * 0x20); |
| 1519 | gatesl_0c = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0x00000007); |
| 1520 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B2 + i * 0x20); |
| 1521 | RegVal = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFFF8); |
| 1522 | WriteReg_32(DBSC_E3_DBPDRGD0, (RegVal | (gatesl_0c + 1))); |
| 1523 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000AF + i * 0x20); |
| 1524 | RegVal = (ReadReg_32(DBSC_E3_DBPDRGD0)); |
| 1525 | rdqsd_0c = (RegVal & 0x0000FF00) >> 8; |
| 1526 | rdqsnd_0c = (RegVal & 0x00FF0000) >> 16; |
| 1527 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000AF + i * 0x20); |
| 1528 | WriteReg_32(DBSC_E3_DBPDRGD0, ((RegVal & 0xFF0000FF) | ((rdqsd_0c + bdlcount_0c_div4) << 8) | ((rdqsnd_0c + bdlcount_0c_div4) << 16))); |
| 1529 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000AA + i * 0x20); |
| 1530 | RegVal = (ReadReg_32(DBSC_E3_DBPDRGD0)); |
| 1531 | rbd_0c[0] = (RegVal) &0x0000001f; |
| 1532 | rbd_0c[1] = (RegVal >> 8) & 0x0000001f; |
| 1533 | rbd_0c[2] = (RegVal >> 16) & 0x0000001f; |
| 1534 | rbd_0c[3] = (RegVal >> 24) & 0x0000001f; |
| 1535 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000AA + i * 0x20); |
| 1536 | RegVal = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xE0E0E0E0); |
| 1537 | for (j = 0; j < 4; j++) { |
| 1538 | rbd_0c[j] = (rbd_0c[j] + bdlcount_0c_div4); |
| 1539 | if (rbd_0c[j] > 0x1F) rbd_0c[j] = 0x1F; |
| 1540 | RegVal = RegVal | (rbd_0c[j] << 8 * j); |
| 1541 | } |
| 1542 | WriteReg_32(DBSC_E3_DBPDRGD0, RegVal); |
| 1543 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000AB + i * 0x20); |
| 1544 | RegVal = (ReadReg_32(DBSC_E3_DBPDRGD0)); |
| 1545 | rbd_0c[0] = (RegVal) &0x0000001f; |
| 1546 | rbd_0c[1] = (RegVal >> 8) & 0x0000001f; |
| 1547 | rbd_0c[2] = (RegVal >> 16) & 0x0000001f; |
| 1548 | rbd_0c[3] = (RegVal >> 24) & 0x0000001f; |
| 1549 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000AB + i * 0x20); |
| 1550 | RegVal = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xE0E0E0E0); |
| 1551 | for (j = 0; j < 4; j++) { |
| 1552 | rbd_0c[j] = (rbd_0c[j] + bdlcount_0c_div4); |
| 1553 | if (rbd_0c[j] > 0x1F) rbd_0c[j] = 0x1F; |
| 1554 | RegVal = RegVal | (rbd_0c[j] << 8 * j); |
| 1555 | } |
| 1556 | WriteReg_32(DBSC_E3_DBPDRGD0, RegVal); |
| 1557 | } |
| 1558 | } |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1559 | } |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1560 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000002); |
| 1561 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x07D81E37); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1562 | } |
| 1563 | |
| 1564 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1565 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000003); |
| 1566 | if (byp_ctl == 1) { |
| 1567 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x0380C720); |
Marek Vasut | 432d767 | 2018-12-12 18:06:39 +0100 | [diff] [blame] | 1568 | } else { |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1569 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x0380C700); |
Marek Vasut | 432d767 | 2018-12-12 18:06:39 +0100 | [diff] [blame] | 1570 | } |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1571 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000007); |
| 1572 | while ((BIT30 & ReadReg_32(DBSC_E3_DBPDRGD0)) != 0); |
| 1573 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000021); |
| 1574 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x0024643E); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1575 | |
| 1576 | /**************************************************************************** |
| 1577 | * recovery_Step3(DBSC Setting 2) |
| 1578 | ***************************************************************************/ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1579 | WriteReg_32(DBSC_E3_DBDFICUPDCNF, 0x40100001); |
| 1580 | WriteReg_32(DBSC_E3_DBACEN, 0x00000001); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1581 | |
| 1582 | /* rev.0.08 */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1583 | if (pdqsr_ctl == 1) { |
| 1584 | WriteReg_32(0xE67F0018, 0x00000001); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1585 | RegVal = ReadReg_32(0x40000000); |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1586 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000000); |
| 1587 | WriteReg_32(DBSC_E3_DBPDRGD0, RegVal); |
| 1588 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A0); |
| 1589 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5); |
| 1590 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C0); |
| 1591 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5); |
| 1592 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E0); |
| 1593 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5); |
| 1594 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000100); |
| 1595 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5); |
Marek Vasut | 432d767 | 2018-12-12 18:06:39 +0100 | [diff] [blame] | 1596 | } |
| 1597 | |
| 1598 | /* PDR dynamic */ /* rev.0.10 */ |
| 1599 | if (pdr_ctl == 1) { |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1600 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A3); |
| 1601 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000000); |
| 1602 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C3); |
| 1603 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000000); |
| 1604 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E3); |
| 1605 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000000); |
| 1606 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000103); |
| 1607 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000000); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1608 | } |
| 1609 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1610 | WriteReg_32(DBSC_E3_DBPDLK0, 0x00000000); |
| 1611 | WriteReg_32(DBSC_E3_DBSYSCNT0, 0x00000000); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1612 | |
| 1613 | #ifdef ddr_qos_init_setting /* only for non qos_init */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1614 | WriteReg_32(DBSC_E3_DBSYSCNT0, 0x00001234); |
| 1615 | WriteReg_32(DBSC_E3_DBCAM0CNF1, 0x00043218); |
| 1616 | WriteReg_32(DBSC_E3_DBCAM0CNF2, 0x000000F4); |
| 1617 | WriteReg_32(DBSC_E3_DBSCHCNT0, 0x000f0037); |
| 1618 | WriteReg_32(DBSC_E3_DBSCHSZ0, 0x00000001); |
| 1619 | WriteReg_32(DBSC_E3_DBSCHRW0, 0x22421111); |
| 1620 | WriteReg_32(DBSC_E3_SCFCTST2, 0x012F1123); |
| 1621 | WriteReg_32(DBSC_E3_DBSCHQOS00, 0x00000F00); |
| 1622 | WriteReg_32(DBSC_E3_DBSCHQOS01, 0x00000B00); |
| 1623 | WriteReg_32(DBSC_E3_DBSCHQOS02, 0x00000000); |
| 1624 | WriteReg_32(DBSC_E3_DBSCHQOS03, 0x00000000); |
| 1625 | WriteReg_32(DBSC_E3_DBSCHQOS40, 0x00000300); |
| 1626 | WriteReg_32(DBSC_E3_DBSCHQOS41, 0x000002F0); |
| 1627 | WriteReg_32(DBSC_E3_DBSCHQOS42, 0x00000200); |
| 1628 | WriteReg_32(DBSC_E3_DBSCHQOS43, 0x00000100); |
| 1629 | WriteReg_32(DBSC_E3_DBSCHQOS90, 0x00000100); |
| 1630 | WriteReg_32(DBSC_E3_DBSCHQOS91, 0x000000F0); |
| 1631 | WriteReg_32(DBSC_E3_DBSCHQOS92, 0x000000A0); |
| 1632 | WriteReg_32(DBSC_E3_DBSCHQOS93, 0x00000040); |
| 1633 | WriteReg_32(DBSC_E3_DBSCHQOS130, 0x00000100); |
| 1634 | WriteReg_32(DBSC_E3_DBSCHQOS131, 0x000000F0); |
| 1635 | WriteReg_32(DBSC_E3_DBSCHQOS132, 0x000000A0); |
| 1636 | WriteReg_32(DBSC_E3_DBSCHQOS133, 0x00000040); |
| 1637 | WriteReg_32(DBSC_E3_DBSCHQOS140, 0x000000C0); |
| 1638 | WriteReg_32(DBSC_E3_DBSCHQOS141, 0x000000B0); |
| 1639 | WriteReg_32(DBSC_E3_DBSCHQOS142, 0x00000080); |
| 1640 | WriteReg_32(DBSC_E3_DBSCHQOS143, 0x00000040); |
| 1641 | WriteReg_32(DBSC_E3_DBSCHQOS150, 0x00000040); |
| 1642 | WriteReg_32(DBSC_E3_DBSCHQOS151, 0x00000030); |
| 1643 | WriteReg_32(DBSC_E3_DBSCHQOS152, 0x00000020); |
| 1644 | WriteReg_32(DBSC_E3_DBSCHQOS153, 0x00000010); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1645 | |
| 1646 | /* rev.0.08 */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1647 | if (pdqsr_ctl == 1){} else { |
| 1648 | WriteReg_32(0xE67F0018, 0x00000001); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1649 | } |
| 1650 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1651 | WriteReg_32(DBSC_E3_DBSYSCNT0, 0x00000000); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1652 | #endif |
| 1653 | |
| 1654 | return 1; |
| 1655 | |
| 1656 | } /* recovery_from_backup_mode */ |
| 1657 | |
| 1658 | /******************************************************************************* |
| 1659 | * init_ddr : MD19=0,DDR3L,1584Mbps / MD19=1,DDR3L,1856Mbps |
| 1660 | ******************************************************************************/ |
| 1661 | |
| 1662 | /******************************************************************************* |
| 1663 | * DDR Initialize entry for IPL |
| 1664 | ******************************************************************************/ |
ldts | 0a596b4 | 2018-11-06 10:17:12 +0100 | [diff] [blame] | 1665 | int32_t rcar_dram_init(void) |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1666 | { |
| 1667 | uint32_t dataL; |
| 1668 | uint32_t failcount; |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1669 | uint32_t md = 0; |
| 1670 | uint32_t ddr = 0; |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1671 | |
| 1672 | md = *((volatile uint32_t*)RST_MODEMR); |
| 1673 | ddr = (md & 0x00080000) >> 19; |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1674 | if (ddr == 0x0) { |
Marek Vasut | 5651989 | 2019-01-21 23:11:33 +0100 | [diff] [blame] | 1675 | NOTICE("BL2: DDR1584(%s)\n", RCAR_E3_DDR_VERSION); |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1676 | } else if(ddr == 0x1){ |
Marek Vasut | 5651989 | 2019-01-21 23:11:33 +0100 | [diff] [blame] | 1677 | NOTICE("BL2: DDR1856(%s)\n", RCAR_E3_DDR_VERSION); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1678 | } /* ddr */ |
| 1679 | |
ldts | 0a596b4 | 2018-11-06 10:17:12 +0100 | [diff] [blame] | 1680 | rcar_dram_get_boot_status(&ddrBackup); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1681 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1682 | if (ddrBackup == DRAM_BOOT_STATUS_WARM) { |
| 1683 | dataL = recovery_from_backup_mode(); /* WARM boot */ |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1684 | } else { |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1685 | dataL = init_ddr(); /* COLD boot */ |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1686 | } /* ddrBackup */ |
| 1687 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1688 | if (dataL == 1) { |
| 1689 | failcount = 0; |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1690 | } else { |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1691 | failcount = 1; |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1692 | } /* dataL */ |
| 1693 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1694 | if (failcount == 0) { |
| 1695 | return INITDRAM_OK; |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1696 | } else { |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1697 | return INITDRAM_NG; |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1698 | } /* failcount */ |
| 1699 | } /* InitDram */ |
| 1700 | |
| 1701 | /******************************************************************************* |
| 1702 | * END |
| 1703 | ******************************************************************************/ |