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Achin Gupta4f6ad662013-10-25 09:08:21 +01001/*
Antonio Nino Diaz5a42b682018-07-18 11:57:21 +01002 * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +01003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Achin Gupta4f6ad662013-10-25 09:08:21 +01005 */
6
Antonio Nino Diaz5a42b682018-07-18 11:57:21 +01007#ifndef PSCI_H
8#define PSCI_H
Achin Gupta4f6ad662013-10-25 09:08:21 +01009
Soby Mathew523d6332015-01-08 18:02:19 +000010#include <bakery_lock.h>
Soby Mathew89256b82016-09-13 14:19:08 +010011#include <bl_common.h>
Soby Mathew981487a2015-07-13 14:10:57 +010012#include <platform_def.h> /* for PLAT_NUM_PWR_DOMAINS */
Soby Mathewb911cc72017-02-13 12:46:28 +000013#include <psci_lib.h> /* To maintain compatibility for SPDs */
Varun Wadekarc6a11f62017-05-25 18:04:48 -070014#include <utils_def.h>
Dan Handley2bd4ef22014-04-09 13:14:54 +010015
Achin Gupta4f6ad662013-10-25 09:08:21 +010016/*******************************************************************************
Sandrine Bailleuxf4119ec2015-12-17 13:58:58 +000017 * Number of power domains whose state this PSCI implementation can track
Soby Mathew523d6332015-01-08 18:02:19 +000018 ******************************************************************************/
Soby Mathew981487a2015-07-13 14:10:57 +010019#ifdef PLAT_NUM_PWR_DOMAINS
20#define PSCI_NUM_PWR_DOMAINS PLAT_NUM_PWR_DOMAINS
Soby Mathew523d6332015-01-08 18:02:19 +000021#else
Antonio Nino Diaz6f3ccc52018-07-20 09:17:26 +010022#define PSCI_NUM_PWR_DOMAINS (2 * PLATFORM_CORE_COUNT)
Soby Mathew523d6332015-01-08 18:02:19 +000023#endif
24
Soby Mathew981487a2015-07-13 14:10:57 +010025#define PSCI_NUM_NON_CPU_PWR_DOMAINS (PSCI_NUM_PWR_DOMAINS - \
26 PLATFORM_CORE_COUNT)
27
28/* This is the power level corresponding to a CPU */
Antonio Nino Diaz6f3ccc52018-07-20 09:17:26 +010029#define PSCI_CPU_PWR_LVL U(0)
Soby Mathew981487a2015-07-13 14:10:57 +010030
31/*
32 * The maximum power level supported by PSCI. Since PSCI CPU_SUSPEND
33 * uses the old power_state parameter format which has 2 bits to specify the
34 * power level, this constant is defined to be 3.
35 */
Varun Wadekarc6a11f62017-05-25 18:04:48 -070036#define PSCI_MAX_PWR_LVL U(3)
Soby Mathew981487a2015-07-13 14:10:57 +010037
Soby Mathew523d6332015-01-08 18:02:19 +000038/*******************************************************************************
Sandrine Bailleuxf4119ec2015-12-17 13:58:58 +000039 * Defines for runtime services function ids
Achin Gupta4f6ad662013-10-25 09:08:21 +010040 ******************************************************************************/
Varun Wadekarc6a11f62017-05-25 18:04:48 -070041#define PSCI_VERSION U(0x84000000)
42#define PSCI_CPU_SUSPEND_AARCH32 U(0x84000001)
43#define PSCI_CPU_SUSPEND_AARCH64 U(0xc4000001)
44#define PSCI_CPU_OFF U(0x84000002)
45#define PSCI_CPU_ON_AARCH32 U(0x84000003)
46#define PSCI_CPU_ON_AARCH64 U(0xc4000003)
47#define PSCI_AFFINITY_INFO_AARCH32 U(0x84000004)
48#define PSCI_AFFINITY_INFO_AARCH64 U(0xc4000004)
49#define PSCI_MIG_AARCH32 U(0x84000005)
50#define PSCI_MIG_AARCH64 U(0xc4000005)
51#define PSCI_MIG_INFO_TYPE U(0x84000006)
52#define PSCI_MIG_INFO_UP_CPU_AARCH32 U(0x84000007)
53#define PSCI_MIG_INFO_UP_CPU_AARCH64 U(0xc4000007)
54#define PSCI_SYSTEM_OFF U(0x84000008)
55#define PSCI_SYSTEM_RESET U(0x84000009)
56#define PSCI_FEATURES U(0x8400000A)
57#define PSCI_NODE_HW_STATE_AARCH32 U(0x8400000d)
58#define PSCI_NODE_HW_STATE_AARCH64 U(0xc400000d)
59#define PSCI_SYSTEM_SUSPEND_AARCH32 U(0x8400000E)
60#define PSCI_SYSTEM_SUSPEND_AARCH64 U(0xc400000E)
61#define PSCI_STAT_RESIDENCY_AARCH32 U(0x84000010)
62#define PSCI_STAT_RESIDENCY_AARCH64 U(0xc4000010)
63#define PSCI_STAT_COUNT_AARCH32 U(0x84000011)
64#define PSCI_STAT_COUNT_AARCH64 U(0xc4000011)
Roberto Vargasb820ad02017-07-26 09:23:09 +010065#define PSCI_SYSTEM_RESET2_AARCH32 U(0x84000012)
66#define PSCI_SYSTEM_RESET2_AARCH64 U(0xc4000012)
Roberto Vargas0a4c2612017-08-03 08:16:16 +010067#define PSCI_MEM_PROTECT U(0x84000013)
68#define PSCI_MEM_CHK_RANGE_AARCH32 U(0x84000014)
69#define PSCI_MEM_CHK_RANGE_AARCH64 U(0xc4000014)
Soby Mathew6cdddaf2015-01-07 11:10:22 +000070
Jeenu Viswambharan1814a3e2014-02-28 10:08:33 +000071/*
Juan Castillo4dc4a472014-08-12 11:17:06 +010072 * Number of PSCI calls (above) implemented
Jeenu Viswambharan1814a3e2014-02-28 10:08:33 +000073 */
Yatharth Kochar241ec6c2016-05-09 18:26:35 +010074#if ENABLE_PSCI_STAT
Varun Wadekarc6a11f62017-05-25 18:04:48 -070075#define PSCI_NUM_CALLS U(22)
Yatharth Kochar241ec6c2016-05-09 18:26:35 +010076#else
Varun Wadekarc6a11f62017-05-25 18:04:48 -070077#define PSCI_NUM_CALLS U(18)
Yatharth Kochar241ec6c2016-05-09 18:26:35 +010078#endif
Jeenu Viswambharan1814a3e2014-02-28 10:08:33 +000079
Soby Mathewd0194872016-04-29 19:01:30 +010080/* The macros below are used to identify PSCI calls from the SMC function ID */
Varun Wadekarc6a11f62017-05-25 18:04:48 -070081#define PSCI_FID_MASK U(0xffe0)
82#define PSCI_FID_VALUE U(0)
Soby Mathewd0194872016-04-29 19:01:30 +010083#define is_psci_fid(_fid) \
84 (((_fid) & PSCI_FID_MASK) == PSCI_FID_VALUE)
85
Achin Gupta4f6ad662013-10-25 09:08:21 +010086/*******************************************************************************
87 * PSCI Migrate and friends
88 ******************************************************************************/
Antonio Nino Diaz6f3ccc52018-07-20 09:17:26 +010089#define PSCI_TOS_UP_MIG_CAP 0
90#define PSCI_TOS_NOT_UP_MIG_CAP 1
91#define PSCI_TOS_NOT_PRESENT_MP 2
Achin Gupta4f6ad662013-10-25 09:08:21 +010092
93/*******************************************************************************
94 * PSCI CPU_SUSPEND 'power_state' parameter specific defines
95 ******************************************************************************/
Varun Wadekarc6a11f62017-05-25 18:04:48 -070096#define PSTATE_ID_SHIFT U(0)
Achin Gupta4f6ad662013-10-25 09:08:21 +010097
Soby Mathew981487a2015-07-13 14:10:57 +010098#if PSCI_EXTENDED_STATE_ID
Varun Wadekarc6a11f62017-05-25 18:04:48 -070099#define PSTATE_VALID_MASK U(0xB0000000)
100#define PSTATE_TYPE_SHIFT U(30)
101#define PSTATE_ID_MASK U(0xfffffff)
Soby Mathew981487a2015-07-13 14:10:57 +0100102#else
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700103#define PSTATE_VALID_MASK U(0xFCFE0000)
104#define PSTATE_TYPE_SHIFT U(16)
105#define PSTATE_PWR_LVL_SHIFT U(24)
106#define PSTATE_ID_MASK U(0xffff)
107#define PSTATE_PWR_LVL_MASK U(0x3)
Soby Mathew981487a2015-07-13 14:10:57 +0100108
109#define psci_get_pstate_pwrlvl(pstate) (((pstate) >> PSTATE_PWR_LVL_SHIFT) & \
110 PSTATE_PWR_LVL_MASK)
111#define psci_make_powerstate(state_id, type, pwrlvl) \
112 (((state_id) & PSTATE_ID_MASK) << PSTATE_ID_SHIFT) |\
113 (((type) & PSTATE_TYPE_MASK) << PSTATE_TYPE_SHIFT) |\
114 (((pwrlvl) & PSTATE_PWR_LVL_MASK) << PSTATE_PWR_LVL_SHIFT)
115#endif /* __PSCI_EXTENDED_STATE_ID__ */
Achin Gupta4f6ad662013-10-25 09:08:21 +0100116
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700117#define PSTATE_TYPE_STANDBY U(0x0)
118#define PSTATE_TYPE_POWERDOWN U(0x1)
119#define PSTATE_TYPE_MASK U(0x1)
Vikram Kanigiri3b7c59b2014-03-21 11:57:10 +0000120
Achin Gupta4f6ad662013-10-25 09:08:21 +0100121/*******************************************************************************
Soby Mathew6cdddaf2015-01-07 11:10:22 +0000122 * PSCI CPU_FEATURES feature flag specific defines
123 ******************************************************************************/
124/* Features flags for CPU SUSPEND power state parameter format. Bits [1:1] */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700125#define FF_PSTATE_SHIFT U(1)
126#define FF_PSTATE_ORIG U(0)
127#define FF_PSTATE_EXTENDED U(1)
Soby Mathew981487a2015-07-13 14:10:57 +0100128#if PSCI_EXTENDED_STATE_ID
129#define FF_PSTATE FF_PSTATE_EXTENDED
130#else
131#define FF_PSTATE FF_PSTATE_ORIG
132#endif
Soby Mathew6cdddaf2015-01-07 11:10:22 +0000133
134/* Features flags for CPU SUSPEND OS Initiated mode support. Bits [0:0] */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700135#define FF_MODE_SUPPORT_SHIFT U(0)
136#define FF_SUPPORTS_OS_INIT_MODE U(1)
Soby Mathew6cdddaf2015-01-07 11:10:22 +0000137
138/*******************************************************************************
Achin Gupta4f6ad662013-10-25 09:08:21 +0100139 * PSCI version
140 ******************************************************************************/
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700141#define PSCI_MAJOR_VER (U(1) << 16)
Roberto Vargasffb34d02017-09-11 09:11:58 +0100142#define PSCI_MINOR_VER U(0x1)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100143
144/*******************************************************************************
145 * PSCI error codes
146 ******************************************************************************/
147#define PSCI_E_SUCCESS 0
148#define PSCI_E_NOT_SUPPORTED -1
149#define PSCI_E_INVALID_PARAMS -2
150#define PSCI_E_DENIED -3
151#define PSCI_E_ALREADY_ON -4
152#define PSCI_E_ON_PENDING -5
153#define PSCI_E_INTERN_FAIL -6
154#define PSCI_E_NOT_PRESENT -7
155#define PSCI_E_DISABLED -8
Soby Mathewf1f97a12015-07-15 12:13:26 +0100156#define PSCI_E_INVALID_ADDRESS -9
Achin Gupta4f6ad662013-10-25 09:08:21 +0100157
Soby Mathew011ca182015-07-29 17:05:03 +0100158#define PSCI_INVALID_MPIDR ~((u_register_t)0)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100159
Roberto Vargasb820ad02017-07-26 09:23:09 +0100160/*
161 * SYSTEM_RESET2 macros
162 */
Antonio Nino Diaz6f3ccc52018-07-20 09:17:26 +0100163#define PSCI_RESET2_TYPE_VENDOR_SHIFT U(31)
164#define PSCI_RESET2_TYPE_VENDOR (U(1) << PSCI_RESET2_TYPE_VENDOR_SHIFT)
165#define PSCI_RESET2_TYPE_ARCH (U(0) << PSCI_RESET2_TYPE_VENDOR_SHIFT)
166#define PSCI_RESET2_SYSTEM_WARM_RESET (PSCI_RESET2_TYPE_ARCH | U(0))
Roberto Vargasb820ad02017-07-26 09:23:09 +0100167
Soby Mathew981487a2015-07-13 14:10:57 +0100168#ifndef __ASSEMBLY__
Achin Gupta4f6ad662013-10-25 09:08:21 +0100169
Soby Mathew981487a2015-07-13 14:10:57 +0100170#include <stdint.h>
Soby Mathew981487a2015-07-13 14:10:57 +0100171
Antonio Nino Diaz5a42b682018-07-18 11:57:21 +0100172/* Function to help build the psci capabilities bitfield */
173
174static inline unsigned int define_psci_cap(unsigned int x)
175{
176 return U(1) << (x & U(0x1f));
177}
178
179
180/* Power state helper functions */
181
182static inline unsigned int psci_get_pstate_id(unsigned int power_state)
183{
184 return ((power_state) >> PSTATE_ID_SHIFT) & PSTATE_ID_MASK;
185}
186
187static inline unsigned int psci_get_pstate_type(unsigned int power_state)
188{
189 return ((power_state) >> PSTATE_TYPE_SHIFT) & PSTATE_TYPE_MASK;
190}
191
192static inline unsigned int psci_check_power_state(unsigned int power_state)
193{
194 return ((power_state) & PSTATE_VALID_MASK);
195}
196
Soby Mathew981487a2015-07-13 14:10:57 +0100197/*
198 * These are the states reported by the PSCI_AFFINITY_INFO API for the specified
199 * CPU. The definitions of these states can be found in Section 5.7.1 in the
200 * PSCI specification (ARM DEN 0022C).
201 */
202typedef enum {
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700203 AFF_STATE_ON = U(0),
204 AFF_STATE_OFF = U(1),
205 AFF_STATE_ON_PENDING = U(2)
Soby Mathew981487a2015-07-13 14:10:57 +0100206} aff_info_state_t;
207
208/*
Jeenu Viswambharan7f03e9d92016-08-03 15:54:50 +0100209 * These are the power states reported by PSCI_NODE_HW_STATE API for the
210 * specified CPU. The definitions of these states can be found in Section 5.15.3
211 * of PSCI specification (ARM DEN 0022C).
212 */
Antonio Nino Diaz6f3ccc52018-07-20 09:17:26 +0100213#define HW_ON 0
214#define HW_OFF 1
215#define HW_STANDBY 2
Jeenu Viswambharan7f03e9d92016-08-03 15:54:50 +0100216
217/*
Soby Mathew981487a2015-07-13 14:10:57 +0100218 * Macro to represent invalid affinity level within PSCI.
219 */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700220#define PSCI_INVALID_PWR_LVL (PLAT_MAX_PWR_LVL + U(1))
Vikram Kanigirif100f412014-04-01 19:26:26 +0100221
Soby Mathew981487a2015-07-13 14:10:57 +0100222/*
223 * Type for representing the local power state at a particular level.
224 */
225typedef uint8_t plat_local_state_t;
226
227/* The local state macro used to represent RUN state. */
Antonio Nino Diaz6f3ccc52018-07-20 09:17:26 +0100228#define PSCI_LOCAL_STATE_RUN U(0)
Achin Gupta75f73672013-12-05 16:33:10 +0000229
Soby Mathew981487a2015-07-13 14:10:57 +0100230/*
Antonio Nino Diaz5a42b682018-07-18 11:57:21 +0100231 * Function to test whether the plat_local_state is RUN state
Soby Mathew981487a2015-07-13 14:10:57 +0100232 */
Antonio Nino Diaz5a42b682018-07-18 11:57:21 +0100233static inline int is_local_state_run(unsigned int plat_local_state)
234{
235 return (plat_local_state == PSCI_LOCAL_STATE_RUN) ? 1 : 0;
236}
Vikram Kanigirif100f412014-04-01 19:26:26 +0100237
Soby Mathew981487a2015-07-13 14:10:57 +0100238/*
Antonio Nino Diaz5a42b682018-07-18 11:57:21 +0100239 * Function to test whether the plat_local_state is RETENTION state
Soby Mathew981487a2015-07-13 14:10:57 +0100240 */
Antonio Nino Diaz5a42b682018-07-18 11:57:21 +0100241static inline int is_local_state_retn(unsigned int plat_local_state)
242{
243 return ((plat_local_state > PSCI_LOCAL_STATE_RUN) &&
244 (plat_local_state <= PLAT_MAX_RET_STATE)) ? 1 : 0;
245}
Vikram Kanigirif100f412014-04-01 19:26:26 +0100246
Soby Mathew981487a2015-07-13 14:10:57 +0100247/*
Antonio Nino Diaz5a42b682018-07-18 11:57:21 +0100248 * Function to test whether the plat_local_state is OFF state
Soby Mathew981487a2015-07-13 14:10:57 +0100249 */
Antonio Nino Diaz5a42b682018-07-18 11:57:21 +0100250static inline int is_local_state_off(unsigned int plat_local_state)
251{
252 return ((plat_local_state > PLAT_MAX_RET_STATE) &&
253 (plat_local_state <= PLAT_MAX_OFF_STATE)) ? 1 : 0;
254}
Dan Handley2bd4ef22014-04-09 13:14:54 +0100255
Soby Mathew981487a2015-07-13 14:10:57 +0100256/*****************************************************************************
257 * This data structure defines the representation of the power state parameter
258 * for its exchange between the generic PSCI code and the platform port. For
259 * example, it is used by the platform port to specify the requested power
260 * states during a power management operation. It is used by the generic code to
261 * inform the platform about the target power states that each level should
262 * enter.
263 ****************************************************************************/
264typedef struct psci_power_state {
265 /*
266 * The pwr_domain_state[] stores the local power state at each level
267 * for the CPU.
268 */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700269 plat_local_state_t pwr_domain_state[PLAT_MAX_PWR_LVL + U(1)];
Soby Mathew981487a2015-07-13 14:10:57 +0100270} psci_power_state_t;
Dan Handley2bd4ef22014-04-09 13:14:54 +0100271
Achin Guptaf3ccbab2014-07-25 14:52:47 +0100272/*******************************************************************************
273 * Structure used to store per-cpu information relevant to the PSCI service.
274 * It is populated in the per-cpu data array. In return we get a guarantee that
275 * this information will not reside on a cache line shared with another cpu.
276 ******************************************************************************/
277typedef struct psci_cpu_data {
Soby Mathew981487a2015-07-13 14:10:57 +0100278 /* State as seen by PSCI Affinity Info API */
279 aff_info_state_t aff_info_state;
Soby Mathew011ca182015-07-29 17:05:03 +0100280
Soby Mathew981487a2015-07-13 14:10:57 +0100281 /*
282 * Highest power level which takes part in a power management
283 * operation.
284 */
Antonio Nino Diaz6f3ccc52018-07-20 09:17:26 +0100285 unsigned int target_pwrlvl;
Soby Mathew011ca182015-07-29 17:05:03 +0100286
Soby Mathew981487a2015-07-13 14:10:57 +0100287 /* The local power state of this CPU */
288 plat_local_state_t local_state;
Achin Guptaf3ccbab2014-07-25 14:52:47 +0100289} psci_cpu_data_t;
Dan Handley2bd4ef22014-04-09 13:14:54 +0100290
Achin Gupta4f6ad662013-10-25 09:08:21 +0100291/*******************************************************************************
292 * Structure populated by platform specific code to export routines which
Sandrine Bailleuxf4119ec2015-12-17 13:58:58 +0000293 * perform common low level power management functions
Achin Gupta4f6ad662013-10-25 09:08:21 +0100294 ******************************************************************************/
Soby Mathew981487a2015-07-13 14:10:57 +0100295typedef struct plat_psci_ops {
296 void (*cpu_standby)(plat_local_state_t cpu_state);
297 int (*pwr_domain_on)(u_register_t mpidr);
298 void (*pwr_domain_off)(const psci_power_state_t *target_state);
Varun Wadekarae87f4b2017-07-10 16:02:05 -0700299 void (*pwr_domain_suspend_pwrdown_early)(
300 const psci_power_state_t *target_state);
Soby Mathew981487a2015-07-13 14:10:57 +0100301 void (*pwr_domain_suspend)(const psci_power_state_t *target_state);
302 void (*pwr_domain_on_finish)(const psci_power_state_t *target_state);
303 void (*pwr_domain_suspend_finish)(
304 const psci_power_state_t *target_state);
Yann Gautierbcf8ba22018-11-09 18:21:51 +0100305 void __dead2 (*pwr_domain_pwr_down_wfi)(
306 const psci_power_state_t *target_state);
307 void __dead2 (*system_off)(void);
308 void __dead2 (*system_reset)(void);
Soby Mathew981487a2015-07-13 14:10:57 +0100309 int (*validate_power_state)(unsigned int power_state,
310 psci_power_state_t *req_state);
Soby Mathew011ca182015-07-29 17:05:03 +0100311 int (*validate_ns_entrypoint)(uintptr_t ns_entrypoint);
Soby Mathew981487a2015-07-13 14:10:57 +0100312 void (*get_sys_suspend_power_state)(
313 psci_power_state_t *req_state);
Yatharth Kochar241ec6c2016-05-09 18:26:35 +0100314 int (*get_pwr_lvl_state_idx)(plat_local_state_t pwr_domain_state,
315 int pwrlvl);
316 int (*translate_power_state_by_mpidr)(u_register_t mpidr,
317 unsigned int power_state,
318 psci_power_state_t *output_state);
Jeenu Viswambharan7f03e9d92016-08-03 15:54:50 +0100319 int (*get_node_hw_state)(u_register_t mpidr, unsigned int power_level);
Roberto Vargas0a4c2612017-08-03 08:16:16 +0100320 int (*mem_protect_chk)(uintptr_t base, u_register_t length);
321 int (*read_mem_protect)(int *val);
322 int (*write_mem_protect)(int val);
Roberto Vargasb820ad02017-07-26 09:23:09 +0100323 int (*system_reset2)(int is_vendor,
324 int reset_type, u_register_t cookie);
Soby Mathew981487a2015-07-13 14:10:57 +0100325} plat_psci_ops_t;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100326
327/*******************************************************************************
328 * Function & Data prototypes
329 ******************************************************************************/
Dan Handleya17fefa2014-05-14 12:38:32 +0100330unsigned int psci_version(void);
Soby Mathew011ca182015-07-29 17:05:03 +0100331int psci_cpu_on(u_register_t target_cpu,
332 uintptr_t entrypoint,
333 u_register_t context_id);
334int psci_cpu_suspend(unsigned int power_state,
335 uintptr_t entrypoint,
336 u_register_t context_id);
337int psci_system_suspend(uintptr_t entrypoint, u_register_t context_id);
338int psci_cpu_off(void);
339int psci_affinity_info(u_register_t target_affinity,
340 unsigned int lowest_affinity_level);
341int psci_migrate(u_register_t target_cpu);
Soby Mathew110fe362014-10-23 10:35:34 +0100342int psci_migrate_info_type(void);
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100343u_register_t psci_migrate_info_up_cpu(void);
Jeenu Viswambharan7f03e9d92016-08-03 15:54:50 +0100344int psci_node_hw_state(u_register_t target_cpu,
345 unsigned int power_level);
Soby Mathew011ca182015-07-29 17:05:03 +0100346int psci_features(unsigned int psci_fid);
Dan Handleya17fefa2014-05-14 12:38:32 +0100347void __dead2 psci_power_down_wfi(void);
Soby Mathewd0194872016-04-29 19:01:30 +0100348void psci_arch_setup(void);
349
Achin Gupta4f6ad662013-10-25 09:08:21 +0100350#endif /*__ASSEMBLY__*/
351
Antonio Nino Diaz5a42b682018-07-18 11:57:21 +0100352#endif /* PSCI_H */