Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 1 | /* |
Varun Wadekar | 1384a16 | 2017-06-05 14:54:46 -0700 | [diff] [blame] | 2 | * Copyright (c) 2014-2017, ARM Limited and Contributors. All rights reserved. |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 3 | * |
dp-arm | fa3cf0b | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 4 | * SPDX-License-Identifier: BSD-3-Clause |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 5 | */ |
| 6 | |
Antonio Nino Diaz | 5eb8837 | 2018-11-08 10:20:19 +0000 | [diff] [blame] | 7 | #ifndef CORTEX_A53_H |
| 8 | #define CORTEX_A53_H |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 9 | |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 10 | /* Cortex-A53 midr for revision 0 */ |
Varun Wadekar | c6a11f6 | 2017-05-25 18:04:48 -0700 | [diff] [blame] | 11 | #define CORTEX_A53_MIDR U(0x410FD030) |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 12 | |
Varun Wadekar | 3ce4e88 | 2015-08-21 15:52:51 +0530 | [diff] [blame] | 13 | /* Retention timer tick definitions */ |
Varun Wadekar | c6a11f6 | 2017-05-25 18:04:48 -0700 | [diff] [blame] | 14 | #define RETENTION_ENTRY_TICKS_2 U(0x1) |
| 15 | #define RETENTION_ENTRY_TICKS_8 U(0x2) |
| 16 | #define RETENTION_ENTRY_TICKS_32 U(0x3) |
| 17 | #define RETENTION_ENTRY_TICKS_64 U(0x4) |
| 18 | #define RETENTION_ENTRY_TICKS_128 U(0x5) |
| 19 | #define RETENTION_ENTRY_TICKS_256 U(0x6) |
| 20 | #define RETENTION_ENTRY_TICKS_512 U(0x7) |
Varun Wadekar | 3ce4e88 | 2015-08-21 15:52:51 +0530 | [diff] [blame] | 21 | |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 22 | /******************************************************************************* |
| 23 | * CPU Extended Control register specific definitions. |
| 24 | ******************************************************************************/ |
Eleanor Bonnici | 41b61be | 2017-08-09 16:42:40 +0100 | [diff] [blame] | 25 | #define CORTEX_A53_ECTLR_EL1 S3_1_C15_C2_1 |
Soby Mathew | 38b4bc9 | 2014-08-14 13:36:41 +0100 | [diff] [blame] | 26 | |
Eleanor Bonnici | 41b61be | 2017-08-09 16:42:40 +0100 | [diff] [blame] | 27 | #define CORTEX_A53_ECTLR_SMP_BIT (U(1) << 6) |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 28 | |
Eleanor Bonnici | 41b61be | 2017-08-09 16:42:40 +0100 | [diff] [blame] | 29 | #define CORTEX_A53_ECTLR_CPU_RET_CTRL_SHIFT U(0) |
| 30 | #define CORTEX_A53_ECTLR_CPU_RET_CTRL_MASK (U(0x7) << CORTEX_A53_ECTLR_CPU_RET_CTRL_SHIFT) |
Varun Wadekar | 3ce4e88 | 2015-08-21 15:52:51 +0530 | [diff] [blame] | 31 | |
Eleanor Bonnici | 41b61be | 2017-08-09 16:42:40 +0100 | [diff] [blame] | 32 | #define CORTEX_A53_ECTLR_FPU_RET_CTRL_SHIFT U(3) |
| 33 | #define CORTEX_A53_ECTLR_FPU_RET_CTRL_MASK (U(0x7) << CORTEX_A53_ECTLR_FPU_RET_CTRL_SHIFT) |
Varun Wadekar | 3ce4e88 | 2015-08-21 15:52:51 +0530 | [diff] [blame] | 34 | |
developer | 4fceaca | 2015-07-29 20:55:31 +0800 | [diff] [blame] | 35 | /******************************************************************************* |
Naga Sureshkumar Relli | 6a72a91 | 2016-07-01 12:52:41 +0530 | [diff] [blame] | 36 | * CPU Memory Error Syndrome register specific definitions. |
| 37 | ******************************************************************************/ |
Eleanor Bonnici | 41b61be | 2017-08-09 16:42:40 +0100 | [diff] [blame] | 38 | #define CORTEX_A53_MERRSR_EL1 S3_1_C15_C2_2 |
Naga Sureshkumar Relli | 6a72a91 | 2016-07-01 12:52:41 +0530 | [diff] [blame] | 39 | |
| 40 | /******************************************************************************* |
developer | 4fceaca | 2015-07-29 20:55:31 +0800 | [diff] [blame] | 41 | * CPU Auxiliary Control register specific definitions. |
| 42 | ******************************************************************************/ |
Eleanor Bonnici | 41b61be | 2017-08-09 16:42:40 +0100 | [diff] [blame] | 43 | #define CORTEX_A53_CPUACTLR_EL1 S3_1_C15_C2_0 |
developer | 4fceaca | 2015-07-29 20:55:31 +0800 | [diff] [blame] | 44 | |
Eleanor Bonnici | 41b61be | 2017-08-09 16:42:40 +0100 | [diff] [blame] | 45 | #define CORTEX_A53_CPUACTLR_EL1_ENDCCASCI_SHIFT U(44) |
| 46 | #define CORTEX_A53_CPUACTLR_EL1_ENDCCASCI (U(1) << CORTEX_A53_CPUACTLR_EL1_ENDCCASCI_SHIFT) |
| 47 | #define CORTEX_A53_CPUACTLR_EL1_RADIS_SHIFT U(27) |
| 48 | #define CORTEX_A53_CPUACTLR_EL1_RADIS (U(3) << CORTEX_A53_CPUACTLR_EL1_RADIS_SHIFT) |
| 49 | #define CORTEX_A53_CPUACTLR_EL1_L1RADIS_SHIFT U(25) |
| 50 | #define CORTEX_A53_CPUACTLR_EL1_L1RADIS (U(3) << CORTEX_A53_CPUACTLR_EL1_L1RADIS_SHIFT) |
| 51 | #define CORTEX_A53_CPUACTLR_EL1_DTAH_SHIFT U(24) |
| 52 | #define CORTEX_A53_CPUACTLR_EL1_DTAH (U(1) << CORTEX_A53_CPUACTLR_EL1_DTAH_SHIFT) |
developer | 4fceaca | 2015-07-29 20:55:31 +0800 | [diff] [blame] | 53 | |
| 54 | /******************************************************************************* |
| 55 | * L2 Auxiliary Control register specific definitions. |
| 56 | ******************************************************************************/ |
Eleanor Bonnici | 41b61be | 2017-08-09 16:42:40 +0100 | [diff] [blame] | 57 | #define CORTEX_A53_L2ACTLR_EL1 S3_1_C15_C0_0 |
developer | 4fceaca | 2015-07-29 20:55:31 +0800 | [diff] [blame] | 58 | |
Eleanor Bonnici | 41b61be | 2017-08-09 16:42:40 +0100 | [diff] [blame] | 59 | #define CORTEX_A53_L2ACTLR_ENABLE_UNIQUECLEAN (U(1) << 14) |
| 60 | #define CORTEX_A53_L2ACTLR_DISABLE_CLEAN_PUSH (U(1) << 3) |
Varun Wadekar | 3ce4e88 | 2015-08-21 15:52:51 +0530 | [diff] [blame] | 61 | /******************************************************************************* |
| 62 | * L2 Extended Control register specific definitions. |
| 63 | ******************************************************************************/ |
Eleanor Bonnici | 41b61be | 2017-08-09 16:42:40 +0100 | [diff] [blame] | 64 | #define CORTEX_A53_L2ECTLR_EL1 S3_1_C11_C0_3 |
Varun Wadekar | 3ce4e88 | 2015-08-21 15:52:51 +0530 | [diff] [blame] | 65 | |
Eleanor Bonnici | 41b61be | 2017-08-09 16:42:40 +0100 | [diff] [blame] | 66 | #define CORTEX_A53_L2ECTLR_RET_CTRL_SHIFT U(0) |
| 67 | #define CORTEX_A53_L2ECTLR_RET_CTRL_MASK (U(0x7) << L2ECTLR_RET_CTRL_SHIFT) |
Varun Wadekar | 3ce4e88 | 2015-08-21 15:52:51 +0530 | [diff] [blame] | 68 | |
Naga Sureshkumar Relli | 6a72a91 | 2016-07-01 12:52:41 +0530 | [diff] [blame] | 69 | /******************************************************************************* |
| 70 | * L2 Memory Error Syndrome register specific definitions. |
| 71 | ******************************************************************************/ |
Eleanor Bonnici | 41b61be | 2017-08-09 16:42:40 +0100 | [diff] [blame] | 72 | #define CORTEX_A53_L2MERRSR_EL1 S3_1_C15_C2_3 |
| 73 | |
Antonio Nino Diaz | 5eb8837 | 2018-11-08 10:20:19 +0000 | [diff] [blame] | 74 | #endif /* CORTEX_A53_H */ |