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git01.mediatek.com / filogic / atf / 4d81931dc18ea0865046ced61e0a63972a4f3492 / . / plat / arm / board / tc0 / fdts / tc0_spmc_manifest.dts
blob: 44c7008a82907dbbfc93e8d41d03892261f3fb48 [file] [log] [blame]
Arunachalam Ganapathyade4a202020-09-22 12:50:45 +0100[diff] [blame]1/*
Arunachalam Ganapathydfd1fb42021-05-27 16:03:58 +0100[diff] [blame]2 * Copyright (c) 2020-2021, Arm Limited. All rights reserved.
Arunachalam Ganapathyade4a202020-09-22 12:50:45 +0100[diff] [blame]3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6/dts-v1/;
7
8/ {
9 compatible = "arm,ffa-core-manifest-1.0";
10 #address-cells = <2>;
11 #size-cells = <1>;
12
13 attribute {
14 spmc_id = <0x8000>;
15 maj_ver = <0x1>;
16 min_ver = <0x0>;
17 exec_state = <0x0>;
18 load_address = <0x0 0xfd000000>;
19 entrypoint = <0x0 0xfd000000>;
20 binary_size = <0x80000>;
21 };
22
Arunachalam Ganapathyade4a202020-09-22 12:50:45 +0100[diff] [blame]23 hypervisor {
24 compatible = "hafnium,hafnium";
25 vm1 {
26 is_ffa_partition;
27 debug_name = "cactus-primary";
28 load_address = <0xfe000000>;
Avinash Mehtaf68a0842020-10-28 16:43:28 +0000[diff] [blame]29 vcpu_count = <8>;
30 mem_size = <1048576>;
Arunachalam Ganapathyade4a202020-09-22 12:50:45 +0100[diff] [blame]31 };
32 vm2 {
33 is_ffa_partition;
34 debug_name = "cactus-secondary";
35 load_address = <0xfe100000>;
Avinash Mehtaf68a0842020-10-28 16:43:28 +0000[diff] [blame]36 vcpu_count = <8>;
Arunachalam Ganapathyade4a202020-09-22 12:50:45 +0100[diff] [blame]37 mem_size = <1048576>;
38 };
39 vm3 {
40 is_ffa_partition;
41 debug_name = "cactus-tertiary";
42 load_address = <0xfe200000>;
Arunachalam Ganapathydfd1fb42021-05-27 16:03:58 +0100[diff] [blame]43 vcpu_count = <1>;
Arunachalam Ganapathyade4a202020-09-22 12:50:45 +0100[diff] [blame]44 mem_size = <1048576>;
45 };
46 };
47
48 cpus {
49 #address-cells = <0x2>;
50 #size-cells = <0x0>;
51
52 CPU0:cpu@0 {
53 device_type = "cpu";
54 compatible = "arm,armv8";
55 reg = <0x0 0x0>;
56 enable-method = "psci";
57 };
58
59 /*
Avinash Mehtaf68a0842020-10-28 16:43:28 +0000[diff] [blame]60 * SPMC (Hafnium) requires secondary cpu nodes are declared in
Arunachalam Ganapathyade4a202020-09-22 12:50:45 +0100[diff] [blame]61 * descending order
62 */
Avinash Mehtaf68a0842020-10-28 16:43:28 +0000[diff] [blame]63 CPU7:cpu@700 {
64 device_type = "cpu";
65 compatible = "arm,armv8";
66 reg = <0x0 0x700>;
67 enable-method = "psci";
68 };
69
70 CPU6:cpu@600 {
71 device_type = "cpu";
72 compatible = "arm,armv8";
73 reg = <0x0 0x600>;
74 enable-method = "psci";
75 };
76
77 CPU5:cpu@500 {
78 device_type = "cpu";
79 compatible = "arm,armv8";
80 reg = <0x0 0x500>;
81 enable-method = "psci";
82 };
83
84 CPU4:cpu@400 {
85 device_type = "cpu";
86 compatible = "arm,armv8";
87 reg = <0x0 0x400>;
88 enable-method = "psci";
89 };
90
Arunachalam Ganapathyade4a202020-09-22 12:50:45 +0100[diff] [blame]91 CPU3:cpu@300 {
92 device_type = "cpu";
93 compatible = "arm,armv8";
94 reg = <0x0 0x300>;
95 enable-method = "psci";
96 };
97
98 CPU2:cpu@200 {
99 device_type = "cpu";
100 compatible = "arm,armv8";
101 reg = <0x0 0x200>;
102 enable-method = "psci";
103 };
104
105 CPU1:cpu@100 {
106 device_type = "cpu";
107 compatible = "arm,armv8";
108 reg = <0x0 0x100>;
109 enable-method = "psci";
110 };
111 };
112
113 /* 32MB of TC0_TZC_DRAM1_BASE */
114 memory@fd000000 {
115 device_type = "memory";
116 reg = <0x0 0xfd000000 0x2000000>;
117 };
118};