blob: ad960f49385935e45b7c8cc6531effe01d6210ee [file] [log] [blame]
Soren Brinkmann76fcae32016-03-06 20:16:27 -08001/*
2 * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved.
3 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Soren Brinkmann76fcae32016-03-06 20:16:27 -08005 */
6
7#include <asm_macros.S>
8#include <gicv2.h>
9#include <platform_def.h>
10
11 .globl plat_secondary_cold_boot_setup
12 .globl plat_is_my_cpu_primary
13
14 /* -----------------------------------------------------
15 * void plat_secondary_cold_boot_setup (void);
16 *
17 * This function performs any platform specific actions
18 * needed for a secondary cpu after a cold reset e.g
19 * mark the cpu's presence, mechanism to place it in a
20 * holding pen etc.
21 * TODO: Should we read the PSYS register to make sure
22 * that the request has gone through.
23 * -----------------------------------------------------
24 */
25func plat_secondary_cold_boot_setup
26 mrs x0, mpidr_el1
27
28 /* Deactivate the gic cpu interface */
29 ldr x1, =BASE_GICC_BASE
30 mov w0, #(IRQ_BYP_DIS_GRP1 | FIQ_BYP_DIS_GRP1)
31 orr w0, w0, #(IRQ_BYP_DIS_GRP0 | FIQ_BYP_DIS_GRP0)
32 str w0, [x1, #GICC_CTLR]
33
34 /*
35 * There is no sane reason to come out of this wfi. This
36 * cpu will be powered on and reset by the cpu_on pm api
37 */
38 dsb sy
391:
Jeenu Viswambharan68aef102016-11-30 15:21:11 +000040 no_ret plat_panic_handler
Soren Brinkmann76fcae32016-03-06 20:16:27 -080041endfunc plat_secondary_cold_boot_setup
42
43func plat_is_my_cpu_primary
44 mov x9, x30
45 bl plat_my_core_pos
46 cmp x0, #ZYNQMP_PRIMARY_CPU
47 cset x0, eq
48 ret x9
49endfunc plat_is_my_cpu_primary