blob: 4735a9dccab5361fa5c04abed3c2e4682f7c61c9 [file] [log] [blame]
Dan Handley9df48042015-03-19 18:58:55 +00001/*
Roberto Vargas550eb082018-01-05 16:00:05 +00002 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
Dan Handley9df48042015-03-19 18:58:55 +00003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Dan Handley9df48042015-03-19 18:58:55 +00005 */
6
Dan Handley9df48042015-03-19 18:58:55 +00007#include <arch_helpers.h>
Soby Mathewfeac8fc2015-09-29 15:47:16 +01008#include <assert.h>
Soby Mathew61e8d0b2015-10-12 17:32:29 +01009#include <cassert.h>
Soby Mathewfeac8fc2015-09-29 15:47:16 +010010#include <css_pm.h>
Dan Handley9df48042015-03-19 18:58:55 +000011#include <debug.h>
12#include <errno.h>
13#include <plat_arm.h>
14#include <platform.h>
15#include <platform_def.h>
Soby Mathew200fffd2016-10-21 11:34:59 +010016#include "../drivers/scp/css_scp.h"
Soby Mathew12012dd2015-10-26 14:01:53 +000017
Soby Mathewfeac8fc2015-09-29 15:47:16 +010018/* Allow CSS platforms to override `plat_arm_psci_pm_ops` */
19#pragma weak plat_arm_psci_pm_ops
Soby Mathewfec4eb72015-07-01 16:16:20 +010020
Soby Mathew7799cf72015-04-16 14:49:09 +010021#if ARM_RECOM_STATE_ID_ENC
22/*
23 * The table storing the valid idle power states. Ensure that the
24 * array entries are populated in ascending order of state-id to
25 * enable us to use binary search during power state validation.
26 * The table must be terminated by a NULL entry.
27 */
28const unsigned int arm_pm_idle_states[] = {
Soby Mathewa869de12015-05-08 10:18:59 +010029 /* State-id - 0x001 */
30 arm_make_pwrstate_lvl2(ARM_LOCAL_STATE_RUN, ARM_LOCAL_STATE_RUN,
31 ARM_LOCAL_STATE_RET, ARM_PWR_LVL0, PSTATE_TYPE_STANDBY),
32 /* State-id - 0x002 */
33 arm_make_pwrstate_lvl2(ARM_LOCAL_STATE_RUN, ARM_LOCAL_STATE_RUN,
34 ARM_LOCAL_STATE_OFF, ARM_PWR_LVL0, PSTATE_TYPE_POWERDOWN),
35 /* State-id - 0x022 */
36 arm_make_pwrstate_lvl2(ARM_LOCAL_STATE_RUN, ARM_LOCAL_STATE_OFF,
37 ARM_LOCAL_STATE_OFF, ARM_PWR_LVL1, PSTATE_TYPE_POWERDOWN),
38#if PLAT_MAX_PWR_LVL > ARM_PWR_LVL1
39 /* State-id - 0x222 */
40 arm_make_pwrstate_lvl2(ARM_LOCAL_STATE_OFF, ARM_LOCAL_STATE_OFF,
41 ARM_LOCAL_STATE_OFF, ARM_PWR_LVL2, PSTATE_TYPE_POWERDOWN),
42#endif
Soby Mathew7799cf72015-04-16 14:49:09 +010043 0,
44};
Soby Mathewa869de12015-05-08 10:18:59 +010045#endif /* __ARM_RECOM_STATE_ID_ENC__ */
Soby Mathew7799cf72015-04-16 14:49:09 +010046
Soby Mathew61e8d0b2015-10-12 17:32:29 +010047/*
48 * All the power management helpers in this file assume at least cluster power
49 * level is supported.
50 */
51CASSERT(PLAT_MAX_PWR_LVL >= ARM_PWR_LVL1,
52 assert_max_pwr_lvl_supported_mismatch);
53
Soby Mathew7a3b5eb2016-12-09 15:23:08 +000054/*
55 * Ensure that the PLAT_MAX_PWR_LVL is not greater than CSS_SYSTEM_PWR_DMN_LVL
56 * assumed by the CSS layer.
57 */
58CASSERT(PLAT_MAX_PWR_LVL <= CSS_SYSTEM_PWR_DMN_LVL,
59 assert_max_pwr_lvl_higher_than_css_sys_lvl);
60
Dan Handley9df48042015-03-19 18:58:55 +000061/*******************************************************************************
Soby Mathewfec4eb72015-07-01 16:16:20 +010062 * Handler called when a power domain is about to be turned on. The
Dan Handley9df48042015-03-19 18:58:55 +000063 * level and mpidr determine the affinity instance.
64 ******************************************************************************/
Soby Mathewfec4eb72015-07-01 16:16:20 +010065int css_pwr_domain_on(u_register_t mpidr)
Dan Handley9df48042015-03-19 18:58:55 +000066{
Soby Mathew200fffd2016-10-21 11:34:59 +010067 css_scp_on(mpidr);
Dan Handley9df48042015-03-19 18:58:55 +000068
69 return PSCI_E_SUCCESS;
70}
71
Soby Mathew12012dd2015-10-26 14:01:53 +000072static void css_pwr_domain_on_finisher_common(
73 const psci_power_state_t *target_state)
Dan Handley9df48042015-03-19 18:58:55 +000074{
Soby Mathew12012dd2015-10-26 14:01:53 +000075 assert(CSS_CORE_PWR_STATE(target_state) == ARM_LOCAL_STATE_OFF);
Soby Mathew61e8d0b2015-10-12 17:32:29 +010076
Soby Mathew9ca28062017-10-11 16:08:58 +010077 /* Enable the gic cpu interface */
78 plat_arm_gic_cpuif_enable();
79
Dan Handley9df48042015-03-19 18:58:55 +000080 /*
81 * Perform the common cluster specific operations i.e enable coherency
82 * if this cluster was off.
83 */
Soby Mathew12012dd2015-10-26 14:01:53 +000084 if (CSS_CLUSTER_PWR_STATE(target_state) == ARM_LOCAL_STATE_OFF)
Vikram Kanigirifbb13012016-02-15 11:54:14 +000085 plat_arm_interconnect_enter_coherency();
Soby Mathew12012dd2015-10-26 14:01:53 +000086}
Dan Handley9df48042015-03-19 18:58:55 +000087
Soby Mathew12012dd2015-10-26 14:01:53 +000088/*******************************************************************************
89 * Handler called when a power level has just been powered on after
90 * being turned off earlier. The target_state encodes the low power state that
91 * each level has woken up from. This handler would never be invoked with
92 * the system power domain uninitialized as either the primary would have taken
93 * care of it as part of cold boot or the first core awakened from system
94 * suspend would have already initialized it.
95 ******************************************************************************/
96void css_pwr_domain_on_finish(const psci_power_state_t *target_state)
97{
98 /* Assert that the system power domain need not be initialized */
Nariman Poushincd956262018-05-01 09:28:40 +010099 assert(css_system_pwr_state(target_state) == ARM_LOCAL_STATE_RUN);
Soby Mathew61e8d0b2015-10-12 17:32:29 +0100100
Achin Gupta1fa7eb62015-11-03 14:18:34 +0000101 /* Program the gic per-cpu distributor or re-distributor interface */
102 plat_arm_gic_pcpu_init();
103
Soby Mathew9ca28062017-10-11 16:08:58 +0100104 css_pwr_domain_on_finisher_common(target_state);
Dan Handley9df48042015-03-19 18:58:55 +0000105}
106
107/*******************************************************************************
108 * Common function called while turning a cpu off or suspending it. It is called
109 * from css_off() or css_suspend() when these functions in turn are called for
Soby Mathewfec4eb72015-07-01 16:16:20 +0100110 * power domain at the highest power level which will be powered down. It
111 * performs the actions common to the OFF and SUSPEND calls.
Dan Handley9df48042015-03-19 18:58:55 +0000112 ******************************************************************************/
Soby Mathewfec4eb72015-07-01 16:16:20 +0100113static void css_power_down_common(const psci_power_state_t *target_state)
Dan Handley9df48042015-03-19 18:58:55 +0000114{
Dan Handley9df48042015-03-19 18:58:55 +0000115 /* Prevent interrupts from spuriously waking up this cpu */
Achin Gupta1fa7eb62015-11-03 14:18:34 +0000116 plat_arm_gic_cpuif_disable();
Dan Handley9df48042015-03-19 18:58:55 +0000117
118 /* Cluster is to be turned off, so disable coherency */
Soby Mathew200fffd2016-10-21 11:34:59 +0100119 if (CSS_CLUSTER_PWR_STATE(target_state) == ARM_LOCAL_STATE_OFF)
Vikram Kanigirifbb13012016-02-15 11:54:14 +0000120 plat_arm_interconnect_exit_coherency();
Dan Handley9df48042015-03-19 18:58:55 +0000121}
122
123/*******************************************************************************
Soby Mathewfec4eb72015-07-01 16:16:20 +0100124 * Handler called when a power domain is about to be turned off. The
125 * target_state encodes the power state that each level should transition to.
Dan Handley9df48042015-03-19 18:58:55 +0000126 ******************************************************************************/
Soby Mathewfeac8fc2015-09-29 15:47:16 +0100127void css_pwr_domain_off(const psci_power_state_t *target_state)
Dan Handley9df48042015-03-19 18:58:55 +0000128{
Soby Mathew12012dd2015-10-26 14:01:53 +0000129 assert(CSS_CORE_PWR_STATE(target_state) == ARM_LOCAL_STATE_OFF);
Soby Mathewfec4eb72015-07-01 16:16:20 +0100130 css_power_down_common(target_state);
Soby Mathew200fffd2016-10-21 11:34:59 +0100131 css_scp_off(target_state);
Dan Handley9df48042015-03-19 18:58:55 +0000132}
133
134/*******************************************************************************
Soby Mathewfec4eb72015-07-01 16:16:20 +0100135 * Handler called when a power domain is about to be suspended. The
136 * target_state encodes the power state that each level should transition to.
Dan Handley9df48042015-03-19 18:58:55 +0000137 ******************************************************************************/
Soby Mathewfeac8fc2015-09-29 15:47:16 +0100138void css_pwr_domain_suspend(const psci_power_state_t *target_state)
Dan Handley9df48042015-03-19 18:58:55 +0000139{
Soby Mathewfec4eb72015-07-01 16:16:20 +0100140 /*
Soby Mathew12012dd2015-10-26 14:01:53 +0000141 * CSS currently supports retention only at cpu level. Just return
Soby Mathewfec4eb72015-07-01 16:16:20 +0100142 * as nothing is to be done for retention.
143 */
Soby Mathew12012dd2015-10-26 14:01:53 +0000144 if (CSS_CORE_PWR_STATE(target_state) == ARM_LOCAL_STATE_RET)
Dan Handley9df48042015-03-19 18:58:55 +0000145 return;
146
Soby Mathew9ca28062017-10-11 16:08:58 +0100147
Soby Mathew12012dd2015-10-26 14:01:53 +0000148 assert(CSS_CORE_PWR_STATE(target_state) == ARM_LOCAL_STATE_OFF);
Soby Mathewfec4eb72015-07-01 16:16:20 +0100149 css_power_down_common(target_state);
Soby Mathew9ca28062017-10-11 16:08:58 +0100150
151 /* Perform system domain state saving if issuing system suspend */
Nariman Poushincd956262018-05-01 09:28:40 +0100152 if (css_system_pwr_state(target_state) == ARM_LOCAL_STATE_OFF) {
Soby Mathew9ca28062017-10-11 16:08:58 +0100153 arm_system_pwr_domain_save();
154
155 /* Power off the Redistributor after having saved its context */
156 plat_arm_gic_redistif_off();
157 }
158
Soby Mathew200fffd2016-10-21 11:34:59 +0100159 css_scp_suspend(target_state);
Dan Handley9df48042015-03-19 18:58:55 +0000160}
161
162/*******************************************************************************
Soby Mathewfec4eb72015-07-01 16:16:20 +0100163 * Handler called when a power domain has just been powered on after
164 * having been suspended earlier. The target_state encodes the low power state
165 * that each level has woken up from.
Dan Handley9df48042015-03-19 18:58:55 +0000166 * TODO: At the moment we reuse the on finisher and reinitialize the secure
167 * context. Need to implement a separate suspend finisher.
168 ******************************************************************************/
Soby Mathewfeac8fc2015-09-29 15:47:16 +0100169void css_pwr_domain_suspend_finish(
Soby Mathewfec4eb72015-07-01 16:16:20 +0100170 const psci_power_state_t *target_state)
Dan Handley9df48042015-03-19 18:58:55 +0000171{
Soby Mathew12012dd2015-10-26 14:01:53 +0000172 /* Return as nothing is to be done on waking up from retention. */
173 if (CSS_CORE_PWR_STATE(target_state) == ARM_LOCAL_STATE_RET)
Soby Mathewfec4eb72015-07-01 16:16:20 +0100174 return;
175
Soby Mathew12012dd2015-10-26 14:01:53 +0000176 /* Perform system domain restore if woken up from system suspend */
Nariman Poushincd956262018-05-01 09:28:40 +0100177 if (css_system_pwr_state(target_state) == ARM_LOCAL_STATE_OFF)
Soby Mathew9ca28062017-10-11 16:08:58 +0100178 /*
179 * At this point, the Distributor must be powered on to be ready
180 * to have its state restored. The Redistributor will be powered
181 * on as part of gicv3_rdistif_init_restore.
182 */
Soby Mathew12012dd2015-10-26 14:01:53 +0000183 arm_system_pwr_domain_resume();
Soby Mathew12012dd2015-10-26 14:01:53 +0000184
185 css_pwr_domain_on_finisher_common(target_state);
Dan Handley9df48042015-03-19 18:58:55 +0000186}
187
188/*******************************************************************************
189 * Handlers to shutdown/reboot the system
190 ******************************************************************************/
Soby Mathewfeac8fc2015-09-29 15:47:16 +0100191void __dead2 css_system_off(void)
Dan Handley9df48042015-03-19 18:58:55 +0000192{
Soby Mathew200fffd2016-10-21 11:34:59 +0100193 css_scp_sys_shutdown();
Dan Handley9df48042015-03-19 18:58:55 +0000194}
195
Soby Mathewfeac8fc2015-09-29 15:47:16 +0100196void __dead2 css_system_reset(void)
Dan Handley9df48042015-03-19 18:58:55 +0000197{
Soby Mathew200fffd2016-10-21 11:34:59 +0100198 css_scp_sys_reboot();
Dan Handley9df48042015-03-19 18:58:55 +0000199}
200
201/*******************************************************************************
Soby Mathewfec4eb72015-07-01 16:16:20 +0100202 * Handler called when the CPU power domain is about to enter standby.
Dan Handley9df48042015-03-19 18:58:55 +0000203 ******************************************************************************/
Soby Mathewfec4eb72015-07-01 16:16:20 +0100204void css_cpu_standby(plat_local_state_t cpu_state)
Dan Handley9df48042015-03-19 18:58:55 +0000205{
206 unsigned int scr;
207
Soby Mathewfec4eb72015-07-01 16:16:20 +0100208 assert(cpu_state == ARM_LOCAL_STATE_RET);
209
Dan Handley9df48042015-03-19 18:58:55 +0000210 scr = read_scr_el3();
David Wangc1d9cfb2016-06-07 09:22:40 +0800211 /*
212 * Enable the Non secure interrupt to wake the CPU.
213 * In GICv3 affinity routing mode, the non secure group1 interrupts use
214 * the PhysicalFIQ at EL3 whereas in GICv2, it uses the PhysicalIRQ.
215 * Enabling both the bits works for both GICv2 mode and GICv3 affinity
216 * routing mode.
217 */
218 write_scr_el3(scr | SCR_IRQ_BIT | SCR_FIQ_BIT);
Dan Handley9df48042015-03-19 18:58:55 +0000219 isb();
220 dsb();
221 wfi();
222
223 /*
224 * Restore SCR to the original value, synchronisation of scr_el3 is
225 * done by eret while el3_exit to save some execution cycles.
226 */
227 write_scr_el3(scr);
228}
229
230/*******************************************************************************
Soby Mathew61e8d0b2015-10-12 17:32:29 +0100231 * Handler called to return the 'req_state' for system suspend.
232 ******************************************************************************/
233void css_get_sys_suspend_power_state(psci_power_state_t *req_state)
234{
235 unsigned int i;
236
237 /*
238 * System Suspend is supported only if the system power domain node
239 * is implemented.
240 */
Soby Mathew7a3b5eb2016-12-09 15:23:08 +0000241 assert(PLAT_MAX_PWR_LVL == CSS_SYSTEM_PWR_DMN_LVL);
Soby Mathew61e8d0b2015-10-12 17:32:29 +0100242
243 for (i = ARM_PWR_LVL0; i <= PLAT_MAX_PWR_LVL; i++)
244 req_state->pwr_domain_state[i] = ARM_LOCAL_STATE_OFF;
245}
246
247/*******************************************************************************
Jeenu Viswambharan9cc4fc02016-08-04 09:43:15 +0100248 * Handler to query CPU/cluster power states from SCP
249 ******************************************************************************/
250int css_node_hw_state(u_register_t mpidr, unsigned int power_level)
251{
Soby Mathew200fffd2016-10-21 11:34:59 +0100252 return css_scp_get_power_state(mpidr, power_level);
Jeenu Viswambharan9cc4fc02016-08-04 09:43:15 +0100253}
254
Soby Mathew7a3b5eb2016-12-09 15:23:08 +0000255/*
256 * The system power domain suspend is only supported only via
257 * PSCI SYSTEM_SUSPEND API. PSCI CPU_SUSPEND request to system power domain
258 * will be downgraded to the lower level.
259 */
260static int css_validate_power_state(unsigned int power_state,
261 psci_power_state_t *req_state)
262{
263 int rc;
264 rc = arm_validate_power_state(power_state, req_state);
265
266 /*
Nariman Poushin16b41092018-05-01 13:07:47 +0100267 * Ensure that we don't overrun the pwr_domain_state array in the case
268 * where the platform supported max power level is less than the system
269 * power level
270 */
271
272#if (PLAT_MAX_PWR_LVL == CSS_SYSTEM_PWR_DMN_LVL)
273
274 /*
Soby Mathew7a3b5eb2016-12-09 15:23:08 +0000275 * Ensure that the system power domain level is never suspended
276 * via PSCI CPU SUSPEND API. Currently system suspend is only
277 * supported via PSCI SYSTEM SUSPEND API.
278 */
Nariman Poushin16b41092018-05-01 13:07:47 +0100279
280 req_state->pwr_domain_state[CSS_SYSTEM_PWR_DMN_LVL] =
281 ARM_LOCAL_STATE_RUN;
282#endif
283
Soby Mathew7a3b5eb2016-12-09 15:23:08 +0000284 return rc;
285}
286
287/*
288 * Custom `translate_power_state_by_mpidr` handler for CSS. Unlike in the
289 * `css_validate_power_state`, we do not downgrade the system power
290 * domain level request in `power_state` as it will be used to query the
291 * PSCI_STAT_COUNT/RESIDENCY at the system power domain level.
292 */
293static int css_translate_power_state_by_mpidr(u_register_t mpidr,
294 unsigned int power_state,
295 psci_power_state_t *output_state)
296{
297 return arm_validate_power_state(power_state, output_state);
298}
299
Jeenu Viswambharan9cc4fc02016-08-04 09:43:15 +0100300/*******************************************************************************
Soby Mathewfeac8fc2015-09-29 15:47:16 +0100301 * Export the platform handlers via plat_arm_psci_pm_ops. The ARM Standard
302 * platform will take care of registering the handlers with PSCI.
Dan Handley9df48042015-03-19 18:58:55 +0000303 ******************************************************************************/
Soby Mathew0b4c5a32016-10-21 17:51:22 +0100304plat_psci_ops_t plat_arm_psci_pm_ops = {
Soby Mathewfec4eb72015-07-01 16:16:20 +0100305 .pwr_domain_on = css_pwr_domain_on,
306 .pwr_domain_on_finish = css_pwr_domain_on_finish,
307 .pwr_domain_off = css_pwr_domain_off,
308 .cpu_standby = css_cpu_standby,
309 .pwr_domain_suspend = css_pwr_domain_suspend,
310 .pwr_domain_suspend_finish = css_pwr_domain_suspend_finish,
Dan Handley9df48042015-03-19 18:58:55 +0000311 .system_off = css_system_off,
312 .system_reset = css_system_reset,
Soby Mathew7a3b5eb2016-12-09 15:23:08 +0000313 .validate_power_state = css_validate_power_state,
Jeenu Viswambharan59424d82017-09-19 09:27:18 +0100314 .validate_ns_entrypoint = arm_validate_psci_entrypoint,
Soby Mathew7a3b5eb2016-12-09 15:23:08 +0000315 .translate_power_state_by_mpidr = css_translate_power_state_by_mpidr,
316 .get_node_hw_state = css_node_hw_state,
Roberto Vargasa1c16b62017-08-03 09:16:43 +0100317 .get_sys_suspend_power_state = css_get_sys_suspend_power_state,
Roberto Vargas550eb082018-01-05 16:00:05 +0000318
319#if defined(PLAT_ARM_MEM_PROT_ADDR)
Roberto Vargasa1c16b62017-08-03 09:16:43 +0100320 .mem_protect_chk = arm_psci_mem_protect_chk,
321 .read_mem_protect = arm_psci_read_mem_protect,
322 .write_mem_protect = arm_nor_psci_write_mem_protect,
323#endif
Roberto Vargas3caafd72017-08-16 08:57:45 +0100324#if CSS_USE_SCMI_SDS_DRIVER
325 .system_reset2 = css_system_reset2,
326#endif
Dan Handley9df48042015-03-19 18:58:55 +0000327};