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Yann Gautier4ede20a2020-09-18 15:04:14 +02001// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2/*
Nicolas Le Bayon79c388e2020-09-25 17:25:09 +02003 * Copyright (c) 2019-2022, STMicroelectronics - All Rights Reserved
Yann Gautier4ede20a2020-09-18 15:04:14 +02004 * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
5 */
6
7#include <dt-bindings/clock/stm32mp1-clksrc.h>
8#include "stm32mp15-ddr3-1x4Gb-1066-binG.dtsi"
9
10/ {
11 memory@c0000000 {
12 device_type = "memory";
13 reg = <0xc0000000 0x20000000>;
14 };
15
16 vin: vin {
17 compatible = "regulator-fixed";
18 regulator-name = "vin";
19 regulator-min-microvolt = <5000000>;
20 regulator-max-microvolt = <5000000>;
21 regulator-always-on;
22 };
23};
24
25&bsec {
26 board_id: board_id@ec {
27 reg = <0xec 0x4>;
28 st,non-secure-otp;
29 };
30};
31
32&clk_hse {
33 st,digbypass;
34};
35
Johann Neuhausera5ef16a2022-07-08 15:22:05 +020036&cpu0 {
Yann Gautier4ede20a2020-09-18 15:04:14 +020037 cpu-supply = <&vddcore>;
38};
39
Johann Neuhausera5ef16a2022-07-08 15:22:05 +020040&cpu1 {
Yann Gautier4ede20a2020-09-18 15:04:14 +020041 cpu-supply = <&vddcore>;
42};
43
44&hash1 {
45 status = "okay";
46};
47
48&i2c4 {
49 pinctrl-names = "default";
50 pinctrl-0 = <&i2c4_pins_a>;
51 i2c-scl-rising-time-ns = <185>;
52 i2c-scl-falling-time-ns = <20>;
53 clock-frequency = <400000>;
54 status = "okay";
55
56 pmic: stpmic@33 {
57 compatible = "st,stpmic1";
58 reg = <0x33>;
59 interrupts-extended = <&exti_pwr 55 IRQ_TYPE_EDGE_FALLING>;
60 interrupt-controller;
61 #interrupt-cells = <2>;
62 status = "okay";
63
64 regulators {
65 compatible = "st,stpmic1-regulators";
66 buck1-supply = <&vin>;
67 buck2-supply = <&vin>;
68 buck3-supply = <&vin>;
69 buck4-supply = <&vin>;
70 ldo1-supply = <&v3v3>;
71 ldo2-supply = <&vin>;
72 ldo3-supply = <&vdd_ddr>;
73 ldo4-supply = <&vin>;
74 ldo5-supply = <&vin>;
75 ldo6-supply = <&v3v3>;
76 vref_ddr-supply = <&vin>;
77 boost-supply = <&vin>;
78 pwr_sw1-supply = <&bst_out>;
79 pwr_sw2-supply = <&bst_out>;
80
81 vddcore: buck1 {
82 regulator-name = "vddcore";
83 regulator-min-microvolt = <1200000>;
84 regulator-max-microvolt = <1350000>;
85 regulator-always-on;
86 regulator-initial-mode = <0>;
87 regulator-over-current-protection;
88 };
89
90 vdd_ddr: buck2 {
91 regulator-name = "vdd_ddr";
92 regulator-min-microvolt = <1350000>;
93 regulator-max-microvolt = <1350000>;
94 regulator-always-on;
95 regulator-initial-mode = <0>;
96 regulator-over-current-protection;
97 };
98
99 vdd: buck3 {
100 regulator-name = "vdd";
101 regulator-min-microvolt = <3300000>;
102 regulator-max-microvolt = <3300000>;
103 regulator-always-on;
104 st,mask-reset;
105 regulator-initial-mode = <0>;
106 regulator-over-current-protection;
107 };
108
109 v3v3: buck4 {
110 regulator-name = "v3v3";
111 regulator-min-microvolt = <3300000>;
112 regulator-max-microvolt = <3300000>;
113 regulator-always-on;
114 regulator-over-current-protection;
115 regulator-initial-mode = <0>;
116 };
117
118 v1v8_audio: ldo1 {
119 regulator-name = "v1v8_audio";
120 regulator-min-microvolt = <1800000>;
121 regulator-max-microvolt = <1800000>;
122 regulator-always-on;
123 };
124
125 v3v3_hdmi: ldo2 {
126 regulator-name = "v3v3_hdmi";
127 regulator-min-microvolt = <3300000>;
128 regulator-max-microvolt = <3300000>;
129 regulator-always-on;
130 };
131
132 vtt_ddr: ldo3 {
133 regulator-name = "vtt_ddr";
Yann Gautier4ede20a2020-09-18 15:04:14 +0200134 regulator-always-on;
135 regulator-over-current-protection;
Pascal Paillet1b7e8ff2021-01-07 18:05:46 +0100136 st,regulator-sink-source;
Yann Gautier4ede20a2020-09-18 15:04:14 +0200137 };
138
139 vdd_usb: ldo4 {
140 regulator-name = "vdd_usb";
141 regulator-min-microvolt = <3300000>;
142 regulator-max-microvolt = <3300000>;
Yann Gautier4ede20a2020-09-18 15:04:14 +0200143 };
144
145 vdda: ldo5 {
146 regulator-name = "vdda";
147 regulator-min-microvolt = <2900000>;
148 regulator-max-microvolt = <2900000>;
149 regulator-boot-on;
150 };
151
152 v1v2_hdmi: ldo6 {
153 regulator-name = "v1v2_hdmi";
154 regulator-min-microvolt = <1200000>;
155 regulator-max-microvolt = <1200000>;
156 regulator-always-on;
157 };
158
159 vref_ddr: vref_ddr {
160 regulator-name = "vref_ddr";
161 regulator-always-on;
Yann Gautier4ede20a2020-09-18 15:04:14 +0200162 };
163
164 bst_out: boost {
165 regulator-name = "bst_out";
166 };
167
168 vbus_otg: pwr_sw1 {
169 regulator-name = "vbus_otg";
170 };
171
172 vbus_sw: pwr_sw2 {
173 regulator-name = "vbus_sw";
174 regulator-active-discharge = <1>;
175 };
176 };
177 };
178};
179
180&iwdg2 {
181 timeout-sec = <32>;
182 status = "okay";
Yann Gautier4ede20a2020-09-18 15:04:14 +0200183};
184
185&pwr_regulators {
186 vdd-supply = <&vdd>;
187 vdd_3v3_usbfs-supply = <&vdd_usb>;
188};
189
190&rcc {
Yann Gautier4ede20a2020-09-18 15:04:14 +0200191 st,clksrc = <
192 CLK_MPU_PLL1P
193 CLK_AXI_PLL2P
194 CLK_MCU_PLL3P
195 CLK_PLL12_HSE
196 CLK_PLL3_HSE
197 CLK_PLL4_HSE
198 CLK_RTC_LSE
199 CLK_MCO1_DISABLED
200 CLK_MCO2_DISABLED
201 >;
202
203 st,clkdiv = <
204 1 /*MPU*/
205 0 /*AXI*/
206 0 /*MCU*/
207 1 /*APB1*/
208 1 /*APB2*/
209 1 /*APB3*/
210 1 /*APB4*/
211 2 /*APB5*/
212 23 /*RTC*/
213 0 /*MCO1*/
214 0 /*MCO2*/
215 >;
216
217 st,pkcs = <
218 CLK_CKPER_HSE
219 CLK_FMC_ACLK
220 CLK_QSPI_ACLK
Yann Gautierdbbf79a2021-05-17 11:25:37 +0200221 CLK_ETH_PLL4P
Yann Gautier4ede20a2020-09-18 15:04:14 +0200222 CLK_SDMMC12_PLL4P
223 CLK_DSI_DSIPLL
224 CLK_STGEN_HSE
225 CLK_USBPHY_HSE
226 CLK_SPI2S1_PLL3Q
227 CLK_SPI2S23_PLL3Q
228 CLK_SPI45_HSI
229 CLK_SPI6_HSI
230 CLK_I2C46_HSI
231 CLK_SDMMC3_PLL4P
232 CLK_USBO_USBPHY
233 CLK_ADC_CKPER
234 CLK_CEC_LSE
235 CLK_I2C12_HSI
236 CLK_I2C35_HSI
237 CLK_UART1_HSI
238 CLK_UART24_HSI
239 CLK_UART35_HSI
240 CLK_UART6_HSI
241 CLK_UART78_HSI
242 CLK_SPDIF_PLL4P
243 CLK_FDCAN_PLL4R
244 CLK_SAI1_PLL3Q
245 CLK_SAI2_PLL3Q
246 CLK_SAI3_PLL3Q
247 CLK_SAI4_PLL3Q
248 CLK_RNG1_LSI
249 CLK_RNG2_LSI
250 CLK_LPTIM1_PCLK1
251 CLK_LPTIM23_PCLK3
252 CLK_LPTIM45_LSE
253 >;
254
255 /* VCO = 1300.0 MHz => P = 650 (CPU) */
256 pll1: st,pll@0 {
257 compatible = "st,stm32mp1-pll";
258 reg = <0>;
259 cfg = < 2 80 0 0 0 PQR(1,0,0) >;
260 frac = < 0x800 >;
261 };
262
263 /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
264 pll2: st,pll@1 {
265 compatible = "st,stm32mp1-pll";
266 reg = <1>;
267 cfg = <2 65 1 0 0 PQR(1,1,1)>;
268 frac = <0x1400>;
269 };
270
271 /* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
272 pll3: st,pll@2 {
273 compatible = "st,stm32mp1-pll";
274 reg = <2>;
275 cfg = <1 33 1 16 36 PQR(1,1,1)>;
276 frac = <0x1a04>;
277 };
278
279 /* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */
280 pll4: st,pll@3 {
281 compatible = "st,stm32mp1-pll";
282 reg = <3>;
283 cfg = <3 98 5 7 7 PQR(1,1,1)>;
284 };
285};
286
287&rng1 {
288 status = "okay";
289};
290
291&rtc {
292 status = "okay";
293};
294
295&sdmmc1 {
296 pinctrl-names = "default";
297 pinctrl-0 = <&sdmmc1_b4_pins_a>;
298 disable-wp;
299 st,neg-edge;
300 bus-width = <4>;
301 vmmc-supply = <&v3v3>;
302 status = "okay";
303};
304
Yann Gautier4ede20a2020-09-18 15:04:14 +0200305&uart4 {
306 pinctrl-names = "default";
307 pinctrl-0 = <&uart4_pins_a>;
308 status = "okay";
309};
310
311&uart7 {
312 pinctrl-names = "default";
Yann Gautierbb053d52021-10-20 17:22:32 +0200313 pinctrl-0 = <&uart7_pins_c>;
Yann Gautier4ede20a2020-09-18 15:04:14 +0200314 status = "disabled";
315};
316
317&usart3 {
318 pinctrl-names = "default";
Yann Gautierbb053d52021-10-20 17:22:32 +0200319 pinctrl-0 = <&usart3_pins_c>;
Yann Gautier4ede20a2020-09-18 15:04:14 +0200320 uart-has-rtscts;
321 status = "disabled";
322};
323
324&usbotg_hs {
325 phys = <&usbphyc_port1 0>;
326 phy-names = "usb2-phy";
327 usb-role-switch;
328 status = "okay";
329};
330
331&usbphyc {
332 status = "okay";
333};
334
335&usbphyc_port0 {
336 phy-supply = <&vdd_usb>;
337};
338
339&usbphyc_port1 {
340 phy-supply = <&vdd_usb>;
341};