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Soby Mathewc6820d12016-05-09 17:49:55 +01001/*
Antonio Nino Diaz128de8d2018-08-07 19:59:49 +01002 * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
Soby Mathewc6820d12016-05-09 17:49:55 +01003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Soby Mathewc6820d12016-05-09 17:49:55 +01005 */
6
7#ifndef __ARCH_HELPERS_H__
8#define __ARCH_HELPERS_H__
9
10#include <arch.h> /* for additional register definitions */
Antonio Nino Diaz4b32e622018-08-16 16:52:57 +010011#include <cdefs.h>
Soby Mathewc6820d12016-05-09 17:49:55 +010012#include <stdint.h>
Antonio Nino Diaz4b32e622018-08-16 16:52:57 +010013#include <string.h>
Soby Mathewc6820d12016-05-09 17:49:55 +010014
15/**********************************************************************
16 * Macros which create inline functions to read or write CPU system
17 * registers
18 *********************************************************************/
19
20#define _DEFINE_COPROCR_WRITE_FUNC(_name, coproc, opc1, CRn, CRm, opc2) \
21static inline void write_## _name(u_register_t v) \
22{ \
23 __asm__ volatile ("mcr "#coproc","#opc1",%0,"#CRn","#CRm","#opc2 : : "r" (v));\
24}
25
26#define _DEFINE_COPROCR_READ_FUNC(_name, coproc, opc1, CRn, CRm, opc2) \
27static inline u_register_t read_ ## _name(void) \
28{ \
29 u_register_t v; \
30 __asm__ volatile ("mrc "#coproc","#opc1",%0,"#CRn","#CRm","#opc2 : "=r" (v));\
31 return v; \
32}
33
34/*
35 * The undocumented %Q and %R extended asm are used to implemented the below
36 * 64 bit `mrrc` and `mcrr` instructions. It works only on Little Endian
37 * systems for GCC versions < 4.6. Above GCC 4.6, both Little Endian and
38 * Big Endian systems generate the right instruction encoding.
39 */
dp-arm320e8442017-05-02 12:00:08 +010040#if !(__clang__ || __GNUC__ > (4) || __GNUC__ == (4) && __GNUC_MINOR__ >= (6))
41#error "clang or GCC 4.6 or above is required to build AArch32 Trusted Firmware"
Soby Mathewc6820d12016-05-09 17:49:55 +010042#endif
43
44#define _DEFINE_COPROCR_WRITE_FUNC_64(_name, coproc, opc1, CRm) \
45static inline void write64_## _name(uint64_t v) \
46{ \
47 __asm__ volatile ("mcrr "#coproc","#opc1", %Q0, %R0,"#CRm : : "r" (v));\
48}
49
50#define _DEFINE_COPROCR_READ_FUNC_64(_name, coproc, opc1, CRm) \
51static inline uint64_t read64_## _name(void) \
52{ uint64_t v; \
53 __asm__ volatile ("mrrc "#coproc","#opc1", %Q0, %R0,"#CRm : "=r" (v));\
54 return v; \
55}
56
57#define _DEFINE_SYSREG_READ_FUNC(_name, _reg_name) \
58static inline u_register_t read_ ## _name(void) \
59{ \
60 u_register_t v; \
61 __asm__ volatile ("mrs %0, " #_reg_name : "=r" (v)); \
62 return v; \
63}
64
65#define _DEFINE_SYSREG_WRITE_FUNC(_name, _reg_name) \
66static inline void write_ ## _name(u_register_t v) \
67{ \
68 __asm__ volatile ("msr " #_reg_name ", %0" : : "r" (v)); \
69}
70
71#define _DEFINE_SYSREG_WRITE_CONST_FUNC(_name, _reg_name) \
72static inline void write_ ## _name(const u_register_t v) \
73{ \
74 __asm__ volatile ("msr " #_reg_name ", %0" : : "i" (v)); \
75}
76
77/* Define read function for coproc register */
78#define DEFINE_COPROCR_READ_FUNC(_name, ...) \
79 _DEFINE_COPROCR_READ_FUNC(_name, __VA_ARGS__)
80
81/* Define read & write function for coproc register */
82#define DEFINE_COPROCR_RW_FUNCS(_name, ...) \
83 _DEFINE_COPROCR_READ_FUNC(_name, __VA_ARGS__) \
84 _DEFINE_COPROCR_WRITE_FUNC(_name, __VA_ARGS__)
85
86/* Define 64 bit read function for coproc register */
87#define DEFINE_COPROCR_READ_FUNC_64(_name, ...) \
88 _DEFINE_COPROCR_READ_FUNC_64(_name, __VA_ARGS__)
89
90/* Define 64 bit read & write function for coproc register */
91#define DEFINE_COPROCR_RW_FUNCS_64(_name, ...) \
92 _DEFINE_COPROCR_READ_FUNC_64(_name, __VA_ARGS__) \
93 _DEFINE_COPROCR_WRITE_FUNC_64(_name, __VA_ARGS__)
94
95/* Define read & write function for system register */
96#define DEFINE_SYSREG_RW_FUNCS(_name) \
97 _DEFINE_SYSREG_READ_FUNC(_name, _name) \
98 _DEFINE_SYSREG_WRITE_FUNC(_name, _name)
99
100/**********************************************************************
101 * Macros to create inline functions for tlbi operations
102 *********************************************************************/
103
Dimitris Papastamos12f8be52017-06-20 09:25:10 +0100104#if ERRATA_A57_813419
105/*
106 * Define function for TLBI instruction with type specifier that
107 * implements the workaround for errata 813419 of Cortex-A57
108 */
Soby Mathewc6820d12016-05-09 17:49:55 +0100109#define _DEFINE_TLBIOP_FUNC(_op, coproc, opc1, CRn, CRm, opc2) \
110static inline void tlbi##_op(void) \
111{ \
112 u_register_t v = 0; \
113 __asm__ volatile ("mcr "#coproc","#opc1",%0,"#CRn","#CRm","#opc2 : : "r" (v));\
Dimitris Papastamos12f8be52017-06-20 09:25:10 +0100114 __asm__ volatile ("dsb ish");\
115 __asm__ volatile ("mcr "#coproc","#opc1",%0,"#CRn","#CRm","#opc2 : : "r" (v));\
Soby Mathewc6820d12016-05-09 17:49:55 +0100116}
117
Dimitris Papastamos12f8be52017-06-20 09:25:10 +0100118#define _DEFINE_TLBIOP_PARAM_FUNC(_op, coproc, opc1, CRn, CRm, opc2) \
119static inline void tlbi##_op(u_register_t v) \
120{ \
121 __asm__ volatile ("mcr "#coproc","#opc1",%0,"#CRn","#CRm","#opc2 : : "r" (v));\
122 __asm__ volatile ("dsb ish");\
123 __asm__ volatile ("mcr "#coproc","#opc1",%0,"#CRn","#CRm","#opc2 : : "r" (v));\
124}
125#else
126#define _DEFINE_TLBIOP_FUNC(_op, coproc, opc1, CRn, CRm, opc2) \
127static inline void tlbi##_op(void) \
Antonio Nino Diazac998032017-02-27 17:23:54 +0000128{ \
129 u_register_t v = 0; \
130 __asm__ volatile ("mcr "#coproc","#opc1",%0,"#CRn","#CRm","#opc2 : : "r" (v));\
131}
132
Soby Mathewc6820d12016-05-09 17:49:55 +0100133#define _DEFINE_TLBIOP_PARAM_FUNC(_op, coproc, opc1, CRn, CRm, opc2) \
134static inline void tlbi##_op(u_register_t v) \
135{ \
136 __asm__ volatile ("mcr "#coproc","#opc1",%0,"#CRn","#CRm","#opc2 : : "r" (v));\
137}
Dimitris Papastamos12f8be52017-06-20 09:25:10 +0100138#endif /* ERRATA_A57_813419 */
139
140#define _DEFINE_BPIOP_FUNC(_op, coproc, opc1, CRn, CRm, opc2) \
141static inline void bpi##_op(void) \
142{ \
143 u_register_t v = 0; \
144 __asm__ volatile ("mcr "#coproc","#opc1",%0,"#CRn","#CRm","#opc2 : : "r" (v));\
145}
Soby Mathewc6820d12016-05-09 17:49:55 +0100146
147/* Define function for simple TLBI operation */
148#define DEFINE_TLBIOP_FUNC(_op, ...) \
149 _DEFINE_TLBIOP_FUNC(_op, __VA_ARGS__)
150
151/* Define function for TLBI operation with register parameter */
152#define DEFINE_TLBIOP_PARAM_FUNC(_op, ...) \
153 _DEFINE_TLBIOP_PARAM_FUNC(_op, __VA_ARGS__)
154
Antonio Nino Diazac998032017-02-27 17:23:54 +0000155/* Define function for simple BPI operation */
156#define DEFINE_BPIOP_FUNC(_op, ...) \
157 _DEFINE_BPIOP_FUNC(_op, __VA_ARGS__)
158
Soby Mathewc6820d12016-05-09 17:49:55 +0100159/**********************************************************************
160 * Macros to create inline functions for DC operations
161 *********************************************************************/
162#define _DEFINE_DCOP_PARAM_FUNC(_op, coproc, opc1, CRn, CRm, opc2) \
163static inline void dc##_op(u_register_t v) \
164{ \
165 __asm__ volatile ("mcr "#coproc","#opc1",%0,"#CRn","#CRm","#opc2 : : "r" (v));\
166}
167
168/* Define function for DC operation with register parameter */
169#define DEFINE_DCOP_PARAM_FUNC(_op, ...) \
170 _DEFINE_DCOP_PARAM_FUNC(_op, __VA_ARGS__)
171
172/**********************************************************************
173 * Macros to create inline functions for system instructions
174 *********************************************************************/
175 /* Define function for simple system instruction */
176#define DEFINE_SYSOP_FUNC(_op) \
177static inline void _op(void) \
178{ \
179 __asm__ (#_op); \
180}
181
182
183/* Define function for system instruction with type specifier */
184#define DEFINE_SYSOP_TYPE_FUNC(_op, _type) \
185static inline void _op ## _type(void) \
186{ \
187 __asm__ (#_op " " #_type); \
188}
189
190/* Define function for system instruction with register parameter */
191#define DEFINE_SYSOP_TYPE_PARAM_FUNC(_op, _type) \
192static inline void _op ## _type(u_register_t v) \
193{ \
194 __asm__ (#_op " " #_type ", %0" : : "r" (v)); \
195}
196
197void flush_dcache_range(uintptr_t addr, size_t size);
198void clean_dcache_range(uintptr_t addr, size_t size);
199void inv_dcache_range(uintptr_t addr, size_t size);
200
Antonio Nino Diaze40306b2017-01-13 15:03:07 +0000201void dcsw_op_louis(u_register_t op_type);
202void dcsw_op_all(u_register_t op_type);
203
Yatharth Kocharf528faf2016-06-28 16:58:26 +0100204void disable_mmu_secure(void);
205void disable_mmu_icache_secure(void);
206
Soby Mathewc6820d12016-05-09 17:49:55 +0100207DEFINE_SYSOP_FUNC(wfi)
208DEFINE_SYSOP_FUNC(wfe)
209DEFINE_SYSOP_FUNC(sev)
210DEFINE_SYSOP_TYPE_FUNC(dsb, sy)
211DEFINE_SYSOP_TYPE_FUNC(dmb, sy)
Yatharth Kochar2694cba2016-11-14 12:00:41 +0000212DEFINE_SYSOP_TYPE_FUNC(dmb, st)
Jeenu Viswambharan1aa2db32018-09-05 14:23:27 +0100213
214/* dmb ld is not valid for armv7/thumb machines */
215#if ARM_ARCH_MAJOR != 7
Yatharth Kochar2694cba2016-11-14 12:00:41 +0000216DEFINE_SYSOP_TYPE_FUNC(dmb, ld)
Jeenu Viswambharan1aa2db32018-09-05 14:23:27 +0100217#endif
218
Soby Mathewc6820d12016-05-09 17:49:55 +0100219DEFINE_SYSOP_TYPE_FUNC(dsb, ish)
Antonio Nino Diazac998032017-02-27 17:23:54 +0000220DEFINE_SYSOP_TYPE_FUNC(dsb, ishst)
Soby Mathewc6820d12016-05-09 17:49:55 +0100221DEFINE_SYSOP_TYPE_FUNC(dmb, ish)
Jeenu Viswambharan62505072017-09-22 08:32:09 +0100222DEFINE_SYSOP_TYPE_FUNC(dmb, ishst)
Soby Mathewc6820d12016-05-09 17:49:55 +0100223DEFINE_SYSOP_FUNC(isb)
224
Yatharth Kocharf528faf2016-06-28 16:58:26 +0100225void __dead2 smc(uint32_t r0, uint32_t r1, uint32_t r2, uint32_t r3,
226 uint32_t r4, uint32_t r5, uint32_t r6, uint32_t r7);
227
Soby Mathewc6820d12016-05-09 17:49:55 +0100228DEFINE_SYSREG_RW_FUNCS(spsr)
229DEFINE_SYSREG_RW_FUNCS(cpsr)
230
231/*******************************************************************************
232 * System register accessor prototypes
233 ******************************************************************************/
234DEFINE_COPROCR_READ_FUNC(mpidr, MPIDR)
235DEFINE_COPROCR_READ_FUNC(midr, MIDR)
Dimitris Papastamosdda48b02017-10-17 14:03:14 +0100236DEFINE_COPROCR_READ_FUNC(id_pfr0, ID_PFR0)
Soby Mathewc6820d12016-05-09 17:49:55 +0100237DEFINE_COPROCR_READ_FUNC(id_pfr1, ID_PFR1)
238DEFINE_COPROCR_READ_FUNC(isr, ISR)
239DEFINE_COPROCR_READ_FUNC(clidr, CLIDR)
240DEFINE_COPROCR_READ_FUNC_64(cntpct, CNTPCT_64)
241
242DEFINE_COPROCR_RW_FUNCS(scr, SCR)
243DEFINE_COPROCR_RW_FUNCS(ctr, CTR)
244DEFINE_COPROCR_RW_FUNCS(sctlr, SCTLR)
Etienne Carriere70a004b2017-11-05 22:56:03 +0100245DEFINE_COPROCR_RW_FUNCS(actlr, ACTLR)
Soby Mathewc6820d12016-05-09 17:49:55 +0100246DEFINE_COPROCR_RW_FUNCS(hsctlr, HSCTLR)
247DEFINE_COPROCR_RW_FUNCS(hcr, HCR)
248DEFINE_COPROCR_RW_FUNCS(hcptr, HCPTR)
249DEFINE_COPROCR_RW_FUNCS(cntfrq, CNTFRQ)
250DEFINE_COPROCR_RW_FUNCS(cnthctl, CNTHCTL)
251DEFINE_COPROCR_RW_FUNCS(mair0, MAIR0)
252DEFINE_COPROCR_RW_FUNCS(mair1, MAIR1)
253DEFINE_COPROCR_RW_FUNCS(ttbcr, TTBCR)
254DEFINE_COPROCR_RW_FUNCS(ttbr0, TTBR0)
255DEFINE_COPROCR_RW_FUNCS_64(ttbr0, TTBR0_64)
256DEFINE_COPROCR_RW_FUNCS(ttbr1, TTBR1)
257DEFINE_COPROCR_RW_FUNCS(vpidr, VPIDR)
258DEFINE_COPROCR_RW_FUNCS(vmpidr, VMPIDR)
259DEFINE_COPROCR_RW_FUNCS_64(vttbr, VTTBR_64)
260DEFINE_COPROCR_RW_FUNCS_64(ttbr1, TTBR1_64)
261DEFINE_COPROCR_RW_FUNCS_64(cntvoff, CNTVOFF_64)
262DEFINE_COPROCR_RW_FUNCS(csselr, CSSELR)
David Cunadofee86532017-04-13 22:38:29 +0100263DEFINE_COPROCR_RW_FUNCS(hstr, HSTR)
Soby Mathewc6820d12016-05-09 17:49:55 +0100264
265DEFINE_COPROCR_RW_FUNCS(icc_sre_el1, ICC_SRE)
266DEFINE_COPROCR_RW_FUNCS(icc_sre_el2, ICC_HSRE)
267DEFINE_COPROCR_RW_FUNCS(icc_sre_el3, ICC_MSRE)
268DEFINE_COPROCR_RW_FUNCS(icc_pmr_el1, ICC_PMR)
Jeenu Viswambharanb1e957e2017-09-22 08:32:09 +0100269DEFINE_COPROCR_RW_FUNCS(icc_rpr_el1, ICC_RPR)
Soby Mathewc6820d12016-05-09 17:49:55 +0100270DEFINE_COPROCR_RW_FUNCS(icc_igrpen1_el3, ICC_MGRPEN1)
271DEFINE_COPROCR_RW_FUNCS(icc_igrpen0_el1, ICC_IGRPEN0)
272DEFINE_COPROCR_RW_FUNCS(icc_hppir0_el1, ICC_HPPIR0)
273DEFINE_COPROCR_RW_FUNCS(icc_hppir1_el1, ICC_HPPIR1)
274DEFINE_COPROCR_RW_FUNCS(icc_iar0_el1, ICC_IAR0)
275DEFINE_COPROCR_RW_FUNCS(icc_iar1_el1, ICC_IAR1)
276DEFINE_COPROCR_RW_FUNCS(icc_eoir0_el1, ICC_EOIR0)
277DEFINE_COPROCR_RW_FUNCS(icc_eoir1_el1, ICC_EOIR1)
Jeenu Viswambharanab14e9b2017-09-22 08:32:09 +0100278DEFINE_COPROCR_RW_FUNCS_64(icc_sgi0r_el1, ICC_SGI0R_EL1_64)
Soby Mathewc6820d12016-05-09 17:49:55 +0100279
David Cunado5f55e282016-10-31 17:37:34 +0000280DEFINE_COPROCR_RW_FUNCS(hdcr, HDCR)
David Cunadoc14b08e2016-11-25 00:21:59 +0000281DEFINE_COPROCR_RW_FUNCS(cnthp_ctl, CNTHP_CTL)
David Cunado5f55e282016-10-31 17:37:34 +0000282DEFINE_COPROCR_READ_FUNC(pmcr, PMCR)
283
Douglas Raillard77414632018-08-21 12:54:45 +0100284DEFINE_COPROCR_RW_FUNCS(ats1cpr, ATS1CPR)
285DEFINE_COPROCR_RW_FUNCS(ats1hr, ATS1HR)
286DEFINE_COPROCR_RW_FUNCS_64(par, PAR_64)
287
Etienne Carriere70a004b2017-11-05 22:56:03 +0100288DEFINE_COPROCR_RW_FUNCS(nsacr, NSACR)
289
290/* AArch32 coproc registers for 32bit MMU descriptor support */
291DEFINE_COPROCR_RW_FUNCS(prrr, PRRR)
292DEFINE_COPROCR_RW_FUNCS(nmrr, NMRR)
293DEFINE_COPROCR_RW_FUNCS(dacr, DACR)
294
Dimitris Papastamosdda48b02017-10-17 14:03:14 +0100295DEFINE_COPROCR_RW_FUNCS(amcntenset0, AMCNTENSET0)
296DEFINE_COPROCR_RW_FUNCS(amcntenset1, AMCNTENSET1)
297DEFINE_COPROCR_RW_FUNCS(amcntenclr0, AMCNTENCLR0)
298DEFINE_COPROCR_RW_FUNCS(amcntenclr1, AMCNTENCLR1)
299
Dimitris Papastamoseaf3e6d2017-11-28 13:47:06 +0000300DEFINE_COPROCR_RW_FUNCS_64(amevcntr00, AMEVCNTR00)
301DEFINE_COPROCR_RW_FUNCS_64(amevcntr01, AMEVCNTR01)
302DEFINE_COPROCR_RW_FUNCS_64(amevcntr02, AMEVCNTR02)
303DEFINE_COPROCR_RW_FUNCS_64(amevcntr03, AMEVCNTR03)
304
Soby Mathewc6820d12016-05-09 17:49:55 +0100305/*
306 * TLBI operation prototypes
307 */
308DEFINE_TLBIOP_FUNC(all, TLBIALL)
309DEFINE_TLBIOP_FUNC(allis, TLBIALLIS)
310DEFINE_TLBIOP_PARAM_FUNC(mva, TLBIMVA)
311DEFINE_TLBIOP_PARAM_FUNC(mvaa, TLBIMVAA)
Antonio Nino Diazac998032017-02-27 17:23:54 +0000312DEFINE_TLBIOP_PARAM_FUNC(mvaais, TLBIMVAAIS)
Antonio Nino Diaz128de8d2018-08-07 19:59:49 +0100313DEFINE_TLBIOP_PARAM_FUNC(mvahis, TLBIMVAHIS)
Antonio Nino Diazac998032017-02-27 17:23:54 +0000314
315/*
316 * BPI operation prototypes.
317 */
318DEFINE_BPIOP_FUNC(allis, BPIALLIS)
Soby Mathewc6820d12016-05-09 17:49:55 +0100319
320/*
321 * DC operation prototypes
322 */
323DEFINE_DCOP_PARAM_FUNC(civac, DCCIMVAC)
324DEFINE_DCOP_PARAM_FUNC(ivac, DCIMVAC)
325DEFINE_DCOP_PARAM_FUNC(cvac, DCCMVAC)
326
327/* Previously defined accessor functions with incomplete register names */
328#define dsb() dsbsy()
Etienne Carrierea2579862017-11-05 22:57:29 +0100329#define dmb() dmbsy()
Soby Mathewc6820d12016-05-09 17:49:55 +0100330
Jeenu Viswambharan1aa2db32018-09-05 14:23:27 +0100331/* dmb ld is not valid for armv7/thumb machines, so alias it to dmb */
332#if ARM_ARCH_MAJOR == 7
333#define dmbld() dmb()
334#endif
335
Soby Mathewc6820d12016-05-09 17:49:55 +0100336#define IS_IN_SECURE() \
337 (GET_NS_BIT(read_scr()) == 0)
338
Antonio Nino Diaz128de8d2018-08-07 19:59:49 +0100339#define IS_IN_HYP() (GET_M32(read_cpsr()) == MODE32_hyp)
340#define IS_IN_SVC() (GET_M32(read_cpsr()) == MODE32_svc)
341#define IS_IN_MON() (GET_M32(read_cpsr()) == MODE32_mon)
342#define IS_IN_EL2() IS_IN_HYP()
Soby Mathewc6820d12016-05-09 17:49:55 +0100343 /*
344 * If EL3 is AArch32, then secure PL1 and monitor mode correspond to EL3
345 */
346#define IS_IN_EL3() \
347 ((GET_M32(read_cpsr()) == MODE32_mon) || \
348 (IS_IN_SECURE() && (GET_M32(read_cpsr()) != MODE32_usr)))
349
Douglas Raillard77414632018-08-21 12:54:45 +0100350static inline unsigned int get_current_el(void)
351{
352 if (IS_IN_EL3()) {
353 return 3U;
354 } else if (IS_IN_EL2()) {
355 return 2U;
356 } else {
357 return 1U;
358 }
359}
360
Soby Mathewc6820d12016-05-09 17:49:55 +0100361/* Macros for compatibility with AArch64 system registers */
362#define read_mpidr_el1() read_mpidr()
363
364#define read_scr_el3() read_scr()
365#define write_scr_el3(_v) write_scr(_v)
366
367#define read_hcr_el2() read_hcr()
368#define write_hcr_el2(_v) write_hcr(_v)
369
370#define read_cpacr_el1() read_cpacr()
371#define write_cpacr_el1(_v) write_cpacr(_v)
372
373#define read_cntfrq_el0() read_cntfrq()
374#define write_cntfrq_el0(_v) write_cntfrq(_v)
375#define read_isr_el1() read_isr()
376
377#define read_cntpct_el0() read64_cntpct()
378
Yatharth Kocharf528faf2016-06-28 16:58:26 +0100379#define read_ctr_el0() read_ctr()
380
Jeenu Viswambharanab14e9b2017-09-22 08:32:09 +0100381#define write_icc_sgi0r_el1(_v) \
382 write64_icc_sgi0r_el1(_v)
383
Soby Mathewc6820d12016-05-09 17:49:55 +0100384#endif /* __ARCH_HELPERS_H__ */