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git01.mediatek.com / filogic / atf / 4c1372c30a0a439827f595cb2ffe9413aa4a8c84 / . / include / lib / cpus / aarch64 / cortex_a78.h
blob: f3cb39f26fbe931b815026b3c2f70699a373f789 [file] [log] [blame]
Louis Mayencourtf57f1082019-05-14 11:00:45 +0100[diff] [blame]1/*
Bipin Ravi86499742022-01-18 01:59:06 -0600[diff] [blame]2 * Copyright (c) 2019-2022, ARM Limited. All rights reserved.
Louis Mayencourtf57f1082019-05-14 11:00:45 +0100[diff] [blame]3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
Jimmy Brisson3571fb92020-06-01 10:18:22 -0500[diff] [blame]7#ifndef CORTEX_A78_H
8#define CORTEX_A78_H
Louis Mayencourtf57f1082019-05-14 11:00:45 +0100[diff] [blame]9
10#include <lib/utils_def.h>
11
Jimmy Brisson3571fb92020-06-01 10:18:22 -0500[diff] [blame]12#define CORTEX_A78_MIDR U(0x410FD410)
Louis Mayencourtf57f1082019-05-14 11:00:45 +0100[diff] [blame]13
Bipin Ravi86499742022-01-18 01:59:06 -0600[diff] [blame]14/* Cortex-A78 loop count for CVE-2022-23960 mitigation */
15#define CORTEX_A78_BHB_LOOP_COUNT U(32)
16
Louis Mayencourtf57f1082019-05-14 11:00:45 +0100[diff] [blame]17/*******************************************************************************
18 * CPU Extended Control register specific definitions.
19 ******************************************************************************/
Jimmy Brisson3571fb92020-06-01 10:18:22 -0500[diff] [blame]20#define CORTEX_A78_CPUECTLR_EL1 S3_0_C15_C1_4
johpow019131eb82020-10-06 17:55:25 -0500[diff] [blame]21#define CORTEX_A78_CPUECTLR_EL1_BIT_8 (ULL(1) << 8)
nayanpatel-arm39e08652021-09-28 17:31:50 -0700[diff] [blame]22#define CORTEX_A78_CPUECTLR_EL1_PF_MODE_CNSRV ULL(3)
23#define CPUECTLR_EL1_PF_MODE_LSB U(6)
24#define CPUECTLR_EL1_PF_MODE_WIDTH U(2)
Louis Mayencourtf57f1082019-05-14 11:00:45 +0100[diff] [blame]25
26/*******************************************************************************
27 * CPU Power Control register specific definitions
28 ******************************************************************************/
johpow019131eb82020-10-06 17:55:25 -0500[diff] [blame]29#define CORTEX_A78_CPUPWRCTLR_EL1 S3_0_C15_C2_7
Jimmy Brisson3571fb92020-06-01 10:18:22 -0500[diff] [blame]30#define CORTEX_A78_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT U(1)
Louis Mayencourtf57f1082019-05-14 11:00:45 +0100[diff] [blame]31
Balint Dobszaydb2ec852019-07-15 11:46:20 +0200[diff] [blame]32/*******************************************************************************
33 * CPU Auxiliary Control register specific definitions.
34 ******************************************************************************/
johpow019131eb82020-10-06 17:55:25 -0500[diff] [blame]35#define CORTEX_A78_ACTLR_TAM_BIT (ULL(1) << 30)
Balint Dobszaydb2ec852019-07-15 11:46:20 +0200[diff] [blame]36
Jimmy Brisson3571fb92020-06-01 10:18:22 -0500[diff] [blame]37#define CORTEX_A78_ACTLR2_EL1 S3_0_C15_C1_1
38#define CORTEX_A78_ACTLR2_EL1_BIT_1 (ULL(1) << 1)
johpow01b3e82942021-04-30 18:08:52 -0500[diff] [blame]39#define CORTEX_A78_ACTLR2_EL1_BIT_2 (ULL(1) << 2)
Madhukar Pappireddy4efede72019-12-18 15:56:27 -0600[diff] [blame]40
Balint Dobszaydb2ec852019-07-15 11:46:20 +0200[diff] [blame]41/*******************************************************************************
42 * CPU Activity Monitor Unit register specific definitions.
43 ******************************************************************************/
johpow019131eb82020-10-06 17:55:25 -0500[diff] [blame]44#define CPUAMCNTENCLR0_EL0 S3_3_C15_C2_4
45#define CPUAMCNTENSET0_EL0 S3_3_C15_C2_5
46#define CPUAMCNTENCLR1_EL0 S3_3_C15_C3_0
47#define CPUAMCNTENSET1_EL0 S3_3_C15_C3_1
Balint Dobszaydb2ec852019-07-15 11:46:20 +0200[diff] [blame]48
johpow019131eb82020-10-06 17:55:25 -0500[diff] [blame]49#define CORTEX_A78_AMU_GROUP0_MASK U(0xF)
50#define CORTEX_A78_AMU_GROUP1_MASK U(0x7)
Balint Dobszaydb2ec852019-07-15 11:46:20 +0200[diff] [blame]51
Jimmy Brisson3571fb92020-06-01 10:18:22 -0500[diff] [blame]52#endif /* CORTEX_A78_H */