| Roberto Vargas | e0e9946 | 2017-10-30 14:43:43 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #include <arch.h> |
| 8 | #include <asm_macros.S> |
| Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 9 | #include <common/bl_common.h> |
| Roberto Vargas | e0e9946 | 2017-10-30 14:43:43 +0000 | [diff] [blame] | 10 | #include <el3_common_macros.S> |
| 11 | |
| Roberto Vargas | e0e9946 | 2017-10-30 14:43:43 +0000 | [diff] [blame] | 12 | .globl bl2_entrypoint |
| 13 | .globl bl2_run_next_image |
| 14 | |
| 15 | |
| 16 | func bl2_entrypoint |
| 17 | /* Save arguments x0-x3 from previous Boot loader */ |
| 18 | mov r9, r0 |
| 19 | mov r10, r1 |
| 20 | mov r11, r2 |
| 21 | mov r12, r3 |
| 22 | |
| 23 | el3_entrypoint_common \ |
| 24 | _init_sctlr=1 \ |
| 25 | _warm_boot_mailbox=!PROGRAMMABLE_RESET_ADDRESS \ |
| 26 | _secondary_cold_boot=!COLD_BOOT_SINGLE_CPU \ |
| 27 | _init_memory=1 \ |
| 28 | _init_c_runtime=1 \ |
| 29 | _exception_vectors=bl2_vector_table |
| 30 | |
| 31 | /* |
| 32 | * Restore parameters of boot rom |
| 33 | */ |
| 34 | mov r0, r9 |
| 35 | mov r1, r10 |
| 36 | mov r2, r11 |
| 37 | mov r3, r12 |
| 38 | |
| 39 | bl bl2_el3_early_platform_setup |
| 40 | bl bl2_el3_plat_arch_setup |
| 41 | |
| 42 | /* --------------------------------------------- |
| 43 | * Jump to main function. |
| 44 | * --------------------------------------------- |
| 45 | */ |
| 46 | bl bl2_main |
| 47 | |
| 48 | /* --------------------------------------------- |
| 49 | * Should never reach this point. |
| 50 | * --------------------------------------------- |
| 51 | */ |
| 52 | no_ret plat_panic_handler |
| 53 | |
| 54 | endfunc bl2_entrypoint |
| 55 | |
| 56 | func bl2_run_next_image |
| 57 | mov r8,r0 |
| 58 | |
| 59 | /* |
| 60 | * MMU needs to be disabled because both BL2 and BL32 execute |
| 61 | * in PL1, and therefore share the same address space. |
| 62 | * BL32 will initialize the address space according to its |
| 63 | * own requirement. |
| 64 | */ |
| 65 | bl disable_mmu_icache_secure |
| 66 | stcopr r0, TLBIALL |
| 67 | dsb sy |
| 68 | isb |
| 69 | mov r0, r8 |
| 70 | bl bl2_el3_plat_prepare_exit |
| 71 | |
| 72 | /* |
| 73 | * Extract PC and SPSR based on struct `entry_point_info_t` |
| 74 | * and load it in LR and SPSR registers respectively. |
| 75 | */ |
| 76 | ldr lr, [r8, #ENTRY_POINT_INFO_PC_OFFSET] |
| 77 | ldr r1, [r8, #(ENTRY_POINT_INFO_PC_OFFSET + 4)] |
| 78 | msr spsr, r1 |
| 79 | |
| Lionel Debieve | 6a89754 | 2018-03-05 15:21:59 +0100 | [diff] [blame] | 80 | /* Some BL32 stages expect lr_svc to provide the BL33 entry address */ |
| 81 | cps #MODE32_svc |
| 82 | ldr lr, [r8, #ENTRY_POINT_INFO_LR_SVC_OFFSET] |
| 83 | cps #MODE32_mon |
| 84 | |
| Roberto Vargas | e0e9946 | 2017-10-30 14:43:43 +0000 | [diff] [blame] | 85 | add r8, r8, #ENTRY_POINT_INFO_ARGS_OFFSET |
| 86 | ldm r8, {r0, r1, r2, r3} |
| 87 | eret |
| 88 | endfunc bl2_run_next_image |