Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 1 | /* |
Jonathan Wright | efb1f33 | 2018-03-28 15:52:03 +0100 | [diff] [blame] | 2 | * Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved. |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 3 | * |
dp-arm | fa3cf0b | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 4 | * SPDX-License-Identifier: BSD-3-Clause |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 5 | */ |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 6 | #include <arch.h> |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 7 | #include <asm_macros.S> |
Yatharth Kochar | 36433d1 | 2014-11-20 18:09:41 +0000 | [diff] [blame] | 8 | #include <bl_common.h> |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 9 | #include <cortex_a53.h> |
Soby Mathew | c704cbc | 2014-08-14 11:33:56 +0100 | [diff] [blame] | 10 | #include <cpu_macros.S> |
Soby Mathew | 6b28c57 | 2016-03-21 10:36:47 +0000 | [diff] [blame] | 11 | #include <debug.h> |
Jonathan Wright | efb1f33 | 2018-03-28 15:52:03 +0100 | [diff] [blame] | 12 | #include <errata_report.h> |
Soby Mathew | c704cbc | 2014-08-14 11:33:56 +0100 | [diff] [blame] | 13 | #include <plat_macros.S> |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 14 | |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 15 | #if A53_DISABLE_NON_TEMPORAL_HINT |
| 16 | #undef ERRATA_A53_836870 |
| 17 | #define ERRATA_A53_836870 1 |
| 18 | #endif |
| 19 | |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 20 | /* --------------------------------------------- |
| 21 | * Disable L1 data cache and unified L2 cache |
| 22 | * --------------------------------------------- |
| 23 | */ |
| 24 | func cortex_a53_disable_dcache |
| 25 | mrs x1, sctlr_el3 |
| 26 | bic x1, x1, #SCTLR_C_BIT |
| 27 | msr sctlr_el3, x1 |
| 28 | isb |
| 29 | ret |
Kévin Petit | a877c25 | 2015-03-24 14:03:57 +0000 | [diff] [blame] | 30 | endfunc cortex_a53_disable_dcache |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 31 | |
| 32 | /* --------------------------------------------- |
| 33 | * Disable intra-cluster coherency |
| 34 | * --------------------------------------------- |
| 35 | */ |
| 36 | func cortex_a53_disable_smp |
Varun Wadekar | 1384a16 | 2017-06-05 14:54:46 -0700 | [diff] [blame] | 37 | mrs x0, CORTEX_A53_ECTLR_EL1 |
| 38 | bic x0, x0, #CORTEX_A53_ECTLR_SMP_BIT |
| 39 | msr CORTEX_A53_ECTLR_EL1, x0 |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 40 | isb |
| 41 | dsb sy |
| 42 | ret |
Kévin Petit | a877c25 | 2015-03-24 14:03:57 +0000 | [diff] [blame] | 43 | endfunc cortex_a53_disable_smp |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 44 | |
developer | 4fceaca | 2015-07-29 20:55:31 +0800 | [diff] [blame] | 45 | /* -------------------------------------------------- |
| 46 | * Errata Workaround for Cortex A53 Errata #826319. |
| 47 | * This applies only to revision <= r0p2 of Cortex A53. |
| 48 | * Inputs: |
| 49 | * x0: variant[4:7] and revision[0:3] of current cpu. |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 50 | * Shall clobber: x0-x17 |
developer | 4fceaca | 2015-07-29 20:55:31 +0800 | [diff] [blame] | 51 | * -------------------------------------------------- |
| 52 | */ |
| 53 | func errata_a53_826319_wa |
| 54 | /* |
| 55 | * Compare x0 against revision r0p2 |
| 56 | */ |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 57 | mov x17, x30 |
| 58 | bl check_errata_826319 |
| 59 | cbz x0, 1f |
Varun Wadekar | 1384a16 | 2017-06-05 14:54:46 -0700 | [diff] [blame] | 60 | mrs x1, CORTEX_A53_L2ACTLR_EL1 |
| 61 | bic x1, x1, #CORTEX_A53_L2ACTLR_ENABLE_UNIQUECLEAN |
| 62 | orr x1, x1, #CORTEX_A53_L2ACTLR_DISABLE_CLEAN_PUSH |
| 63 | msr CORTEX_A53_L2ACTLR_EL1, x1 |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 64 | 1: |
| 65 | ret x17 |
developer | 4fceaca | 2015-07-29 20:55:31 +0800 | [diff] [blame] | 66 | endfunc errata_a53_826319_wa |
| 67 | |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 68 | func check_errata_826319 |
| 69 | mov x1, #0x02 |
| 70 | b cpu_rev_var_ls |
| 71 | endfunc check_errata_826319 |
| 72 | |
Sandrine Bailleux | d481759 | 2016-01-13 14:57:38 +0000 | [diff] [blame] | 73 | /* --------------------------------------------------------------------- |
| 74 | * Disable the cache non-temporal hint. |
| 75 | * |
| 76 | * This ignores the Transient allocation hint in the MAIR and treats |
| 77 | * allocations the same as non-transient allocation types. As a result, |
| 78 | * the LDNP and STNP instructions in AArch64 behave the same as the |
| 79 | * equivalent LDP and STP instructions. |
| 80 | * |
| 81 | * This is relevant only for revisions <= r0p3 of Cortex-A53. |
| 82 | * From r0p4 and onwards, the bit to disable the hint is enabled by |
| 83 | * default at reset. |
| 84 | * |
developer | 4fceaca | 2015-07-29 20:55:31 +0800 | [diff] [blame] | 85 | * Inputs: |
| 86 | * x0: variant[4:7] and revision[0:3] of current cpu. |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 87 | * Shall clobber: x0-x17 |
Sandrine Bailleux | d481759 | 2016-01-13 14:57:38 +0000 | [diff] [blame] | 88 | * --------------------------------------------------------------------- |
developer | 4fceaca | 2015-07-29 20:55:31 +0800 | [diff] [blame] | 89 | */ |
Sandrine Bailleux | d481759 | 2016-01-13 14:57:38 +0000 | [diff] [blame] | 90 | func a53_disable_non_temporal_hint |
developer | 4fceaca | 2015-07-29 20:55:31 +0800 | [diff] [blame] | 91 | /* |
| 92 | * Compare x0 against revision r0p3 |
| 93 | */ |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 94 | mov x17, x30 |
| 95 | bl check_errata_disable_non_temporal_hint |
| 96 | cbz x0, 1f |
Eleanor Bonnici | 41b61be | 2017-08-09 16:42:40 +0100 | [diff] [blame] | 97 | mrs x1, CORTEX_A53_CPUACTLR_EL1 |
| 98 | orr x1, x1, #CORTEX_A53_CPUACTLR_EL1_DTAH |
| 99 | msr CORTEX_A53_CPUACTLR_EL1, x1 |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 100 | 1: |
| 101 | ret x17 |
Sandrine Bailleux | d481759 | 2016-01-13 14:57:38 +0000 | [diff] [blame] | 102 | endfunc a53_disable_non_temporal_hint |
developer | 4fceaca | 2015-07-29 20:55:31 +0800 | [diff] [blame] | 103 | |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 104 | func check_errata_disable_non_temporal_hint |
| 105 | mov x1, #0x03 |
| 106 | b cpu_rev_var_ls |
| 107 | endfunc check_errata_disable_non_temporal_hint |
| 108 | |
Andre Przywara | 00eefd9 | 2016-10-06 16:54:53 +0100 | [diff] [blame] | 109 | /* -------------------------------------------------- |
| 110 | * Errata Workaround for Cortex A53 Errata #855873. |
| 111 | * |
| 112 | * This applies only to revisions >= r0p3 of Cortex A53. |
| 113 | * Earlier revisions of the core are affected as well, but don't |
| 114 | * have the chicken bit in the CPUACTLR register. It is expected that |
| 115 | * the rich OS takes care of that, especially as the workaround is |
| 116 | * shared with other erratas in those revisions of the CPU. |
| 117 | * Inputs: |
| 118 | * x0: variant[4:7] and revision[0:3] of current cpu. |
| 119 | * Shall clobber: x0-x17 |
| 120 | * -------------------------------------------------- |
| 121 | */ |
| 122 | func errata_a53_855873_wa |
| 123 | /* |
| 124 | * Compare x0 against revision r0p3 and higher |
| 125 | */ |
| 126 | mov x17, x30 |
| 127 | bl check_errata_855873 |
| 128 | cbz x0, 1f |
| 129 | |
Eleanor Bonnici | 41b61be | 2017-08-09 16:42:40 +0100 | [diff] [blame] | 130 | mrs x1, CORTEX_A53_CPUACTLR_EL1 |
| 131 | orr x1, x1, #CORTEX_A53_CPUACTLR_EL1_ENDCCASCI |
| 132 | msr CORTEX_A53_CPUACTLR_EL1, x1 |
Andre Przywara | 00eefd9 | 2016-10-06 16:54:53 +0100 | [diff] [blame] | 133 | 1: |
| 134 | ret x17 |
| 135 | endfunc errata_a53_855873_wa |
| 136 | |
| 137 | func check_errata_855873 |
| 138 | mov x1, #0x03 |
| 139 | b cpu_rev_var_hs |
| 140 | endfunc check_errata_855873 |
| 141 | |
Douglas Raillard | d56fb04 | 2017-06-19 15:38:02 +0100 | [diff] [blame] | 142 | /* |
| 143 | * Errata workaround for Cortex A53 Errata #835769. |
| 144 | * This applies to revisions <= r0p4 of Cortex A53. |
| 145 | * This workaround is statically enabled at build time. |
| 146 | */ |
| 147 | func check_errata_835769 |
Jonathan Wright | 6e1796e | 2018-03-28 16:55:54 +0100 | [diff] [blame] | 148 | cmp x0, #0x04 |
| 149 | b.hi errata_not_applies |
| 150 | /* |
| 151 | * Fix potentially available for revisions r0p2, r0p3 and r0p4. |
| 152 | * If r0p2, r0p3 or r0p4; check for fix in REVIDR, else exit. |
| 153 | */ |
| 154 | cmp x0, #0x01 |
| 155 | mov x0, #ERRATA_APPLIES |
| 156 | b.ls exit_check_errata_835769 |
| 157 | /* Load REVIDR. */ |
| 158 | mrs x1, revidr_el1 |
| 159 | /* If REVIDR[7] is set (fix exists) set ERRATA_NOT_APPLIES, else exit. */ |
| 160 | tbz x1, #7, exit_check_errata_835769 |
| 161 | errata_not_applies: |
| 162 | mov x0, #ERRATA_NOT_APPLIES |
| 163 | exit_check_errata_835769: |
| 164 | ret |
Douglas Raillard | d56fb04 | 2017-06-19 15:38:02 +0100 | [diff] [blame] | 165 | endfunc check_errata_835769 |
| 166 | |
| 167 | /* |
| 168 | * Errata workaround for Cortex A53 Errata #843419. |
| 169 | * This applies to revisions <= r0p4 of Cortex A53. |
| 170 | * This workaround is statically enabled at build time. |
| 171 | */ |
| 172 | func check_errata_843419 |
Jonathan Wright | efb1f33 | 2018-03-28 15:52:03 +0100 | [diff] [blame] | 173 | mov x1, #ERRATA_APPLIES |
| 174 | mov x2, #ERRATA_NOT_APPLIES |
| 175 | cmp x0, #0x04 |
| 176 | csel x0, x1, x2, ls |
| 177 | /* |
| 178 | * Fix potentially available for revision r0p4. |
| 179 | * If r0p4 check for fix in REVIDR, else exit. |
| 180 | */ |
| 181 | b.ne exit_check_errata_843419 |
| 182 | /* Load REVIDR. */ |
| 183 | mrs x3, revidr_el1 |
| 184 | /* If REVIDR[8] is set (fix exists) set ERRATA_NOT_APPLIES, else exit. */ |
| 185 | tbz x3, #8, exit_check_errata_843419 |
| 186 | mov x0, x2 |
| 187 | exit_check_errata_843419: |
| 188 | ret |
Douglas Raillard | d56fb04 | 2017-06-19 15:38:02 +0100 | [diff] [blame] | 189 | endfunc check_errata_843419 |
| 190 | |
developer | 4fceaca | 2015-07-29 20:55:31 +0800 | [diff] [blame] | 191 | /* ------------------------------------------------- |
| 192 | * The CPU Ops reset function for Cortex-A53. |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 193 | * Shall clobber: x0-x19 |
developer | 4fceaca | 2015-07-29 20:55:31 +0800 | [diff] [blame] | 194 | * ------------------------------------------------- |
| 195 | */ |
Soby Mathew | c704cbc | 2014-08-14 11:33:56 +0100 | [diff] [blame] | 196 | func cortex_a53_reset_func |
developer | 4fceaca | 2015-07-29 20:55:31 +0800 | [diff] [blame] | 197 | mov x19, x30 |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 198 | bl cpu_get_rev_var |
| 199 | mov x18, x0 |
developer | 4fceaca | 2015-07-29 20:55:31 +0800 | [diff] [blame] | 200 | |
developer | 4fceaca | 2015-07-29 20:55:31 +0800 | [diff] [blame] | 201 | |
| 202 | #if ERRATA_A53_826319 |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 203 | mov x0, x18 |
developer | 4fceaca | 2015-07-29 20:55:31 +0800 | [diff] [blame] | 204 | bl errata_a53_826319_wa |
| 205 | #endif |
| 206 | |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 207 | #if ERRATA_A53_836870 |
| 208 | mov x0, x18 |
Sandrine Bailleux | d481759 | 2016-01-13 14:57:38 +0000 | [diff] [blame] | 209 | bl a53_disable_non_temporal_hint |
developer | 4fceaca | 2015-07-29 20:55:31 +0800 | [diff] [blame] | 210 | #endif |
| 211 | |
Andre Przywara | 00eefd9 | 2016-10-06 16:54:53 +0100 | [diff] [blame] | 212 | #if ERRATA_A53_855873 |
| 213 | mov x0, x18 |
| 214 | bl errata_a53_855873_wa |
| 215 | #endif |
| 216 | |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 217 | /* --------------------------------------------- |
Sandrine Bailleux | f12a31d | 2016-01-29 14:37:58 +0000 | [diff] [blame] | 218 | * Enable the SMP bit. |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 219 | * --------------------------------------------- |
| 220 | */ |
Varun Wadekar | 1384a16 | 2017-06-05 14:54:46 -0700 | [diff] [blame] | 221 | mrs x0, CORTEX_A53_ECTLR_EL1 |
| 222 | orr x0, x0, #CORTEX_A53_ECTLR_SMP_BIT |
| 223 | msr CORTEX_A53_ECTLR_EL1, x0 |
developer | 4fceaca | 2015-07-29 20:55:31 +0800 | [diff] [blame] | 224 | isb |
| 225 | ret x19 |
Kévin Petit | a877c25 | 2015-03-24 14:03:57 +0000 | [diff] [blame] | 226 | endfunc cortex_a53_reset_func |
Soby Mathew | c704cbc | 2014-08-14 11:33:56 +0100 | [diff] [blame] | 227 | |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 228 | func cortex_a53_core_pwr_dwn |
| 229 | mov x18, x30 |
| 230 | |
Andrew F. Davis | 7c461d7 | 2018-10-12 15:37:04 -0500 | [diff] [blame] | 231 | #if !TI_AM65X_WORKAROUND |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 232 | /* --------------------------------------------- |
| 233 | * Turn off caches. |
| 234 | * --------------------------------------------- |
| 235 | */ |
| 236 | bl cortex_a53_disable_dcache |
Andrew F. Davis | 7c461d7 | 2018-10-12 15:37:04 -0500 | [diff] [blame] | 237 | #endif |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 238 | |
| 239 | /* --------------------------------------------- |
Soby Mathew | 42aa5eb | 2014-09-02 10:47:33 +0100 | [diff] [blame] | 240 | * Flush L1 caches. |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 241 | * --------------------------------------------- |
| 242 | */ |
| 243 | mov x0, #DCCISW |
Soby Mathew | 42aa5eb | 2014-09-02 10:47:33 +0100 | [diff] [blame] | 244 | bl dcsw_op_level1 |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 245 | |
| 246 | /* --------------------------------------------- |
| 247 | * Come out of intra cluster coherency |
| 248 | * --------------------------------------------- |
| 249 | */ |
| 250 | mov x30, x18 |
| 251 | b cortex_a53_disable_smp |
Kévin Petit | a877c25 | 2015-03-24 14:03:57 +0000 | [diff] [blame] | 252 | endfunc cortex_a53_core_pwr_dwn |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 253 | |
| 254 | func cortex_a53_cluster_pwr_dwn |
| 255 | mov x18, x30 |
| 256 | |
Andrew F. Davis | 7c461d7 | 2018-10-12 15:37:04 -0500 | [diff] [blame] | 257 | #if !TI_AM65X_WORKAROUND |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 258 | /* --------------------------------------------- |
| 259 | * Turn off caches. |
| 260 | * --------------------------------------------- |
| 261 | */ |
| 262 | bl cortex_a53_disable_dcache |
Andrew F. Davis | 7c461d7 | 2018-10-12 15:37:04 -0500 | [diff] [blame] | 263 | #endif |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 264 | |
| 265 | /* --------------------------------------------- |
Soby Mathew | 42aa5eb | 2014-09-02 10:47:33 +0100 | [diff] [blame] | 266 | * Flush L1 caches. |
| 267 | * --------------------------------------------- |
| 268 | */ |
| 269 | mov x0, #DCCISW |
| 270 | bl dcsw_op_level1 |
| 271 | |
| 272 | /* --------------------------------------------- |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 273 | * Disable the optional ACP. |
| 274 | * --------------------------------------------- |
| 275 | */ |
| 276 | bl plat_disable_acp |
| 277 | |
| 278 | /* --------------------------------------------- |
Soby Mathew | 42aa5eb | 2014-09-02 10:47:33 +0100 | [diff] [blame] | 279 | * Flush L2 caches. |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 280 | * --------------------------------------------- |
| 281 | */ |
| 282 | mov x0, #DCCISW |
Soby Mathew | 42aa5eb | 2014-09-02 10:47:33 +0100 | [diff] [blame] | 283 | bl dcsw_op_level2 |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 284 | |
| 285 | /* --------------------------------------------- |
| 286 | * Come out of intra cluster coherency |
| 287 | * --------------------------------------------- |
| 288 | */ |
| 289 | mov x30, x18 |
| 290 | b cortex_a53_disable_smp |
Kévin Petit | a877c25 | 2015-03-24 14:03:57 +0000 | [diff] [blame] | 291 | endfunc cortex_a53_cluster_pwr_dwn |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 292 | |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 293 | #if REPORT_ERRATA |
| 294 | /* |
| 295 | * Errata printing function for Cortex A53. Must follow AAPCS. |
| 296 | */ |
| 297 | func cortex_a53_errata_report |
| 298 | stp x8, x30, [sp, #-16]! |
| 299 | |
| 300 | bl cpu_get_rev_var |
| 301 | mov x8, x0 |
| 302 | |
| 303 | /* |
| 304 | * Report all errata. The revision-variant information is passed to |
| 305 | * checking functions of each errata. |
| 306 | */ |
| 307 | report_errata ERRATA_A53_826319, cortex_a53, 826319 |
Douglas Raillard | d56fb04 | 2017-06-19 15:38:02 +0100 | [diff] [blame] | 308 | report_errata ERRATA_A53_835769, cortex_a53, 835769 |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 309 | report_errata ERRATA_A53_836870, cortex_a53, disable_non_temporal_hint |
Douglas Raillard | d56fb04 | 2017-06-19 15:38:02 +0100 | [diff] [blame] | 310 | report_errata ERRATA_A53_843419, cortex_a53, 843419 |
Andre Przywara | 00eefd9 | 2016-10-06 16:54:53 +0100 | [diff] [blame] | 311 | report_errata ERRATA_A53_855873, cortex_a53, 855873 |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 312 | |
| 313 | ldp x8, x30, [sp], #16 |
| 314 | ret |
| 315 | endfunc cortex_a53_errata_report |
| 316 | #endif |
| 317 | |
Soby Mathew | 38b4bc9 | 2014-08-14 13:36:41 +0100 | [diff] [blame] | 318 | /* --------------------------------------------- |
| 319 | * This function provides cortex_a53 specific |
| 320 | * register information for crash reporting. |
| 321 | * It needs to return with x6 pointing to |
| 322 | * a list of register names in ascii and |
| 323 | * x8 - x15 having values of registers to be |
| 324 | * reported. |
| 325 | * --------------------------------------------- |
| 326 | */ |
| 327 | .section .rodata.cortex_a53_regs, "aS" |
| 328 | cortex_a53_regs: /* The ascii list of register names to be reported */ |
Andre Przywara | 00eefd9 | 2016-10-06 16:54:53 +0100 | [diff] [blame] | 329 | .asciz "cpuectlr_el1", "cpumerrsr_el1", "l2merrsr_el1", \ |
| 330 | "cpuactlr_el1", "" |
Soby Mathew | 38b4bc9 | 2014-08-14 13:36:41 +0100 | [diff] [blame] | 331 | |
| 332 | func cortex_a53_cpu_reg_dump |
| 333 | adr x6, cortex_a53_regs |
Varun Wadekar | 1384a16 | 2017-06-05 14:54:46 -0700 | [diff] [blame] | 334 | mrs x8, CORTEX_A53_ECTLR_EL1 |
| 335 | mrs x9, CORTEX_A53_MERRSR_EL1 |
| 336 | mrs x10, CORTEX_A53_L2MERRSR_EL1 |
Eleanor Bonnici | 41b61be | 2017-08-09 16:42:40 +0100 | [diff] [blame] | 337 | mrs x11, CORTEX_A53_CPUACTLR_EL1 |
Soby Mathew | 38b4bc9 | 2014-08-14 13:36:41 +0100 | [diff] [blame] | 338 | ret |
Kévin Petit | a877c25 | 2015-03-24 14:03:57 +0000 | [diff] [blame] | 339 | endfunc cortex_a53_cpu_reg_dump |
Soby Mathew | 38b4bc9 | 2014-08-14 13:36:41 +0100 | [diff] [blame] | 340 | |
Jeenu Viswambharan | ee5eb80 | 2016-11-18 12:58:28 +0000 | [diff] [blame] | 341 | declare_cpu_ops cortex_a53, CORTEX_A53_MIDR, \ |
| 342 | cortex_a53_reset_func, \ |
| 343 | cortex_a53_core_pwr_dwn, \ |
| 344 | cortex_a53_cluster_pwr_dwn |