ti: k3: common: Do not disable cache on TI K3 core powerdown
Leave the caches on and explicitly flush any data that
may be stale when the core is powered down. This prevents
non-coherent interconnect access which has negative side-
effects on AM65x.
Signed-off-by: Andrew F. Davis <afd@ti.com>
diff --git a/lib/cpus/aarch64/cortex_a53.S b/lib/cpus/aarch64/cortex_a53.S
index 3a23e02..108509f 100644
--- a/lib/cpus/aarch64/cortex_a53.S
+++ b/lib/cpus/aarch64/cortex_a53.S
@@ -228,11 +228,13 @@
func cortex_a53_core_pwr_dwn
mov x18, x30
+#if !TI_AM65X_WORKAROUND
/* ---------------------------------------------
* Turn off caches.
* ---------------------------------------------
*/
bl cortex_a53_disable_dcache
+#endif
/* ---------------------------------------------
* Flush L1 caches.
@@ -252,11 +254,13 @@
func cortex_a53_cluster_pwr_dwn
mov x18, x30
+#if !TI_AM65X_WORKAROUND
/* ---------------------------------------------
* Turn off caches.
* ---------------------------------------------
*/
bl cortex_a53_disable_dcache
+#endif
/* ---------------------------------------------
* Flush L1 caches.