Varun Wadekar | cd5a2f5 | 2015-09-20 15:08:22 +0530 | [diff] [blame] | 1 | /* |
Harvey Hsieh | b9b374f | 2016-11-15 22:04:51 +0800 | [diff] [blame] | 2 | * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. |
Varun Wadekar | cd5a2f5 | 2015-09-20 15:08:22 +0530 | [diff] [blame] | 3 | * |
dp-arm | fa3cf0b | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 4 | * SPDX-License-Identifier: BSD-3-Clause |
Varun Wadekar | cd5a2f5 | 2015-09-20 15:08:22 +0530 | [diff] [blame] | 5 | */ |
| 6 | |
Varun Wadekar | cd5a2f5 | 2015-09-20 15:08:22 +0530 | [diff] [blame] | 7 | #include <assert.h> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 8 | #include <string.h> |
| 9 | |
| 10 | #include <arch_helpers.h> |
| 11 | #include <common/bl_common.h> |
| 12 | #include <common/debug.h> |
| 13 | #include <lib/mmio.h> |
| 14 | #include <lib/utils.h> |
| 15 | #include <lib/xlat_tables/xlat_tables_v2.h> |
| 16 | |
Varun Wadekar | cd5a2f5 | 2015-09-20 15:08:22 +0530 | [diff] [blame] | 17 | #include <mce.h> |
| 18 | #include <memctrl.h> |
| 19 | #include <memctrl_v2.h> |
Varun Wadekar | 87e44ff | 2016-03-03 13:22:39 -0800 | [diff] [blame] | 20 | #include <smmu.h> |
Varun Wadekar | cd5a2f5 | 2015-09-20 15:08:22 +0530 | [diff] [blame] | 21 | #include <tegra_def.h> |
Varun Wadekar | e81177d | 2016-07-18 17:43:41 -0700 | [diff] [blame] | 22 | #include <tegra_platform.h> |
Varun Wadekar | cd5a2f5 | 2015-09-20 15:08:22 +0530 | [diff] [blame] | 23 | |
| 24 | /* Video Memory base and size (live values) */ |
| 25 | static uint64_t video_mem_base; |
Varun Wadekar | 7058aee | 2016-04-25 09:01:46 -0700 | [diff] [blame] | 26 | static uint64_t video_mem_size_mb; |
Varun Wadekar | cd5a2f5 | 2015-09-20 15:08:22 +0530 | [diff] [blame] | 27 | |
Varun Wadekar | a0f2697 | 2016-03-11 17:18:51 -0800 | [diff] [blame] | 28 | static void tegra_memctrl_reconfig_mss_clients(void) |
| 29 | { |
| 30 | #if ENABLE_ROC_FOR_ORDERING_CLIENT_REQUESTS |
| 31 | uint32_t val, wdata_0, wdata_1; |
| 32 | |
| 33 | /* |
| 34 | * Assert Memory Controller's HOTRESET_FLUSH_ENABLE signal for |
| 35 | * boot and strongly ordered MSS clients to flush existing memory |
| 36 | * traffic and stall future requests. |
| 37 | */ |
| 38 | val = tegra_mc_read_32(MC_CLIENT_HOTRESET_CTRL0); |
| 39 | assert(val == MC_CLIENT_HOTRESET_CTRL0_RESET_VAL); |
| 40 | |
Varun Wadekar | 4c7fa50 | 2016-12-13 13:13:42 -0800 | [diff] [blame] | 41 | wdata_0 = MC_CLIENT_HOTRESET_CTRL0_HDA_FLUSH_ENB | |
| 42 | #if ENABLE_AFI_DEVICE |
| 43 | MC_CLIENT_HOTRESET_CTRL0_AFI_FLUSH_ENB | |
| 44 | #endif |
Varun Wadekar | a0f2697 | 2016-03-11 17:18:51 -0800 | [diff] [blame] | 45 | MC_CLIENT_HOTRESET_CTRL0_SATA_FLUSH_ENB | |
| 46 | MC_CLIENT_HOTRESET_CTRL0_XUSB_HOST_FLUSH_ENB | |
| 47 | MC_CLIENT_HOTRESET_CTRL0_XUSB_DEV_FLUSH_ENB; |
| 48 | tegra_mc_write_32(MC_CLIENT_HOTRESET_CTRL0, wdata_0); |
| 49 | |
| 50 | /* Wait for HOTRESET STATUS to indicate FLUSH_DONE */ |
| 51 | do { |
| 52 | val = tegra_mc_read_32(MC_CLIENT_HOTRESET_STATUS0); |
| 53 | } while ((val & wdata_0) != wdata_0); |
| 54 | |
| 55 | /* Wait one more time due to SW WAR for known legacy issue */ |
| 56 | do { |
| 57 | val = tegra_mc_read_32(MC_CLIENT_HOTRESET_STATUS0); |
| 58 | } while ((val & wdata_0) != wdata_0); |
| 59 | |
| 60 | val = tegra_mc_read_32(MC_CLIENT_HOTRESET_CTRL1); |
| 61 | assert(val == MC_CLIENT_HOTRESET_CTRL1_RESET_VAL); |
| 62 | |
| 63 | wdata_1 = MC_CLIENT_HOTRESET_CTRL1_SDMMC4A_FLUSH_ENB | |
| 64 | MC_CLIENT_HOTRESET_CTRL1_APE_FLUSH_ENB | |
| 65 | MC_CLIENT_HOTRESET_CTRL1_SE_FLUSH_ENB | |
| 66 | MC_CLIENT_HOTRESET_CTRL1_ETR_FLUSH_ENB | |
| 67 | MC_CLIENT_HOTRESET_CTRL1_AXIS_FLUSH_ENB | |
| 68 | MC_CLIENT_HOTRESET_CTRL1_EQOS_FLUSH_ENB | |
| 69 | MC_CLIENT_HOTRESET_CTRL1_UFSHC_FLUSH_ENB | |
| 70 | MC_CLIENT_HOTRESET_CTRL1_BPMP_FLUSH_ENB | |
| 71 | MC_CLIENT_HOTRESET_CTRL1_AON_FLUSH_ENB | |
| 72 | MC_CLIENT_HOTRESET_CTRL1_SCE_FLUSH_ENB; |
| 73 | tegra_mc_write_32(MC_CLIENT_HOTRESET_CTRL1, wdata_1); |
| 74 | |
| 75 | /* Wait for HOTRESET STATUS to indicate FLUSH_DONE */ |
| 76 | do { |
| 77 | val = tegra_mc_read_32(MC_CLIENT_HOTRESET_STATUS1); |
| 78 | } while ((val & wdata_1) != wdata_1); |
| 79 | |
| 80 | /* Wait one more time due to SW WAR for known legacy issue */ |
| 81 | do { |
| 82 | val = tegra_mc_read_32(MC_CLIENT_HOTRESET_STATUS1); |
| 83 | } while ((val & wdata_1) != wdata_1); |
| 84 | |
| 85 | /* |
| 86 | * Change MEMTYPE_OVERRIDE from SO_DEV -> PASSTHRU for boot and |
| 87 | * strongly ordered MSS clients. ROC needs to be single point |
| 88 | * of control on overriding the memory type. So, remove TSA's |
| 89 | * memtype override. |
Krishna Reddy | 329e228 | 2017-05-25 11:04:33 -0700 | [diff] [blame] | 90 | * |
| 91 | * MC clients with default SO_DEV override still enabled at TSA: |
| 92 | * AONW, BPMPW, SCEW, APEW |
Varun Wadekar | a0f2697 | 2016-03-11 17:18:51 -0800 | [diff] [blame] | 93 | */ |
Varun Wadekar | 4c7fa50 | 2016-12-13 13:13:42 -0800 | [diff] [blame] | 94 | #if ENABLE_AFI_DEVICE |
Varun Wadekar | a0f2697 | 2016-03-11 17:18:51 -0800 | [diff] [blame] | 95 | mc_set_tsa_passthrough(AFIW); |
Varun Wadekar | 4c7fa50 | 2016-12-13 13:13:42 -0800 | [diff] [blame] | 96 | #endif |
Varun Wadekar | a0f2697 | 2016-03-11 17:18:51 -0800 | [diff] [blame] | 97 | mc_set_tsa_passthrough(HDAW); |
| 98 | mc_set_tsa_passthrough(SATAW); |
| 99 | mc_set_tsa_passthrough(XUSB_HOSTW); |
| 100 | mc_set_tsa_passthrough(XUSB_DEVW); |
| 101 | mc_set_tsa_passthrough(SDMMCWAB); |
| 102 | mc_set_tsa_passthrough(APEDMAW); |
| 103 | mc_set_tsa_passthrough(SESWR); |
| 104 | mc_set_tsa_passthrough(ETRW); |
| 105 | mc_set_tsa_passthrough(AXISW); |
| 106 | mc_set_tsa_passthrough(EQOSW); |
| 107 | mc_set_tsa_passthrough(UFSHCW); |
| 108 | mc_set_tsa_passthrough(BPMPDMAW); |
| 109 | mc_set_tsa_passthrough(AONDMAW); |
| 110 | mc_set_tsa_passthrough(SCEDMAW); |
| 111 | |
Krishna Reddy | 329e228 | 2017-05-25 11:04:33 -0700 | [diff] [blame] | 112 | /* Parker has no IO Coherency support and need the following: |
| 113 | * Ordered MC Clients on Parker are AFI, EQOS, SATA, XUSB. |
| 114 | * ISO clients(DISP, VI, EQOS) should never snoop caches and |
| 115 | * don't need ROC/PCFIFO ordering. |
| 116 | * ISO clients(EQOS) that need ordering should use PCFIFO ordering |
| 117 | * and bypass ROC ordering by using FORCE_NON_COHERENT path. |
| 118 | * FORCE_NON_COHERENT/FORCE_COHERENT config take precedence |
| 119 | * over SMMU attributes. |
| 120 | * Force all Normal memory transactions from ISO and non-ISO to be |
| 121 | * non-coherent(bypass ROC, avoid cache snoop to avoid perf hit). |
| 122 | * Force the SO_DEV transactions from ordered ISO clients(EQOS) to |
| 123 | * non-coherent path and enable MC PCFIFO interlock for ordering. |
| 124 | * Force the SO_DEV transactions from ordered non-ISO clients (PCIe, |
| 125 | * XUSB, SATA) to coherent so that the transactions are |
| 126 | * ordered by ROC. |
| 127 | * PCFIFO ensure write ordering. |
| 128 | * Read after Write ordering is maintained/enforced by MC clients. |
| 129 | * Clients that need PCIe type write ordering must |
| 130 | * go through ROC ordering. |
| 131 | * Ordering enable for Read clients is not necessary. |
| 132 | * R5's and A9 would get necessary ordering from AXI and |
| 133 | * don't need ROC ordering enable: |
| 134 | * - MMIO ordering is through dev mapping and MMIO |
| 135 | * accesses bypass SMMU. |
| 136 | * - Normal memory is accessed through SMMU and ordering is |
| 137 | * ensured by client and AXI. |
| 138 | * - Ack point for Normal memory is WCAM in MC. |
| 139 | * - MMIO's can be early acked and AXI ensures dev memory ordering, |
| 140 | * Client ensures read/write direction change ordering. |
| 141 | * - See Bug 200312466 for more details. |
Varun Wadekar | a0f2697 | 2016-03-11 17:18:51 -0800 | [diff] [blame] | 142 | * |
Krishna Reddy | 329e228 | 2017-05-25 11:04:33 -0700 | [diff] [blame] | 143 | * CGID_TAG_ADR is only present from T186 A02. As this code is common |
| 144 | * between A01 and A02, tegra_memctrl_set_overrides() programs |
| 145 | * CGID_TAG_ADR for the necessary clients on A02. |
Varun Wadekar | a0f2697 | 2016-03-11 17:18:51 -0800 | [diff] [blame] | 146 | */ |
Krishna Reddy | 329e228 | 2017-05-25 11:04:33 -0700 | [diff] [blame] | 147 | mc_set_txn_override(HDAR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); |
| 148 | mc_set_txn_override(BPMPW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); |
| 149 | mc_set_txn_override(PTCR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); |
| 150 | mc_set_txn_override(NVDISPLAYR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); |
| 151 | mc_set_txn_override(EQOSW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); |
| 152 | mc_set_txn_override(NVJPGSWR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); |
| 153 | mc_set_txn_override(ISPRA, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); |
| 154 | mc_set_txn_override(SDMMCWAA, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); |
| 155 | mc_set_txn_override(VICSRD, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); |
| 156 | mc_set_txn_override(MPCOREW, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); |
| 157 | mc_set_txn_override(GPUSRD, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); |
| 158 | mc_set_txn_override(AXISR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); |
| 159 | mc_set_txn_override(SCEDMAW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); |
| 160 | mc_set_txn_override(SDMMCW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); |
| 161 | mc_set_txn_override(EQOSR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); |
| 162 | /* See bug 200131110 comment #35*/ |
| 163 | mc_set_txn_override(APEDMAR, CGID_TAG_CLIENT_AXI_ID, SO_DEV_CLIENT_AXI_ID, FORCE_NON_COHERENT, FORCE_NON_COHERENT); |
| 164 | mc_set_txn_override(NVENCSRD, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); |
| 165 | mc_set_txn_override(SDMMCRAB, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); |
| 166 | mc_set_txn_override(VICSRD1, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); |
| 167 | mc_set_txn_override(BPMPDMAR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); |
| 168 | mc_set_txn_override(VIW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); |
| 169 | mc_set_txn_override(SDMMCRAA, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); |
| 170 | mc_set_txn_override(AXISW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); |
| 171 | mc_set_txn_override(XUSB_DEVR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); |
| 172 | mc_set_txn_override(UFSHCR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); |
| 173 | mc_set_txn_override(TSECSWR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); |
| 174 | mc_set_txn_override(GPUSWR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); |
| 175 | mc_set_txn_override(SATAR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); |
| 176 | mc_set_txn_override(XUSB_HOSTW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_COHERENT); |
| 177 | mc_set_txn_override(TSECSWRB, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); |
| 178 | mc_set_txn_override(GPUSRD2, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); |
| 179 | mc_set_txn_override(SCEDMAR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); |
| 180 | mc_set_txn_override(GPUSWR2, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); |
| 181 | mc_set_txn_override(AONDMAW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); |
| 182 | /* See bug 200131110 comment #35*/ |
| 183 | mc_set_txn_override(APEDMAW, CGID_TAG_CLIENT_AXI_ID, SO_DEV_CLIENT_AXI_ID, FORCE_NON_COHERENT, FORCE_NON_COHERENT); |
| 184 | mc_set_txn_override(AONW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); |
| 185 | mc_set_txn_override(HOST1XDMAR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); |
| 186 | mc_set_txn_override(ETRR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); |
| 187 | mc_set_txn_override(SESWR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); |
| 188 | mc_set_txn_override(NVJPGSRD, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); |
| 189 | mc_set_txn_override(NVDECSRD, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); |
| 190 | mc_set_txn_override(TSECSRDB, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); |
| 191 | mc_set_txn_override(BPMPDMAW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); |
| 192 | mc_set_txn_override(APER, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); |
| 193 | mc_set_txn_override(NVDECSRD1, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); |
| 194 | mc_set_txn_override(XUSB_HOSTR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); |
| 195 | mc_set_txn_override(ISPWA, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); |
| 196 | mc_set_txn_override(SESRD, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); |
| 197 | mc_set_txn_override(SCER, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); |
| 198 | mc_set_txn_override(AONR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); |
| 199 | mc_set_txn_override(MPCORER, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); |
| 200 | mc_set_txn_override(SDMMCWA, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); |
| 201 | mc_set_txn_override(HDAW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); |
| 202 | mc_set_txn_override(NVDECSWR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); |
| 203 | mc_set_txn_override(UFSHCW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); |
| 204 | mc_set_txn_override(AONDMAR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); |
| 205 | mc_set_txn_override(SATAW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_COHERENT); |
| 206 | mc_set_txn_override(ETRW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); |
| 207 | mc_set_txn_override(VICSWR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); |
| 208 | mc_set_txn_override(NVENCSWR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); |
| 209 | /* See bug 200131110 comment #35 */ |
| 210 | mc_set_txn_override(AFIR, CGID_TAG_DEFAULT, SO_DEV_CLIENT_AXI_ID, FORCE_NON_COHERENT, FORCE_NON_COHERENT); |
| 211 | mc_set_txn_override(SDMMCWAB, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); |
| 212 | mc_set_txn_override(SDMMCRA, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); |
| 213 | mc_set_txn_override(NVDISPLAYR1, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); |
| 214 | mc_set_txn_override(ISPWB, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); |
| 215 | mc_set_txn_override(BPMPR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); |
| 216 | mc_set_txn_override(APEW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); |
| 217 | mc_set_txn_override(SDMMCR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); |
| 218 | mc_set_txn_override(XUSB_DEVW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_COHERENT); |
| 219 | mc_set_txn_override(TSECSRD, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); |
Varun Wadekar | a0f2697 | 2016-03-11 17:18:51 -0800 | [diff] [blame] | 220 | /* |
| 221 | * See bug 200131110 comment #35 - there are no normal requests |
| 222 | * and AWID for SO/DEV requests is hardcoded in RTL for a |
| 223 | * particular PCIE controller |
| 224 | */ |
Krishna Reddy | 329e228 | 2017-05-25 11:04:33 -0700 | [diff] [blame] | 225 | mc_set_txn_override(AFIW, CGID_TAG_DEFAULT, SO_DEV_CLIENT_AXI_ID, FORCE_NON_COHERENT, FORCE_COHERENT); |
| 226 | mc_set_txn_override(SCEW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); |
Varun Wadekar | a0f2697 | 2016-03-11 17:18:51 -0800 | [diff] [blame] | 227 | |
| 228 | /* |
| 229 | * At this point, ordering can occur at ROC. So, remove PCFIFO's |
| 230 | * control over ordering requests. |
| 231 | * |
| 232 | * Change PCFIFO_*_ORDERED_CLIENT from ORDERED -> UNORDERED for |
| 233 | * boot and strongly ordered MSS clients |
| 234 | */ |
| 235 | val = MC_PCFIFO_CLIENT_CONFIG1_RESET_VAL & |
Varun Wadekar | 4c7fa50 | 2016-12-13 13:13:42 -0800 | [diff] [blame] | 236 | #if ENABLE_AFI_DEVICE |
Varun Wadekar | a0f2697 | 2016-03-11 17:18:51 -0800 | [diff] [blame] | 237 | mc_set_pcfifo_unordered_boot_so_mss(1, AFIW) & |
Varun Wadekar | 4c7fa50 | 2016-12-13 13:13:42 -0800 | [diff] [blame] | 238 | #endif |
Varun Wadekar | a0f2697 | 2016-03-11 17:18:51 -0800 | [diff] [blame] | 239 | mc_set_pcfifo_unordered_boot_so_mss(1, HDAW) & |
| 240 | mc_set_pcfifo_unordered_boot_so_mss(1, SATAW); |
| 241 | tegra_mc_write_32(MC_PCFIFO_CLIENT_CONFIG1, val); |
| 242 | |
| 243 | val = MC_PCFIFO_CLIENT_CONFIG2_RESET_VAL & |
| 244 | mc_set_pcfifo_unordered_boot_so_mss(2, XUSB_HOSTW) & |
| 245 | mc_set_pcfifo_unordered_boot_so_mss(2, XUSB_DEVW); |
| 246 | tegra_mc_write_32(MC_PCFIFO_CLIENT_CONFIG2, val); |
| 247 | |
| 248 | val = MC_PCFIFO_CLIENT_CONFIG3_RESET_VAL & |
| 249 | mc_set_pcfifo_unordered_boot_so_mss(3, SDMMCWAB); |
| 250 | tegra_mc_write_32(MC_PCFIFO_CLIENT_CONFIG3, val); |
| 251 | |
| 252 | val = MC_PCFIFO_CLIENT_CONFIG4_RESET_VAL & |
| 253 | mc_set_pcfifo_unordered_boot_so_mss(4, SESWR) & |
| 254 | mc_set_pcfifo_unordered_boot_so_mss(4, ETRW) & |
| 255 | mc_set_pcfifo_unordered_boot_so_mss(4, AXISW) & |
Varun Wadekar | a0f2697 | 2016-03-11 17:18:51 -0800 | [diff] [blame] | 256 | mc_set_pcfifo_unordered_boot_so_mss(4, UFSHCW) & |
| 257 | mc_set_pcfifo_unordered_boot_so_mss(4, BPMPDMAW) & |
| 258 | mc_set_pcfifo_unordered_boot_so_mss(4, AONDMAW) & |
| 259 | mc_set_pcfifo_unordered_boot_so_mss(4, SCEDMAW); |
Krishna Reddy | 329e228 | 2017-05-25 11:04:33 -0700 | [diff] [blame] | 260 | /* EQOSW is the only client that has PCFIFO order enabled. */ |
| 261 | val |= mc_set_pcfifo_ordered_boot_so_mss(4, EQOSW); |
Varun Wadekar | a0f2697 | 2016-03-11 17:18:51 -0800 | [diff] [blame] | 262 | tegra_mc_write_32(MC_PCFIFO_CLIENT_CONFIG4, val); |
| 263 | |
| 264 | val = MC_PCFIFO_CLIENT_CONFIG5_RESET_VAL & |
| 265 | mc_set_pcfifo_unordered_boot_so_mss(5, APEDMAW); |
| 266 | tegra_mc_write_32(MC_PCFIFO_CLIENT_CONFIG5, val); |
| 267 | |
| 268 | /* |
Varun Wadekar | a0f2697 | 2016-03-11 17:18:51 -0800 | [diff] [blame] | 269 | * Deassert HOTRESET FLUSH_ENABLE for boot and strongly ordered MSS |
| 270 | * clients to allow memory traffic from all clients to start passing |
| 271 | * through ROC |
| 272 | */ |
| 273 | val = tegra_mc_read_32(MC_CLIENT_HOTRESET_CTRL0); |
| 274 | assert(val == wdata_0); |
| 275 | |
| 276 | wdata_0 = MC_CLIENT_HOTRESET_CTRL0_RESET_VAL; |
| 277 | tegra_mc_write_32(MC_CLIENT_HOTRESET_CTRL0, wdata_0); |
| 278 | |
Varun Wadekar | a0f2697 | 2016-03-11 17:18:51 -0800 | [diff] [blame] | 279 | val = tegra_mc_read_32(MC_CLIENT_HOTRESET_CTRL1); |
| 280 | assert(val == wdata_1); |
| 281 | |
| 282 | wdata_1 = MC_CLIENT_HOTRESET_CTRL1_RESET_VAL; |
| 283 | tegra_mc_write_32(MC_CLIENT_HOTRESET_CTRL1, wdata_1); |
| 284 | |
Varun Wadekar | a0f2697 | 2016-03-11 17:18:51 -0800 | [diff] [blame] | 285 | #endif |
| 286 | } |
| 287 | |
Varun Wadekar | ad45ef7 | 2017-04-03 13:44:57 -0700 | [diff] [blame] | 288 | static void tegra_memctrl_set_overrides(void) |
| 289 | { |
Anthony Zhou | 0844b97 | 2017-06-28 16:35:54 +0800 | [diff] [blame] | 290 | const tegra_mc_settings_t *plat_mc_settings = tegra_get_mc_settings(); |
Varun Wadekar | ad45ef7 | 2017-04-03 13:44:57 -0700 | [diff] [blame] | 291 | const mc_txn_override_cfg_t *mc_txn_override_cfgs; |
| 292 | uint32_t num_txn_override_cfgs; |
| 293 | uint32_t i, val; |
| 294 | |
| 295 | /* Get the settings from the platform */ |
Anthony Zhou | 4408e88 | 2017-07-07 14:29:51 +0800 | [diff] [blame] | 296 | assert(plat_mc_settings != NULL); |
Varun Wadekar | ad45ef7 | 2017-04-03 13:44:57 -0700 | [diff] [blame] | 297 | mc_txn_override_cfgs = plat_mc_settings->txn_override_cfg; |
| 298 | num_txn_override_cfgs = plat_mc_settings->num_txn_override_cfgs; |
| 299 | |
| 300 | /* |
| 301 | * Set the MC_TXN_OVERRIDE registers for write clients. |
| 302 | */ |
| 303 | if ((tegra_chipid_is_t186()) && |
| 304 | (!tegra_platform_is_silicon() || |
Anthony Zhou | 0e07e45 | 2017-07-26 17:16:54 +0800 | [diff] [blame] | 305 | (tegra_platform_is_silicon() && (tegra_get_chipid_minor() == 1U)))) { |
Varun Wadekar | ad45ef7 | 2017-04-03 13:44:57 -0700 | [diff] [blame] | 306 | |
| 307 | /* |
| 308 | * GPU and NVENC settings for Tegra186 simulation and |
| 309 | * Silicon rev. A01 |
| 310 | */ |
| 311 | val = tegra_mc_read_32(MC_TXN_OVERRIDE_CONFIG_GPUSWR); |
Anthony Zhou | 0e07e45 | 2017-07-26 17:16:54 +0800 | [diff] [blame] | 312 | val &= (uint32_t)~MC_TXN_OVERRIDE_CGID_TAG_MASK; |
Varun Wadekar | ad45ef7 | 2017-04-03 13:44:57 -0700 | [diff] [blame] | 313 | tegra_mc_write_32(MC_TXN_OVERRIDE_CONFIG_GPUSWR, |
| 314 | val | MC_TXN_OVERRIDE_CGID_TAG_ZERO); |
| 315 | |
| 316 | val = tegra_mc_read_32(MC_TXN_OVERRIDE_CONFIG_GPUSWR2); |
Anthony Zhou | 0e07e45 | 2017-07-26 17:16:54 +0800 | [diff] [blame] | 317 | val &= (uint32_t)~MC_TXN_OVERRIDE_CGID_TAG_MASK; |
Varun Wadekar | ad45ef7 | 2017-04-03 13:44:57 -0700 | [diff] [blame] | 318 | tegra_mc_write_32(MC_TXN_OVERRIDE_CONFIG_GPUSWR2, |
| 319 | val | MC_TXN_OVERRIDE_CGID_TAG_ZERO); |
| 320 | |
| 321 | val = tegra_mc_read_32(MC_TXN_OVERRIDE_CONFIG_NVENCSWR); |
Anthony Zhou | 0e07e45 | 2017-07-26 17:16:54 +0800 | [diff] [blame] | 322 | val &= (uint32_t)~MC_TXN_OVERRIDE_CGID_TAG_MASK; |
Varun Wadekar | ad45ef7 | 2017-04-03 13:44:57 -0700 | [diff] [blame] | 323 | tegra_mc_write_32(MC_TXN_OVERRIDE_CONFIG_NVENCSWR, |
| 324 | val | MC_TXN_OVERRIDE_CGID_TAG_CLIENT_AXI_ID); |
| 325 | |
| 326 | } else { |
| 327 | |
| 328 | /* |
| 329 | * Settings for Tegra186 silicon rev. A02 and onwards. |
| 330 | */ |
| 331 | for (i = 0; i < num_txn_override_cfgs; i++) { |
| 332 | val = tegra_mc_read_32(mc_txn_override_cfgs[i].offset); |
Anthony Zhou | 0e07e45 | 2017-07-26 17:16:54 +0800 | [diff] [blame] | 333 | val &= (uint32_t)~MC_TXN_OVERRIDE_CGID_TAG_MASK; |
Varun Wadekar | ad45ef7 | 2017-04-03 13:44:57 -0700 | [diff] [blame] | 334 | tegra_mc_write_32(mc_txn_override_cfgs[i].offset, |
| 335 | val | mc_txn_override_cfgs[i].cgid_tag); |
| 336 | } |
| 337 | } |
| 338 | } |
| 339 | |
Varun Wadekar | cd5a2f5 | 2015-09-20 15:08:22 +0530 | [diff] [blame] | 340 | /* |
Varun Wadekar | 87e44ff | 2016-03-03 13:22:39 -0800 | [diff] [blame] | 341 | * Init Memory controller during boot. |
Varun Wadekar | cd5a2f5 | 2015-09-20 15:08:22 +0530 | [diff] [blame] | 342 | */ |
| 343 | void tegra_memctrl_setup(void) |
| 344 | { |
| 345 | uint32_t val; |
Pritesh Raithatha | 9eb5db5 | 2017-01-02 19:42:31 +0530 | [diff] [blame] | 346 | const uint32_t *mc_streamid_override_regs; |
| 347 | uint32_t num_streamid_override_regs; |
| 348 | const mc_streamid_security_cfg_t *mc_streamid_sec_cfgs; |
| 349 | uint32_t num_streamid_sec_cfgs; |
Anthony Zhou | 0844b97 | 2017-06-28 16:35:54 +0800 | [diff] [blame] | 350 | const tegra_mc_settings_t *plat_mc_settings = tegra_get_mc_settings(); |
Varun Wadekar | ad45ef7 | 2017-04-03 13:44:57 -0700 | [diff] [blame] | 351 | uint32_t i; |
Varun Wadekar | cd5a2f5 | 2015-09-20 15:08:22 +0530 | [diff] [blame] | 352 | |
| 353 | INFO("Tegra Memory Controller (v2)\n"); |
| 354 | |
Varun Wadekar | 6cb25f9 | 2016-12-19 11:17:54 -0800 | [diff] [blame] | 355 | #if ENABLE_SMMU_DEVICE |
Varun Wadekar | cd5a2f5 | 2015-09-20 15:08:22 +0530 | [diff] [blame] | 356 | /* Program the SMMU pagesize */ |
Varun Wadekar | 87e44ff | 2016-03-03 13:22:39 -0800 | [diff] [blame] | 357 | tegra_smmu_init(); |
Varun Wadekar | 6cb25f9 | 2016-12-19 11:17:54 -0800 | [diff] [blame] | 358 | #endif |
Pritesh Raithatha | 9eb5db5 | 2017-01-02 19:42:31 +0530 | [diff] [blame] | 359 | /* Get the settings from the platform */ |
Anthony Zhou | 4408e88 | 2017-07-07 14:29:51 +0800 | [diff] [blame] | 360 | assert(plat_mc_settings != NULL); |
Pritesh Raithatha | 9eb5db5 | 2017-01-02 19:42:31 +0530 | [diff] [blame] | 361 | mc_streamid_override_regs = plat_mc_settings->streamid_override_cfg; |
| 362 | num_streamid_override_regs = plat_mc_settings->num_streamid_override_cfgs; |
| 363 | mc_streamid_sec_cfgs = plat_mc_settings->streamid_security_cfg; |
| 364 | num_streamid_sec_cfgs = plat_mc_settings->num_streamid_security_cfgs; |
Varun Wadekar | cd5a2f5 | 2015-09-20 15:08:22 +0530 | [diff] [blame] | 365 | |
| 366 | /* Program all the Stream ID overrides */ |
Pritesh Raithatha | 9eb5db5 | 2017-01-02 19:42:31 +0530 | [diff] [blame] | 367 | for (i = 0; i < num_streamid_override_regs; i++) |
| 368 | tegra_mc_streamid_write_32(mc_streamid_override_regs[i], |
Varun Wadekar | cd5a2f5 | 2015-09-20 15:08:22 +0530 | [diff] [blame] | 369 | MC_STREAM_ID_MAX); |
| 370 | |
| 371 | /* Program the security config settings for all Stream IDs */ |
Pritesh Raithatha | 9eb5db5 | 2017-01-02 19:42:31 +0530 | [diff] [blame] | 372 | for (i = 0; i < num_streamid_sec_cfgs; i++) { |
| 373 | val = mc_streamid_sec_cfgs[i].override_enable << 16 | |
| 374 | mc_streamid_sec_cfgs[i].override_client_inputs << 8 | |
| 375 | mc_streamid_sec_cfgs[i].override_client_ns_flag << 0; |
| 376 | tegra_mc_streamid_write_32(mc_streamid_sec_cfgs[i].offset, val); |
Varun Wadekar | cd5a2f5 | 2015-09-20 15:08:22 +0530 | [diff] [blame] | 377 | } |
| 378 | |
| 379 | /* |
| 380 | * All requests at boot time, and certain requests during |
| 381 | * normal run time, are physically addressed and must bypass |
| 382 | * the SMMU. The client hub logic implements a hardware bypass |
| 383 | * path around the Translation Buffer Units (TBU). During |
| 384 | * boot-time, the SMMU_BYPASS_CTRL register (which defaults to |
| 385 | * TBU_BYPASS mode) will be used to steer all requests around |
| 386 | * the uninitialized TBUs. During normal operation, this register |
| 387 | * is locked into TBU_BYPASS_SID config, which routes requests |
| 388 | * with special StreamID 0x7f on the bypass path and all others |
| 389 | * through the selected TBU. This is done to disable SMMU Bypass |
| 390 | * mode, as it could be used to circumvent SMMU security checks. |
| 391 | */ |
| 392 | tegra_mc_write_32(MC_SMMU_BYPASS_CONFIG, |
Pritesh Raithatha | 9eb5db5 | 2017-01-02 19:42:31 +0530 | [diff] [blame] | 393 | MC_SMMU_BYPASS_CONFIG_SETTINGS); |
Varun Wadekar | cd5a2f5 | 2015-09-20 15:08:22 +0530 | [diff] [blame] | 394 | |
Varun Wadekar | c9ac3e4 | 2016-02-17 15:07:49 -0800 | [diff] [blame] | 395 | /* |
Varun Wadekar | a0f2697 | 2016-03-11 17:18:51 -0800 | [diff] [blame] | 396 | * Re-configure MSS to allow ROC to deal with ordering of the |
| 397 | * Memory Controller traffic. This is needed as the Memory Controller |
| 398 | * boots with MSS having all control, but ROC provides a performance |
| 399 | * boost as compared to MSS. |
| 400 | */ |
| 401 | tegra_memctrl_reconfig_mss_clients(); |
| 402 | |
Varun Wadekar | ad45ef7 | 2017-04-03 13:44:57 -0700 | [diff] [blame] | 403 | /* Program overrides for MC transactions */ |
| 404 | tegra_memctrl_set_overrides(); |
Varun Wadekar | 87e44ff | 2016-03-03 13:22:39 -0800 | [diff] [blame] | 405 | } |
Varun Wadekar | c9ac3e4 | 2016-02-17 15:07:49 -0800 | [diff] [blame] | 406 | |
Varun Wadekar | 87e44ff | 2016-03-03 13:22:39 -0800 | [diff] [blame] | 407 | /* |
| 408 | * Restore Memory Controller settings after "System Suspend" |
| 409 | */ |
| 410 | void tegra_memctrl_restore_settings(void) |
| 411 | { |
Varun Wadekar | a0f2697 | 2016-03-11 17:18:51 -0800 | [diff] [blame] | 412 | /* |
| 413 | * Re-configure MSS to allow ROC to deal with ordering of the |
| 414 | * Memory Controller traffic. This is needed as the Memory Controller |
| 415 | * resets during System Suspend with MSS having all control, but ROC |
| 416 | * provides a performance boost as compared to MSS. |
| 417 | */ |
| 418 | tegra_memctrl_reconfig_mss_clients(); |
| 419 | |
Varun Wadekar | ad45ef7 | 2017-04-03 13:44:57 -0700 | [diff] [blame] | 420 | /* Program overrides for MC transactions */ |
| 421 | tegra_memctrl_set_overrides(); |
| 422 | |
Varun Wadekar | cd5a2f5 | 2015-09-20 15:08:22 +0530 | [diff] [blame] | 423 | /* video memory carveout region */ |
Anthony Zhou | 0e07e45 | 2017-07-26 17:16:54 +0800 | [diff] [blame] | 424 | if (video_mem_base != 0ULL) { |
Varun Wadekar | cd5a2f5 | 2015-09-20 15:08:22 +0530 | [diff] [blame] | 425 | tegra_mc_write_32(MC_VIDEO_PROTECT_BASE_LO, |
| 426 | (uint32_t)video_mem_base); |
| 427 | tegra_mc_write_32(MC_VIDEO_PROTECT_BASE_HI, |
| 428 | (uint32_t)(video_mem_base >> 32)); |
Varun Wadekar | 7058aee | 2016-04-25 09:01:46 -0700 | [diff] [blame] | 429 | tegra_mc_write_32(MC_VIDEO_PROTECT_SIZE_MB, video_mem_size_mb); |
Varun Wadekar | cd5a2f5 | 2015-09-20 15:08:22 +0530 | [diff] [blame] | 430 | |
| 431 | /* |
Varun Wadekar | 153982c | 2016-12-21 14:50:18 -0800 | [diff] [blame] | 432 | * MCE propagates the VideoMem configuration values across the |
Varun Wadekar | cd5a2f5 | 2015-09-20 15:08:22 +0530 | [diff] [blame] | 433 | * CCPLEX. |
| 434 | */ |
| 435 | mce_update_gsc_videomem(); |
| 436 | } |
| 437 | } |
| 438 | |
| 439 | /* |
| 440 | * Secure the BL31 DRAM aperture. |
| 441 | * |
| 442 | * phys_base = physical base of TZDRAM aperture |
| 443 | * size_in_bytes = size of aperture in bytes |
| 444 | */ |
| 445 | void tegra_memctrl_tzdram_setup(uint64_t phys_base, uint32_t size_in_bytes) |
| 446 | { |
| 447 | /* |
| 448 | * Setup the Memory controller to allow only secure accesses to |
| 449 | * the TZDRAM carveout |
| 450 | */ |
| 451 | INFO("Configuring TrustZone DRAM Memory Carveout\n"); |
| 452 | |
| 453 | tegra_mc_write_32(MC_SECURITY_CFG0_0, (uint32_t)phys_base); |
| 454 | tegra_mc_write_32(MC_SECURITY_CFG3_0, (uint32_t)(phys_base >> 32)); |
| 455 | tegra_mc_write_32(MC_SECURITY_CFG1_0, size_in_bytes >> 20); |
| 456 | |
| 457 | /* |
Harvey Hsieh | c95802d | 2016-07-29 20:10:59 +0800 | [diff] [blame] | 458 | * When TZ encryption enabled, |
| 459 | * We need setup TZDRAM before CPU to access TZ Carveout, |
| 460 | * otherwise CPU will fetch non-decrypted data. |
| 461 | * So save TZDRAM setting for retore by SC7 resume FW. |
| 462 | */ |
| 463 | |
| 464 | mmio_write_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV55_LO, |
| 465 | tegra_mc_read_32(MC_SECURITY_CFG0_0)); |
| 466 | mmio_write_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV55_HI, |
| 467 | tegra_mc_read_32(MC_SECURITY_CFG3_0)); |
| 468 | mmio_write_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV54_HI, |
| 469 | tegra_mc_read_32(MC_SECURITY_CFG1_0)); |
| 470 | |
| 471 | /* |
Varun Wadekar | 153982c | 2016-12-21 14:50:18 -0800 | [diff] [blame] | 472 | * MCE propagates the security configuration values across the |
Varun Wadekar | cd5a2f5 | 2015-09-20 15:08:22 +0530 | [diff] [blame] | 473 | * CCPLEX. |
| 474 | */ |
| 475 | mce_update_gsc_tzdram(); |
| 476 | } |
| 477 | |
| 478 | /* |
Varun Wadekar | 13e7dc4 | 2015-12-30 15:15:08 -0800 | [diff] [blame] | 479 | * Secure the BL31 TZRAM aperture. |
| 480 | * |
| 481 | * phys_base = physical base of TZRAM aperture |
| 482 | * size_in_bytes = size of aperture in bytes |
| 483 | */ |
| 484 | void tegra_memctrl_tzram_setup(uint64_t phys_base, uint32_t size_in_bytes) |
| 485 | { |
Varun Wadekar | e6d4322 | 2016-05-25 16:35:04 -0700 | [diff] [blame] | 486 | uint32_t index; |
| 487 | uint32_t total_128kb_blocks = size_in_bytes >> 17; |
Varun Wadekar | 153982c | 2016-12-21 14:50:18 -0800 | [diff] [blame] | 488 | uint32_t residual_4kb_blocks = (size_in_bytes & (uint32_t)0x1FFFF) >> 12; |
Varun Wadekar | 13e7dc4 | 2015-12-30 15:15:08 -0800 | [diff] [blame] | 489 | uint32_t val; |
| 490 | |
Varun Wadekar | 153982c | 2016-12-21 14:50:18 -0800 | [diff] [blame] | 491 | INFO("Configuring TrustZone SRAM Memory Carveout\n"); |
| 492 | |
Varun Wadekar | 13e7dc4 | 2015-12-30 15:15:08 -0800 | [diff] [blame] | 493 | /* |
Varun Wadekar | e6d4322 | 2016-05-25 16:35:04 -0700 | [diff] [blame] | 494 | * Reset the access configuration registers to restrict access |
| 495 | * to the TZRAM aperture |
Varun Wadekar | 13e7dc4 | 2015-12-30 15:15:08 -0800 | [diff] [blame] | 496 | */ |
Varun Wadekar | 153982c | 2016-12-21 14:50:18 -0800 | [diff] [blame] | 497 | for (index = MC_TZRAM_CLIENT_ACCESS_CFG0; |
| 498 | index < ((uint32_t)MC_TZRAM_CARVEOUT_CFG + (uint32_t)MC_GSC_CONFIG_REGS_SIZE); |
| 499 | index += 4U) { |
Varun Wadekar | e6d4322 | 2016-05-25 16:35:04 -0700 | [diff] [blame] | 500 | tegra_mc_write_32(index, 0); |
Varun Wadekar | 153982c | 2016-12-21 14:50:18 -0800 | [diff] [blame] | 501 | } |
Varun Wadekar | 13e7dc4 | 2015-12-30 15:15:08 -0800 | [diff] [blame] | 502 | |
| 503 | /* |
Varun Wadekar | e6d4322 | 2016-05-25 16:35:04 -0700 | [diff] [blame] | 504 | * Set the TZRAM base. TZRAM base must be 4k aligned, at least. |
| 505 | */ |
Varun Wadekar | 153982c | 2016-12-21 14:50:18 -0800 | [diff] [blame] | 506 | assert((phys_base & (uint64_t)0xFFF) == 0U); |
Varun Wadekar | e6d4322 | 2016-05-25 16:35:04 -0700 | [diff] [blame] | 507 | tegra_mc_write_32(MC_TZRAM_BASE_LO, (uint32_t)phys_base); |
| 508 | tegra_mc_write_32(MC_TZRAM_BASE_HI, |
Varun Wadekar | 153982c | 2016-12-21 14:50:18 -0800 | [diff] [blame] | 509 | (uint32_t)(phys_base >> 32) & MC_GSC_BASE_HI_MASK); |
Varun Wadekar | 13e7dc4 | 2015-12-30 15:15:08 -0800 | [diff] [blame] | 510 | |
Varun Wadekar | e6d4322 | 2016-05-25 16:35:04 -0700 | [diff] [blame] | 511 | /* |
| 512 | * Set the TZRAM size |
| 513 | * |
| 514 | * total size = (number of 128KB blocks) + (number of remaining 4KB |
| 515 | * blocks) |
| 516 | * |
| 517 | */ |
Varun Wadekar | 153982c | 2016-12-21 14:50:18 -0800 | [diff] [blame] | 518 | val = (residual_4kb_blocks << MC_GSC_SIZE_RANGE_4KB_SHIFT) | |
Varun Wadekar | e6d4322 | 2016-05-25 16:35:04 -0700 | [diff] [blame] | 519 | total_128kb_blocks; |
| 520 | tegra_mc_write_32(MC_TZRAM_SIZE, val); |
Varun Wadekar | 13e7dc4 | 2015-12-30 15:15:08 -0800 | [diff] [blame] | 521 | |
Varun Wadekar | e6d4322 | 2016-05-25 16:35:04 -0700 | [diff] [blame] | 522 | /* |
| 523 | * Lock the configuration settings by disabling TZ-only lock |
| 524 | * and locking the configuration against any future changes |
| 525 | * at all. |
| 526 | */ |
| 527 | val = tegra_mc_read_32(MC_TZRAM_CARVEOUT_CFG); |
Anthony Zhou | 0844b97 | 2017-06-28 16:35:54 +0800 | [diff] [blame] | 528 | val &= (uint32_t)~MC_GSC_ENABLE_TZ_LOCK_BIT; |
Varun Wadekar | 153982c | 2016-12-21 14:50:18 -0800 | [diff] [blame] | 529 | val |= MC_GSC_LOCK_CFG_SETTINGS_BIT; |
Varun Wadekar | e6d4322 | 2016-05-25 16:35:04 -0700 | [diff] [blame] | 530 | tegra_mc_write_32(MC_TZRAM_CARVEOUT_CFG, val); |
Varun Wadekar | 13e7dc4 | 2015-12-30 15:15:08 -0800 | [diff] [blame] | 531 | |
| 532 | /* |
Varun Wadekar | 153982c | 2016-12-21 14:50:18 -0800 | [diff] [blame] | 533 | * MCE propagates the security configuration values across the |
Varun Wadekar | 13e7dc4 | 2015-12-30 15:15:08 -0800 | [diff] [blame] | 534 | * CCPLEX. |
| 535 | */ |
| 536 | mce_update_gsc_tzram(); |
| 537 | } |
| 538 | |
Varun Wadekar | 153982c | 2016-12-21 14:50:18 -0800 | [diff] [blame] | 539 | static void tegra_lock_videomem_nonoverlap(uint64_t phys_base, |
| 540 | uint64_t size_in_bytes) |
| 541 | { |
| 542 | uint32_t index; |
| 543 | uint64_t total_128kb_blocks = size_in_bytes >> 17; |
| 544 | uint64_t residual_4kb_blocks = (size_in_bytes & (uint32_t)0x1FFFF) >> 12; |
| 545 | uint64_t val; |
| 546 | |
| 547 | /* |
| 548 | * Reset the access configuration registers to restrict access to |
| 549 | * old Videomem aperture |
| 550 | */ |
| 551 | for (index = MC_VIDEO_PROTECT_CLEAR_ACCESS_CFG0; |
| 552 | index < ((uint32_t)MC_VIDEO_PROTECT_CLEAR_ACCESS_CFG0 + (uint32_t)MC_GSC_CONFIG_REGS_SIZE); |
| 553 | index += 4U) { |
| 554 | tegra_mc_write_32(index, 0); |
| 555 | } |
| 556 | |
| 557 | /* |
| 558 | * Set the base. It must be 4k aligned, at least. |
| 559 | */ |
| 560 | assert((phys_base & (uint64_t)0xFFF) == 0U); |
| 561 | tegra_mc_write_32(MC_VIDEO_PROTECT_CLEAR_BASE_LO, (uint32_t)phys_base); |
| 562 | tegra_mc_write_32(MC_VIDEO_PROTECT_CLEAR_BASE_HI, |
| 563 | (uint32_t)(phys_base >> 32) & (uint32_t)MC_GSC_BASE_HI_MASK); |
| 564 | |
| 565 | /* |
| 566 | * Set the aperture size |
| 567 | * |
| 568 | * total size = (number of 128KB blocks) + (number of remaining 4KB |
| 569 | * blocks) |
| 570 | * |
| 571 | */ |
| 572 | val = (uint32_t)((residual_4kb_blocks << MC_GSC_SIZE_RANGE_4KB_SHIFT) | |
| 573 | total_128kb_blocks); |
| 574 | tegra_mc_write_32(MC_VIDEO_PROTECT_CLEAR_SIZE, (uint32_t)val); |
| 575 | |
| 576 | /* |
| 577 | * Lock the configuration settings by enabling TZ-only lock and |
| 578 | * locking the configuration against any future changes from NS |
| 579 | * world. |
| 580 | */ |
| 581 | tegra_mc_write_32(MC_VIDEO_PROTECT_CLEAR_CFG, |
| 582 | (uint32_t)MC_GSC_ENABLE_TZ_LOCK_BIT); |
| 583 | |
| 584 | /* |
| 585 | * MCE propagates the GSC configuration values across the |
| 586 | * CCPLEX. |
| 587 | */ |
| 588 | } |
| 589 | |
| 590 | static void tegra_unlock_videomem_nonoverlap(void) |
| 591 | { |
| 592 | /* Clear the base */ |
| 593 | tegra_mc_write_32(MC_VIDEO_PROTECT_CLEAR_BASE_LO, 0); |
| 594 | tegra_mc_write_32(MC_VIDEO_PROTECT_CLEAR_BASE_HI, 0); |
| 595 | |
| 596 | /* Clear the size */ |
| 597 | tegra_mc_write_32(MC_VIDEO_PROTECT_CLEAR_SIZE, 0); |
| 598 | } |
| 599 | |
| 600 | static void tegra_clear_videomem(uintptr_t non_overlap_area_start, |
| 601 | unsigned long long non_overlap_area_size) |
| 602 | { |
| 603 | /* |
| 604 | * Map the NS memory first, clean it and then unmap it. |
| 605 | */ |
Anthony Zhou | 0844b97 | 2017-06-28 16:35:54 +0800 | [diff] [blame] | 606 | (void)mmap_add_dynamic_region(non_overlap_area_start, /* PA */ |
Varun Wadekar | 153982c | 2016-12-21 14:50:18 -0800 | [diff] [blame] | 607 | non_overlap_area_start, /* VA */ |
| 608 | non_overlap_area_size, /* size */ |
| 609 | MT_NS | MT_RW | MT_EXECUTE_NEVER); /* attrs */ |
| 610 | |
| 611 | zero_normalmem((void *)non_overlap_area_start, non_overlap_area_size); |
| 612 | flush_dcache_range(non_overlap_area_start, non_overlap_area_size); |
| 613 | |
Anthony Zhou | 0844b97 | 2017-06-28 16:35:54 +0800 | [diff] [blame] | 614 | (void)mmap_remove_dynamic_region(non_overlap_area_start, |
Varun Wadekar | 153982c | 2016-12-21 14:50:18 -0800 | [diff] [blame] | 615 | non_overlap_area_size); |
| 616 | } |
| 617 | |
Varun Wadekar | 13e7dc4 | 2015-12-30 15:15:08 -0800 | [diff] [blame] | 618 | /* |
Varun Wadekar | cd5a2f5 | 2015-09-20 15:08:22 +0530 | [diff] [blame] | 619 | * Program the Video Memory carveout region |
| 620 | * |
| 621 | * phys_base = physical base of aperture |
| 622 | * size_in_bytes = size of aperture in bytes |
| 623 | */ |
| 624 | void tegra_memctrl_videomem_setup(uint64_t phys_base, uint32_t size_in_bytes) |
| 625 | { |
Varun Wadekar | 153982c | 2016-12-21 14:50:18 -0800 | [diff] [blame] | 626 | uintptr_t vmem_end_old = video_mem_base + (video_mem_size_mb << 20); |
| 627 | uintptr_t vmem_end_new = phys_base + size_in_bytes; |
Varun Wadekar | 153982c | 2016-12-21 14:50:18 -0800 | [diff] [blame] | 628 | unsigned long long non_overlap_area_size; |
Varun Wadekar | e60f1bf | 2016-02-17 10:10:50 -0800 | [diff] [blame] | 629 | |
| 630 | /* |
Varun Wadekar | cd5a2f5 | 2015-09-20 15:08:22 +0530 | [diff] [blame] | 631 | * Setup the Memory controller to restrict CPU accesses to the Video |
| 632 | * Memory region |
| 633 | */ |
| 634 | INFO("Configuring Video Memory Carveout\n"); |
| 635 | |
Varun Wadekar | 153982c | 2016-12-21 14:50:18 -0800 | [diff] [blame] | 636 | /* |
| 637 | * Configure Memory Controller directly for the first time. |
| 638 | */ |
| 639 | if (video_mem_base == 0U) |
| 640 | goto done; |
| 641 | |
| 642 | /* |
| 643 | * Lock the non overlapping memory being cleared so that other masters |
| 644 | * do not accidently write to it. The memory would be unlocked once |
| 645 | * the non overlapping region is cleared and the new memory |
| 646 | * settings take effect. |
| 647 | */ |
| 648 | tegra_lock_videomem_nonoverlap(video_mem_base, |
| 649 | video_mem_size_mb << 20); |
| 650 | |
| 651 | /* |
| 652 | * Clear the old regions now being exposed. The following cases |
| 653 | * can occur - |
| 654 | * |
| 655 | * 1. clear whole old region (no overlap with new region) |
| 656 | * 2. clear old sub-region below new base |
| 657 | * 3. clear old sub-region above new end |
| 658 | */ |
| 659 | INFO("Cleaning previous Video Memory Carveout\n"); |
| 660 | |
Anthony Zhou | 0844b97 | 2017-06-28 16:35:54 +0800 | [diff] [blame] | 661 | if ((phys_base > vmem_end_old) || (video_mem_base > vmem_end_new)) { |
Varun Wadekar | 153982c | 2016-12-21 14:50:18 -0800 | [diff] [blame] | 662 | tegra_clear_videomem(video_mem_base, |
Anthony Zhou | 0844b97 | 2017-06-28 16:35:54 +0800 | [diff] [blame] | 663 | (uint32_t)video_mem_size_mb << 20U); |
Varun Wadekar | 153982c | 2016-12-21 14:50:18 -0800 | [diff] [blame] | 664 | } else { |
| 665 | if (video_mem_base < phys_base) { |
| 666 | non_overlap_area_size = phys_base - video_mem_base; |
Anthony Zhou | 0844b97 | 2017-06-28 16:35:54 +0800 | [diff] [blame] | 667 | tegra_clear_videomem(video_mem_base, |
| 668 | (uint32_t)non_overlap_area_size); |
Varun Wadekar | 153982c | 2016-12-21 14:50:18 -0800 | [diff] [blame] | 669 | } |
| 670 | if (vmem_end_old > vmem_end_new) { |
| 671 | non_overlap_area_size = vmem_end_old - vmem_end_new; |
Anthony Zhou | 0844b97 | 2017-06-28 16:35:54 +0800 | [diff] [blame] | 672 | tegra_clear_videomem(vmem_end_new, |
| 673 | (uint32_t)non_overlap_area_size); |
Varun Wadekar | 153982c | 2016-12-21 14:50:18 -0800 | [diff] [blame] | 674 | } |
| 675 | } |
| 676 | |
| 677 | done: |
| 678 | /* program the Videomem aperture */ |
Varun Wadekar | cd5a2f5 | 2015-09-20 15:08:22 +0530 | [diff] [blame] | 679 | tegra_mc_write_32(MC_VIDEO_PROTECT_BASE_LO, (uint32_t)phys_base); |
| 680 | tegra_mc_write_32(MC_VIDEO_PROTECT_BASE_HI, |
| 681 | (uint32_t)(phys_base >> 32)); |
Varun Wadekar | 7058aee | 2016-04-25 09:01:46 -0700 | [diff] [blame] | 682 | tegra_mc_write_32(MC_VIDEO_PROTECT_SIZE_MB, size_in_bytes >> 20); |
Varun Wadekar | cd5a2f5 | 2015-09-20 15:08:22 +0530 | [diff] [blame] | 683 | |
Varun Wadekar | 153982c | 2016-12-21 14:50:18 -0800 | [diff] [blame] | 684 | /* unlock the previous locked nonoverlapping aperture */ |
| 685 | tegra_unlock_videomem_nonoverlap(); |
| 686 | |
Varun Wadekar | cd5a2f5 | 2015-09-20 15:08:22 +0530 | [diff] [blame] | 687 | /* store new values */ |
| 688 | video_mem_base = phys_base; |
Varun Wadekar | 7058aee | 2016-04-25 09:01:46 -0700 | [diff] [blame] | 689 | video_mem_size_mb = size_in_bytes >> 20; |
Varun Wadekar | cd5a2f5 | 2015-09-20 15:08:22 +0530 | [diff] [blame] | 690 | |
| 691 | /* |
Varun Wadekar | 153982c | 2016-12-21 14:50:18 -0800 | [diff] [blame] | 692 | * MCE propagates the VideoMem configuration values across the |
Varun Wadekar | cd5a2f5 | 2015-09-20 15:08:22 +0530 | [diff] [blame] | 693 | * CCPLEX. |
| 694 | */ |
| 695 | mce_update_gsc_videomem(); |
| 696 | } |
Varun Wadekar | c92050b | 2017-03-29 14:57:29 -0700 | [diff] [blame] | 697 | |
| 698 | /* |
| 699 | * This feature exists only for v1 of the Tegra Memory Controller. |
| 700 | */ |
| 701 | void tegra_memctrl_disable_ahb_redirection(void) |
| 702 | { |
| 703 | ; /* do nothing */ |
| 704 | } |