Grzegorz Jaszczyk | 964aac4 | 2018-12-09 22:08:20 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2018 Marvell International Ltd. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | * https://spdx.org/licenses |
| 6 | */ |
| 7 | |
| 8 | #include <armada_common.h> |
| 9 | #include <mvebu_def.h> |
| 10 | |
| 11 | /* |
| 12 | * If bootrom is currently at BLE there's no need to include the memory |
| 13 | * maps structure at this point |
| 14 | */ |
| 15 | #ifndef IMAGE_BLE |
| 16 | |
| 17 | /***************************************************************************** |
| 18 | * AMB Configuration |
| 19 | ***************************************************************************** |
| 20 | */ |
| 21 | struct addr_map_win amb_memory_map_cp0[] = { |
| 22 | /* CP0 SPI1 CS0 Direct Mode access */ |
| 23 | {0xe800, 0x2000000, AMB_SPI1_CS0_ID}, |
| 24 | }; |
| 25 | |
| 26 | int marvell_get_amb_memory_map(struct addr_map_win **win, uint32_t *size, |
| 27 | uintptr_t base) |
| 28 | { |
| 29 | switch (base) { |
| 30 | case MVEBU_CP_REGS_BASE(0): |
| 31 | *win = amb_memory_map_cp0; |
| 32 | *size = ARRAY_SIZE(amb_memory_map_cp0); |
| 33 | return 0; |
| 34 | case MVEBU_CP_REGS_BASE(1): |
| 35 | case MVEBU_CP_REGS_BASE(2): |
| 36 | default: |
| 37 | *size = 0; |
| 38 | *win = 0; |
| 39 | return 1; |
| 40 | } |
| 41 | } |
| 42 | #endif |
| 43 | |
| 44 | /***************************************************************************** |
| 45 | * IO WIN Configuration |
| 46 | ***************************************************************************** |
| 47 | */ |
| 48 | struct addr_map_win io_win_memory_map[] = { |
Konstantin Porotchkin | e49569d | 2020-09-29 11:37:12 +0300 | [diff] [blame] | 49 | #if (CP_COUNT > 1) |
| 50 | /* SB (MCi0) internal regs */ |
| 51 | {0x00000000f4000000, 0x2000000, MCI_0_TID}, |
| 52 | #if (CP_COUNT > 2) |
| 53 | /* SB (MCi1) internal regs */ |
| 54 | {0x00000000f6000000, 0x2000000, MCI_1_TID}, |
| 55 | #endif |
| 56 | #endif |
Grzegorz Jaszczyk | 964aac4 | 2018-12-09 22:08:20 +0100 | [diff] [blame] | 57 | #ifndef IMAGE_BLE |
| 58 | /* SB (MCi0) PCIe0-2 on CP1 */ |
| 59 | {0x00000000e2000000, 0x3000000, MCI_0_TID}, |
| 60 | /* SB (MCi1) PCIe0-2 on CP2 */ |
| 61 | {0x00000000e5000000, 0x3000000, MCI_1_TID}, |
Grzegorz Jaszczyk | 964aac4 | 2018-12-09 22:08:20 +0100 | [diff] [blame] | 62 | /* MCI 0 indirect window */ |
| 63 | {MVEBU_MCI_REG_BASE_REMAP(0), 0x100000, MCI_0_TID}, |
| 64 | /* MCI 1 indirect window */ |
| 65 | {MVEBU_MCI_REG_BASE_REMAP(1), 0x100000, MCI_1_TID}, |
| 66 | #endif |
| 67 | }; |
| 68 | |
| 69 | /* Global Control Register - window default target */ |
| 70 | uint32_t marvell_get_io_win_gcr_target(int ap_index) |
| 71 | { |
| 72 | /* |
| 73 | * PIDI == iMCIP AP to SB internal MoChi connection. |
| 74 | * In other words CP0 |
| 75 | */ |
| 76 | return PIDI_TID; |
| 77 | } |
| 78 | |
| 79 | int marvell_get_io_win_memory_map(int ap_index, struct addr_map_win **win, |
| 80 | uint32_t *size) |
| 81 | { |
| 82 | *win = io_win_memory_map; |
| 83 | if (*win == NULL) |
| 84 | *size = 0; |
| 85 | else |
| 86 | *size = ARRAY_SIZE(io_win_memory_map); |
| 87 | |
| 88 | return 0; |
| 89 | } |
| 90 | |
| 91 | #ifndef IMAGE_BLE |
| 92 | /***************************************************************************** |
| 93 | * IOB Configuration |
| 94 | ***************************************************************************** |
| 95 | */ |
| 96 | struct addr_map_win iob_memory_map_cp0[] = { |
| 97 | /* SPI1_CS0 (RUNIT) window */ |
| 98 | {0x00000000e8000000, 0x2000000, RUNIT_TID}, |
| 99 | /* PEX2_X1 window */ |
| 100 | {0x00000000e1000000, 0x1000000, PEX2_TID}, |
| 101 | /* PEX1_X1 window */ |
| 102 | {0x00000000e0000000, 0x1000000, PEX1_TID}, |
| 103 | /* PEX0_X4 window */ |
| 104 | {0x00000000c0000000, 0x20000000, PEX0_TID}, |
| 105 | }; |
| 106 | |
| 107 | struct addr_map_win iob_memory_map_cp1[] = { |
| 108 | |
| 109 | /* PEX2_X1 window */ |
| 110 | {0x00000000e4000000, 0x1000000, PEX2_TID}, |
| 111 | /* PEX1_X1 window */ |
| 112 | {0x00000000e3000000, 0x1000000, PEX1_TID}, |
| 113 | /* PEX0_X4 window */ |
| 114 | {0x00000000e2000000, 0x1000000, PEX0_TID}, |
| 115 | }; |
| 116 | |
| 117 | struct addr_map_win iob_memory_map_cp2[] = { |
| 118 | |
| 119 | /* PEX2_X1 window */ |
| 120 | {0x00000000e7000000, 0x1000000, PEX2_TID}, |
| 121 | /* PEX1_X1 window */ |
| 122 | {0x00000000e6000000, 0x1000000, PEX1_TID}, |
| 123 | /* PEX0_X4 window */ |
| 124 | {0x00000000e5000000, 0x1000000, PEX0_TID}, |
| 125 | }; |
| 126 | |
| 127 | int marvell_get_iob_memory_map(struct addr_map_win **win, uint32_t *size, |
| 128 | uintptr_t base) |
| 129 | { |
| 130 | switch (base) { |
| 131 | case MVEBU_CP_REGS_BASE(0): |
| 132 | *win = iob_memory_map_cp0; |
| 133 | *size = ARRAY_SIZE(iob_memory_map_cp0); |
| 134 | return 0; |
| 135 | case MVEBU_CP_REGS_BASE(1): |
| 136 | *win = iob_memory_map_cp1; |
| 137 | *size = ARRAY_SIZE(iob_memory_map_cp1); |
| 138 | return 0; |
| 139 | case MVEBU_CP_REGS_BASE(2): |
| 140 | *win = iob_memory_map_cp2; |
| 141 | *size = ARRAY_SIZE(iob_memory_map_cp2); |
| 142 | return 0; |
| 143 | default: |
| 144 | *size = 0; |
| 145 | *win = 0; |
| 146 | return 1; |
| 147 | } |
| 148 | } |
| 149 | #endif |
| 150 | |
| 151 | /***************************************************************************** |
| 152 | * CCU Configuration |
| 153 | ***************************************************************************** |
| 154 | */ |
| 155 | struct addr_map_win ccu_memory_map[] = { /* IO window */ |
| 156 | #ifdef IMAGE_BLE |
| 157 | {0x00000000f2000000, 0x6000000, IO_0_TID}, /* IO window */ |
| 158 | #else |
| 159 | #if LLC_SRAM |
| 160 | {PLAT_MARVELL_LLC_SRAM_BASE, PLAT_MARVELL_LLC_SRAM_SIZE, DRAM_0_TID}, |
| 161 | #endif |
| 162 | {0x00000000f2000000, 0xe000000, IO_0_TID}, /* IO window */ |
| 163 | {0x00000000c0000000, 0x30000000, IO_0_TID}, /* IO window */ |
| 164 | {0x0000002000000000, 0x70e000000, IO_0_TID}, /* IO for CV-OS */ |
| 165 | #endif |
| 166 | }; |
| 167 | |
| 168 | uint32_t marvell_get_ccu_gcr_target(int ap) |
| 169 | { |
| 170 | return DRAM_0_TID; |
| 171 | } |
| 172 | |
| 173 | int marvell_get_ccu_memory_map(int ap_index, struct addr_map_win **win, |
| 174 | uint32_t *size) |
| 175 | { |
| 176 | *win = ccu_memory_map; |
| 177 | *size = ARRAY_SIZE(ccu_memory_map); |
| 178 | |
| 179 | return 0; |
| 180 | } |
| 181 | |
| 182 | #ifdef IMAGE_BLE |
| 183 | /***************************************************************************** |
| 184 | * SKIP IMAGE Configuration |
| 185 | ***************************************************************************** |
| 186 | */ |
| 187 | void *plat_get_skip_image_data(void) |
| 188 | { |
| 189 | /* No recovery button on CN-9130 board? */ |
| 190 | return NULL; |
| 191 | } |
| 192 | #endif |