Varun Wadekar | cd5a2f5 | 2015-09-20 15:08:22 +0530 | [diff] [blame] | 1 | /* |
Varun Wadekar | 13e7dc4 | 2015-12-30 15:15:08 -0800 | [diff] [blame] | 2 | * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. |
Varun Wadekar | cd5a2f5 | 2015-09-20 15:08:22 +0530 | [diff] [blame] | 3 | * |
| 4 | * Redistribution and use in source and binary forms, with or without |
| 5 | * modification, are permitted provided that the following conditions are met: |
| 6 | * |
| 7 | * Redistributions of source code must retain the above copyright notice, this |
| 8 | * list of conditions and the following disclaimer. |
| 9 | * |
| 10 | * Redistributions in binary form must reproduce the above copyright notice, |
| 11 | * this list of conditions and the following disclaimer in the documentation |
| 12 | * and/or other materials provided with the distribution. |
| 13 | * |
| 14 | * Neither the name of ARM nor the names of its contributors may be used |
| 15 | * to endorse or promote products derived from this software without specific |
| 16 | * prior written permission. |
| 17 | * |
| 18 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 19 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 21 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
| 22 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 23 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 24 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 25 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 26 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 27 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 28 | * POSSIBILITY OF SUCH DAMAGE. |
| 29 | */ |
| 30 | |
| 31 | #include <arch_helpers.h> |
| 32 | #include <assert.h> |
| 33 | #include <debug.h> |
| 34 | #include <mce.h> |
| 35 | #include <memctrl.h> |
| 36 | #include <memctrl_v2.h> |
| 37 | #include <mmio.h> |
Varun Wadekar | 87e44ff | 2016-03-03 13:22:39 -0800 | [diff] [blame] | 38 | #include <smmu.h> |
Varun Wadekar | cd5a2f5 | 2015-09-20 15:08:22 +0530 | [diff] [blame] | 39 | #include <string.h> |
| 40 | #include <tegra_def.h> |
| 41 | #include <xlat_tables.h> |
| 42 | |
Varun Wadekar | e60f1bf | 2016-02-17 10:10:50 -0800 | [diff] [blame] | 43 | #define TEGRA_GPU_RESET_REG_OFFSET 0x30 |
| 44 | #define GPU_RESET_BIT (1 << 0) |
| 45 | |
Varun Wadekar | cd5a2f5 | 2015-09-20 15:08:22 +0530 | [diff] [blame] | 46 | /* Video Memory base and size (live values) */ |
| 47 | static uint64_t video_mem_base; |
| 48 | static uint64_t video_mem_size; |
| 49 | |
| 50 | /* array to hold stream_id override config register offsets */ |
| 51 | const static uint32_t streamid_overrides[] = { |
| 52 | MC_STREAMID_OVERRIDE_CFG_PTCR, |
| 53 | MC_STREAMID_OVERRIDE_CFG_AFIR, |
| 54 | MC_STREAMID_OVERRIDE_CFG_HDAR, |
| 55 | MC_STREAMID_OVERRIDE_CFG_HOST1XDMAR, |
| 56 | MC_STREAMID_OVERRIDE_CFG_NVENCSRD, |
| 57 | MC_STREAMID_OVERRIDE_CFG_SATAR, |
| 58 | MC_STREAMID_OVERRIDE_CFG_MPCORER, |
| 59 | MC_STREAMID_OVERRIDE_CFG_NVENCSWR, |
| 60 | MC_STREAMID_OVERRIDE_CFG_AFIW, |
| 61 | MC_STREAMID_OVERRIDE_CFG_SATAW, |
| 62 | MC_STREAMID_OVERRIDE_CFG_MPCOREW, |
| 63 | MC_STREAMID_OVERRIDE_CFG_SATAW, |
| 64 | MC_STREAMID_OVERRIDE_CFG_HDAW, |
| 65 | MC_STREAMID_OVERRIDE_CFG_ISPRA, |
| 66 | MC_STREAMID_OVERRIDE_CFG_ISPWA, |
| 67 | MC_STREAMID_OVERRIDE_CFG_ISPWB, |
| 68 | MC_STREAMID_OVERRIDE_CFG_XUSB_HOSTR, |
| 69 | MC_STREAMID_OVERRIDE_CFG_XUSB_HOSTW, |
| 70 | MC_STREAMID_OVERRIDE_CFG_XUSB_DEVR, |
| 71 | MC_STREAMID_OVERRIDE_CFG_XUSB_DEVW, |
| 72 | MC_STREAMID_OVERRIDE_CFG_TSECSRD, |
| 73 | MC_STREAMID_OVERRIDE_CFG_TSECSWR, |
| 74 | MC_STREAMID_OVERRIDE_CFG_GPUSRD, |
| 75 | MC_STREAMID_OVERRIDE_CFG_GPUSWR, |
| 76 | MC_STREAMID_OVERRIDE_CFG_SDMMCRA, |
| 77 | MC_STREAMID_OVERRIDE_CFG_SDMMCRAA, |
| 78 | MC_STREAMID_OVERRIDE_CFG_SDMMCR, |
| 79 | MC_STREAMID_OVERRIDE_CFG_SDMMCRAB, |
| 80 | MC_STREAMID_OVERRIDE_CFG_SDMMCWA, |
| 81 | MC_STREAMID_OVERRIDE_CFG_SDMMCWAA, |
| 82 | MC_STREAMID_OVERRIDE_CFG_SDMMCW, |
| 83 | MC_STREAMID_OVERRIDE_CFG_SDMMCWAB, |
| 84 | MC_STREAMID_OVERRIDE_CFG_VICSRD, |
| 85 | MC_STREAMID_OVERRIDE_CFG_VICSWR, |
| 86 | MC_STREAMID_OVERRIDE_CFG_VIW, |
| 87 | MC_STREAMID_OVERRIDE_CFG_NVDECSRD, |
| 88 | MC_STREAMID_OVERRIDE_CFG_NVDECSWR, |
| 89 | MC_STREAMID_OVERRIDE_CFG_APER, |
| 90 | MC_STREAMID_OVERRIDE_CFG_APEW, |
| 91 | MC_STREAMID_OVERRIDE_CFG_NVJPGSRD, |
| 92 | MC_STREAMID_OVERRIDE_CFG_NVJPGSWR, |
| 93 | MC_STREAMID_OVERRIDE_CFG_SESRD, |
| 94 | MC_STREAMID_OVERRIDE_CFG_SESWR, |
| 95 | MC_STREAMID_OVERRIDE_CFG_ETRR, |
| 96 | MC_STREAMID_OVERRIDE_CFG_ETRW, |
| 97 | MC_STREAMID_OVERRIDE_CFG_TSECSRDB, |
| 98 | MC_STREAMID_OVERRIDE_CFG_TSECSWRB, |
| 99 | MC_STREAMID_OVERRIDE_CFG_GPUSRD2, |
| 100 | MC_STREAMID_OVERRIDE_CFG_GPUSWR2, |
| 101 | MC_STREAMID_OVERRIDE_CFG_AXISR, |
| 102 | MC_STREAMID_OVERRIDE_CFG_AXISW, |
| 103 | MC_STREAMID_OVERRIDE_CFG_EQOSR, |
| 104 | MC_STREAMID_OVERRIDE_CFG_EQOSW, |
| 105 | MC_STREAMID_OVERRIDE_CFG_UFSHCR, |
| 106 | MC_STREAMID_OVERRIDE_CFG_UFSHCW, |
| 107 | MC_STREAMID_OVERRIDE_CFG_NVDISPLAYR, |
| 108 | MC_STREAMID_OVERRIDE_CFG_BPMPR, |
| 109 | MC_STREAMID_OVERRIDE_CFG_BPMPW, |
| 110 | MC_STREAMID_OVERRIDE_CFG_BPMPDMAR, |
| 111 | MC_STREAMID_OVERRIDE_CFG_BPMPDMAW, |
| 112 | MC_STREAMID_OVERRIDE_CFG_AONR, |
| 113 | MC_STREAMID_OVERRIDE_CFG_AONW, |
| 114 | MC_STREAMID_OVERRIDE_CFG_AONDMAR, |
| 115 | MC_STREAMID_OVERRIDE_CFG_AONDMAW, |
| 116 | MC_STREAMID_OVERRIDE_CFG_SCER, |
| 117 | MC_STREAMID_OVERRIDE_CFG_SCEW, |
| 118 | MC_STREAMID_OVERRIDE_CFG_SCEDMAR, |
| 119 | MC_STREAMID_OVERRIDE_CFG_SCEDMAW, |
| 120 | MC_STREAMID_OVERRIDE_CFG_APEDMAR, |
| 121 | MC_STREAMID_OVERRIDE_CFG_APEDMAW, |
| 122 | MC_STREAMID_OVERRIDE_CFG_NVDISPLAYR1, |
| 123 | MC_STREAMID_OVERRIDE_CFG_VICSRD1, |
| 124 | MC_STREAMID_OVERRIDE_CFG_NVDECSRD1 |
| 125 | }; |
| 126 | |
| 127 | /* array to hold the security configs for stream IDs */ |
| 128 | const static mc_streamid_security_cfg_t sec_cfgs[] = { |
Varun Wadekar | de729d6 | 2016-02-17 10:01:28 -0800 | [diff] [blame] | 129 | mc_make_sec_cfg(SCEW, NON_SECURE, NO_OVERRIDE, ENABLE), |
Varun Wadekar | cd5a2f5 | 2015-09-20 15:08:22 +0530 | [diff] [blame] | 130 | mc_make_sec_cfg(AFIR, NON_SECURE, OVERRIDE, ENABLE), |
| 131 | mc_make_sec_cfg(NVDISPLAYR1, NON_SECURE, OVERRIDE, ENABLE), |
| 132 | mc_make_sec_cfg(XUSB_DEVR, NON_SECURE, OVERRIDE, ENABLE), |
| 133 | mc_make_sec_cfg(VICSRD1, NON_SECURE, NO_OVERRIDE, ENABLE), |
| 134 | mc_make_sec_cfg(NVENCSWR, NON_SECURE, NO_OVERRIDE, ENABLE), |
| 135 | mc_make_sec_cfg(TSECSRDB, NON_SECURE, NO_OVERRIDE, ENABLE), |
| 136 | mc_make_sec_cfg(AXISW, SECURE, NO_OVERRIDE, DISABLE), |
| 137 | mc_make_sec_cfg(SDMMCWAB, NON_SECURE, OVERRIDE, ENABLE), |
| 138 | mc_make_sec_cfg(AONDMAW, NON_SECURE, OVERRIDE, ENABLE), |
| 139 | mc_make_sec_cfg(GPUSWR2, SECURE, NO_OVERRIDE, DISABLE), |
| 140 | mc_make_sec_cfg(SATAW, NON_SECURE, OVERRIDE, ENABLE), |
| 141 | mc_make_sec_cfg(UFSHCW, NON_SECURE, OVERRIDE, ENABLE), |
| 142 | mc_make_sec_cfg(AFIW, NON_SECURE, OVERRIDE, ENABLE), |
| 143 | mc_make_sec_cfg(SDMMCR, NON_SECURE, OVERRIDE, ENABLE), |
Varun Wadekar | de729d6 | 2016-02-17 10:01:28 -0800 | [diff] [blame] | 144 | mc_make_sec_cfg(SCEDMAW, NON_SECURE, NO_OVERRIDE, ENABLE), |
Varun Wadekar | cd5a2f5 | 2015-09-20 15:08:22 +0530 | [diff] [blame] | 145 | mc_make_sec_cfg(UFSHCR, NON_SECURE, OVERRIDE, ENABLE), |
| 146 | mc_make_sec_cfg(SDMMCWAA, NON_SECURE, OVERRIDE, ENABLE), |
Varun Wadekar | cd5a2f5 | 2015-09-20 15:08:22 +0530 | [diff] [blame] | 147 | mc_make_sec_cfg(SESWR, NON_SECURE, OVERRIDE, ENABLE), |
| 148 | mc_make_sec_cfg(MPCORER, NON_SECURE, OVERRIDE, ENABLE), |
| 149 | mc_make_sec_cfg(PTCR, NON_SECURE, OVERRIDE, ENABLE), |
| 150 | mc_make_sec_cfg(BPMPW, NON_SECURE, NO_OVERRIDE, ENABLE), |
| 151 | mc_make_sec_cfg(ETRW, NON_SECURE, OVERRIDE, ENABLE), |
| 152 | mc_make_sec_cfg(GPUSRD, SECURE, NO_OVERRIDE, DISABLE), |
| 153 | mc_make_sec_cfg(VICSWR, NON_SECURE, NO_OVERRIDE, ENABLE), |
Varun Wadekar | de729d6 | 2016-02-17 10:01:28 -0800 | [diff] [blame] | 154 | mc_make_sec_cfg(SCEDMAR, NON_SECURE, NO_OVERRIDE, ENABLE), |
Varun Wadekar | cd5a2f5 | 2015-09-20 15:08:22 +0530 | [diff] [blame] | 155 | mc_make_sec_cfg(HDAW, NON_SECURE, OVERRIDE, ENABLE), |
| 156 | mc_make_sec_cfg(ISPWA, NON_SECURE, OVERRIDE, ENABLE), |
| 157 | mc_make_sec_cfg(EQOSW, NON_SECURE, OVERRIDE, ENABLE), |
| 158 | mc_make_sec_cfg(XUSB_HOSTW, NON_SECURE, OVERRIDE, ENABLE), |
| 159 | mc_make_sec_cfg(TSECSWR, NON_SECURE, NO_OVERRIDE, ENABLE), |
| 160 | mc_make_sec_cfg(SDMMCRAA, NON_SECURE, OVERRIDE, ENABLE), |
Varun Wadekar | cd5a2f5 | 2015-09-20 15:08:22 +0530 | [diff] [blame] | 161 | mc_make_sec_cfg(VIW, NON_SECURE, OVERRIDE, ENABLE), |
Varun Wadekar | cd5a2f5 | 2015-09-20 15:08:22 +0530 | [diff] [blame] | 162 | mc_make_sec_cfg(AXISR, SECURE, NO_OVERRIDE, DISABLE), |
| 163 | mc_make_sec_cfg(SDMMCW, NON_SECURE, OVERRIDE, ENABLE), |
| 164 | mc_make_sec_cfg(BPMPDMAW, NON_SECURE, NO_OVERRIDE, ENABLE), |
| 165 | mc_make_sec_cfg(ISPRA, NON_SECURE, OVERRIDE, ENABLE), |
| 166 | mc_make_sec_cfg(NVDECSWR, NON_SECURE, NO_OVERRIDE, ENABLE), |
| 167 | mc_make_sec_cfg(XUSB_DEVW, NON_SECURE, OVERRIDE, ENABLE), |
| 168 | mc_make_sec_cfg(NVDECSRD, NON_SECURE, NO_OVERRIDE, ENABLE), |
| 169 | mc_make_sec_cfg(MPCOREW, NON_SECURE, OVERRIDE, ENABLE), |
| 170 | mc_make_sec_cfg(NVDISPLAYR, NON_SECURE, OVERRIDE, ENABLE), |
| 171 | mc_make_sec_cfg(BPMPDMAR, NON_SECURE, NO_OVERRIDE, ENABLE), |
| 172 | mc_make_sec_cfg(NVJPGSWR, NON_SECURE, NO_OVERRIDE, ENABLE), |
| 173 | mc_make_sec_cfg(NVDECSRD1, NON_SECURE, NO_OVERRIDE, ENABLE), |
| 174 | mc_make_sec_cfg(TSECSRD, NON_SECURE, NO_OVERRIDE, ENABLE), |
| 175 | mc_make_sec_cfg(NVJPGSRD, NON_SECURE, NO_OVERRIDE, ENABLE), |
| 176 | mc_make_sec_cfg(SDMMCWA, NON_SECURE, OVERRIDE, ENABLE), |
Varun Wadekar | de729d6 | 2016-02-17 10:01:28 -0800 | [diff] [blame] | 177 | mc_make_sec_cfg(SCER, NON_SECURE, NO_OVERRIDE, ENABLE), |
Varun Wadekar | cd5a2f5 | 2015-09-20 15:08:22 +0530 | [diff] [blame] | 178 | mc_make_sec_cfg(XUSB_HOSTR, NON_SECURE, OVERRIDE, ENABLE), |
| 179 | mc_make_sec_cfg(VICSRD, NON_SECURE, NO_OVERRIDE, ENABLE), |
| 180 | mc_make_sec_cfg(AONDMAR, NON_SECURE, OVERRIDE, ENABLE), |
| 181 | mc_make_sec_cfg(AONW, NON_SECURE, OVERRIDE, ENABLE), |
| 182 | mc_make_sec_cfg(SDMMCRA, NON_SECURE, OVERRIDE, ENABLE), |
| 183 | mc_make_sec_cfg(HOST1XDMAR, NON_SECURE, NO_OVERRIDE, ENABLE), |
| 184 | mc_make_sec_cfg(EQOSR, NON_SECURE, OVERRIDE, ENABLE), |
| 185 | mc_make_sec_cfg(SATAR, NON_SECURE, OVERRIDE, ENABLE), |
| 186 | mc_make_sec_cfg(BPMPR, NON_SECURE, NO_OVERRIDE, ENABLE), |
| 187 | mc_make_sec_cfg(HDAR, NON_SECURE, OVERRIDE, ENABLE), |
| 188 | mc_make_sec_cfg(SDMMCRAB, NON_SECURE, OVERRIDE, ENABLE), |
| 189 | mc_make_sec_cfg(ETRR, NON_SECURE, OVERRIDE, ENABLE), |
| 190 | mc_make_sec_cfg(AONR, NON_SECURE, OVERRIDE, ENABLE), |
Varun Wadekar | cd5a2f5 | 2015-09-20 15:08:22 +0530 | [diff] [blame] | 191 | mc_make_sec_cfg(SESRD, NON_SECURE, OVERRIDE, ENABLE), |
| 192 | mc_make_sec_cfg(NVENCSRD, NON_SECURE, NO_OVERRIDE, ENABLE), |
| 193 | mc_make_sec_cfg(GPUSWR, SECURE, NO_OVERRIDE, DISABLE), |
| 194 | mc_make_sec_cfg(TSECSWRB, NON_SECURE, NO_OVERRIDE, ENABLE), |
| 195 | mc_make_sec_cfg(ISPWB, NON_SECURE, OVERRIDE, ENABLE), |
| 196 | mc_make_sec_cfg(GPUSRD2, SECURE, NO_OVERRIDE, DISABLE), |
Varun Wadekar | 9610573 | 2016-03-28 14:28:09 -0700 | [diff] [blame] | 197 | #if ENABLE_CHIP_VERIFICATION_HARNESS |
| 198 | mc_make_sec_cfg(APEDMAW, NON_SECURE, OVERRIDE, ENABLE), |
| 199 | mc_make_sec_cfg(APER, NON_SECURE, OVERRIDE, ENABLE), |
| 200 | mc_make_sec_cfg(APEW, NON_SECURE, OVERRIDE, ENABLE), |
| 201 | mc_make_sec_cfg(APEDMAR, NON_SECURE, OVERRIDE, ENABLE), |
| 202 | #else |
| 203 | mc_make_sec_cfg(APEDMAW, NON_SECURE, NO_OVERRIDE, ENABLE), |
| 204 | mc_make_sec_cfg(APER, NON_SECURE, NO_OVERRIDE, ENABLE), |
| 205 | mc_make_sec_cfg(APEW, NON_SECURE, NO_OVERRIDE, ENABLE), |
| 206 | mc_make_sec_cfg(APEDMAR, NON_SECURE, NO_OVERRIDE, ENABLE), |
| 207 | #endif |
Varun Wadekar | cd5a2f5 | 2015-09-20 15:08:22 +0530 | [diff] [blame] | 208 | }; |
| 209 | |
Varun Wadekar | c9ac3e4 | 2016-02-17 15:07:49 -0800 | [diff] [blame] | 210 | const static mc_txn_override_cfg_t mc_override_cfgs[] = { |
| 211 | mc_make_txn_override_cfg(BPMPW, CGID_TAG_ADR), |
| 212 | mc_make_txn_override_cfg(EQOSW, CGID_TAG_ADR), |
| 213 | mc_make_txn_override_cfg(NVJPGSWR, CGID_TAG_ADR), |
| 214 | mc_make_txn_override_cfg(SDMMCWAA, CGID_TAG_ADR), |
| 215 | mc_make_txn_override_cfg(MPCOREW, CGID_TAG_ADR), |
| 216 | mc_make_txn_override_cfg(SCEDMAW, CGID_TAG_ADR), |
| 217 | mc_make_txn_override_cfg(SDMMCW, CGID_TAG_ADR), |
| 218 | mc_make_txn_override_cfg(AXISW, CGID_TAG_ADR), |
| 219 | mc_make_txn_override_cfg(TSECSWR, CGID_TAG_ADR), |
| 220 | mc_make_txn_override_cfg(GPUSWR, CGID_TAG_ADR), |
| 221 | mc_make_txn_override_cfg(XUSB_HOSTW, CGID_TAG_ADR), |
| 222 | mc_make_txn_override_cfg(TSECSWRB, CGID_TAG_ADR), |
| 223 | mc_make_txn_override_cfg(GPUSWR2, CGID_TAG_ADR), |
| 224 | mc_make_txn_override_cfg(AONDMAW, CGID_TAG_ADR), |
| 225 | mc_make_txn_override_cfg(AONW, CGID_TAG_ADR), |
| 226 | mc_make_txn_override_cfg(SESWR, CGID_TAG_ADR), |
| 227 | mc_make_txn_override_cfg(BPMPDMAW, CGID_TAG_ADR), |
| 228 | mc_make_txn_override_cfg(SDMMCWA, CGID_TAG_ADR), |
| 229 | mc_make_txn_override_cfg(HDAW, CGID_TAG_ADR), |
| 230 | mc_make_txn_override_cfg(NVDECSWR, CGID_TAG_ADR), |
| 231 | mc_make_txn_override_cfg(UFSHCW, CGID_TAG_ADR), |
| 232 | mc_make_txn_override_cfg(SATAW, CGID_TAG_ADR), |
| 233 | mc_make_txn_override_cfg(ETRW, CGID_TAG_ADR), |
| 234 | mc_make_txn_override_cfg(VICSWR, CGID_TAG_ADR), |
| 235 | mc_make_txn_override_cfg(NVENCSWR, CGID_TAG_ADR), |
| 236 | mc_make_txn_override_cfg(SDMMCWAB, CGID_TAG_ADR), |
| 237 | mc_make_txn_override_cfg(ISPWB, CGID_TAG_ADR), |
| 238 | mc_make_txn_override_cfg(APEW, CGID_TAG_ADR), |
| 239 | mc_make_txn_override_cfg(XUSB_DEVW, CGID_TAG_ADR), |
| 240 | mc_make_txn_override_cfg(AFIW, CGID_TAG_ADR), |
| 241 | mc_make_txn_override_cfg(SCEW, CGID_TAG_ADR), |
| 242 | }; |
| 243 | |
Varun Wadekar | a0f2697 | 2016-03-11 17:18:51 -0800 | [diff] [blame] | 244 | static void tegra_memctrl_reconfig_mss_clients(void) |
| 245 | { |
| 246 | #if ENABLE_ROC_FOR_ORDERING_CLIENT_REQUESTS |
| 247 | uint32_t val, wdata_0, wdata_1; |
| 248 | |
| 249 | /* |
| 250 | * Assert Memory Controller's HOTRESET_FLUSH_ENABLE signal for |
| 251 | * boot and strongly ordered MSS clients to flush existing memory |
| 252 | * traffic and stall future requests. |
| 253 | */ |
| 254 | val = tegra_mc_read_32(MC_CLIENT_HOTRESET_CTRL0); |
| 255 | assert(val == MC_CLIENT_HOTRESET_CTRL0_RESET_VAL); |
| 256 | |
| 257 | wdata_0 = MC_CLIENT_HOTRESET_CTRL0_AFI_FLUSH_ENB | |
| 258 | MC_CLIENT_HOTRESET_CTRL0_HDA_FLUSH_ENB | |
| 259 | MC_CLIENT_HOTRESET_CTRL0_SATA_FLUSH_ENB | |
| 260 | MC_CLIENT_HOTRESET_CTRL0_XUSB_HOST_FLUSH_ENB | |
| 261 | MC_CLIENT_HOTRESET_CTRL0_XUSB_DEV_FLUSH_ENB; |
| 262 | tegra_mc_write_32(MC_CLIENT_HOTRESET_CTRL0, wdata_0); |
| 263 | |
| 264 | /* Wait for HOTRESET STATUS to indicate FLUSH_DONE */ |
| 265 | do { |
| 266 | val = tegra_mc_read_32(MC_CLIENT_HOTRESET_STATUS0); |
| 267 | } while ((val & wdata_0) != wdata_0); |
| 268 | |
| 269 | /* Wait one more time due to SW WAR for known legacy issue */ |
| 270 | do { |
| 271 | val = tegra_mc_read_32(MC_CLIENT_HOTRESET_STATUS0); |
| 272 | } while ((val & wdata_0) != wdata_0); |
| 273 | |
| 274 | val = tegra_mc_read_32(MC_CLIENT_HOTRESET_CTRL1); |
| 275 | assert(val == MC_CLIENT_HOTRESET_CTRL1_RESET_VAL); |
| 276 | |
| 277 | wdata_1 = MC_CLIENT_HOTRESET_CTRL1_SDMMC4A_FLUSH_ENB | |
| 278 | MC_CLIENT_HOTRESET_CTRL1_APE_FLUSH_ENB | |
| 279 | MC_CLIENT_HOTRESET_CTRL1_SE_FLUSH_ENB | |
| 280 | MC_CLIENT_HOTRESET_CTRL1_ETR_FLUSH_ENB | |
| 281 | MC_CLIENT_HOTRESET_CTRL1_AXIS_FLUSH_ENB | |
| 282 | MC_CLIENT_HOTRESET_CTRL1_EQOS_FLUSH_ENB | |
| 283 | MC_CLIENT_HOTRESET_CTRL1_UFSHC_FLUSH_ENB | |
| 284 | MC_CLIENT_HOTRESET_CTRL1_BPMP_FLUSH_ENB | |
| 285 | MC_CLIENT_HOTRESET_CTRL1_AON_FLUSH_ENB | |
| 286 | MC_CLIENT_HOTRESET_CTRL1_SCE_FLUSH_ENB; |
| 287 | tegra_mc_write_32(MC_CLIENT_HOTRESET_CTRL1, wdata_1); |
| 288 | |
| 289 | /* Wait for HOTRESET STATUS to indicate FLUSH_DONE */ |
| 290 | do { |
| 291 | val = tegra_mc_read_32(MC_CLIENT_HOTRESET_STATUS1); |
| 292 | } while ((val & wdata_1) != wdata_1); |
| 293 | |
| 294 | /* Wait one more time due to SW WAR for known legacy issue */ |
| 295 | do { |
| 296 | val = tegra_mc_read_32(MC_CLIENT_HOTRESET_STATUS1); |
| 297 | } while ((val & wdata_1) != wdata_1); |
| 298 | |
| 299 | /* |
| 300 | * Change MEMTYPE_OVERRIDE from SO_DEV -> PASSTHRU for boot and |
| 301 | * strongly ordered MSS clients. ROC needs to be single point |
| 302 | * of control on overriding the memory type. So, remove TSA's |
| 303 | * memtype override. |
| 304 | */ |
| 305 | mc_set_tsa_passthrough(AFIW); |
| 306 | mc_set_tsa_passthrough(HDAW); |
| 307 | mc_set_tsa_passthrough(SATAW); |
| 308 | mc_set_tsa_passthrough(XUSB_HOSTW); |
| 309 | mc_set_tsa_passthrough(XUSB_DEVW); |
| 310 | mc_set_tsa_passthrough(SDMMCWAB); |
| 311 | mc_set_tsa_passthrough(APEDMAW); |
| 312 | mc_set_tsa_passthrough(SESWR); |
| 313 | mc_set_tsa_passthrough(ETRW); |
| 314 | mc_set_tsa_passthrough(AXISW); |
| 315 | mc_set_tsa_passthrough(EQOSW); |
| 316 | mc_set_tsa_passthrough(UFSHCW); |
| 317 | mc_set_tsa_passthrough(BPMPDMAW); |
| 318 | mc_set_tsa_passthrough(AONDMAW); |
| 319 | mc_set_tsa_passthrough(SCEDMAW); |
| 320 | |
| 321 | /* |
| 322 | * Change COH_PATH_OVERRIDE_SO_DEV from NO_OVERRIDE -> FORCE_COHERENT |
| 323 | * for boot and strongly ordered MSS clients. This steers all sodev |
| 324 | * transactions to ROC. |
| 325 | * |
| 326 | * Change AXID_OVERRIDE/AXID_OVERRIDE_SO_DEV only for some clients |
| 327 | * whose AXI IDs we know and trust. |
| 328 | */ |
| 329 | |
| 330 | /* Match AFIW */ |
| 331 | mc_set_forced_coherent_so_dev_cfg(AFIR); |
| 332 | |
| 333 | /* |
| 334 | * See bug 200131110 comment #35 - there are no normal requests |
| 335 | * and AWID for SO/DEV requests is hardcoded in RTL for a |
| 336 | * particular PCIE controller |
| 337 | */ |
| 338 | mc_set_forced_coherent_so_dev_cfg(AFIW); |
| 339 | mc_set_forced_coherent_cfg(HDAR); |
| 340 | mc_set_forced_coherent_cfg(HDAW); |
| 341 | mc_set_forced_coherent_cfg(SATAR); |
| 342 | mc_set_forced_coherent_cfg(SATAW); |
| 343 | mc_set_forced_coherent_cfg(XUSB_HOSTR); |
| 344 | mc_set_forced_coherent_cfg(XUSB_HOSTW); |
| 345 | mc_set_forced_coherent_cfg(XUSB_DEVR); |
| 346 | mc_set_forced_coherent_cfg(XUSB_DEVW); |
| 347 | mc_set_forced_coherent_cfg(SDMMCRAB); |
| 348 | mc_set_forced_coherent_cfg(SDMMCWAB); |
| 349 | |
| 350 | /* Match APEDMAW */ |
| 351 | mc_set_forced_coherent_axid_so_dev_cfg(APEDMAR); |
| 352 | |
| 353 | /* |
| 354 | * See bug 200131110 comment #35 - AWID for normal requests |
| 355 | * is 0x80 and AWID for SO/DEV requests is 0x01 |
| 356 | */ |
| 357 | mc_set_forced_coherent_axid_so_dev_cfg(APEDMAW); |
| 358 | mc_set_forced_coherent_cfg(SESRD); |
| 359 | mc_set_forced_coherent_cfg(SESWR); |
| 360 | mc_set_forced_coherent_cfg(ETRR); |
| 361 | mc_set_forced_coherent_cfg(ETRW); |
| 362 | mc_set_forced_coherent_cfg(AXISR); |
| 363 | mc_set_forced_coherent_cfg(AXISW); |
| 364 | mc_set_forced_coherent_cfg(EQOSR); |
| 365 | mc_set_forced_coherent_cfg(EQOSW); |
| 366 | mc_set_forced_coherent_cfg(UFSHCR); |
| 367 | mc_set_forced_coherent_cfg(UFSHCW); |
| 368 | mc_set_forced_coherent_cfg(BPMPDMAR); |
| 369 | mc_set_forced_coherent_cfg(BPMPDMAW); |
| 370 | mc_set_forced_coherent_cfg(AONDMAR); |
| 371 | mc_set_forced_coherent_cfg(AONDMAW); |
| 372 | mc_set_forced_coherent_cfg(SCEDMAR); |
| 373 | mc_set_forced_coherent_cfg(SCEDMAW); |
| 374 | |
| 375 | /* |
| 376 | * At this point, ordering can occur at ROC. So, remove PCFIFO's |
| 377 | * control over ordering requests. |
| 378 | * |
| 379 | * Change PCFIFO_*_ORDERED_CLIENT from ORDERED -> UNORDERED for |
| 380 | * boot and strongly ordered MSS clients |
| 381 | */ |
| 382 | val = MC_PCFIFO_CLIENT_CONFIG1_RESET_VAL & |
| 383 | mc_set_pcfifo_unordered_boot_so_mss(1, AFIW) & |
| 384 | mc_set_pcfifo_unordered_boot_so_mss(1, HDAW) & |
| 385 | mc_set_pcfifo_unordered_boot_so_mss(1, SATAW); |
| 386 | tegra_mc_write_32(MC_PCFIFO_CLIENT_CONFIG1, val); |
| 387 | |
| 388 | val = MC_PCFIFO_CLIENT_CONFIG2_RESET_VAL & |
| 389 | mc_set_pcfifo_unordered_boot_so_mss(2, XUSB_HOSTW) & |
| 390 | mc_set_pcfifo_unordered_boot_so_mss(2, XUSB_DEVW); |
| 391 | tegra_mc_write_32(MC_PCFIFO_CLIENT_CONFIG2, val); |
| 392 | |
| 393 | val = MC_PCFIFO_CLIENT_CONFIG3_RESET_VAL & |
| 394 | mc_set_pcfifo_unordered_boot_so_mss(3, SDMMCWAB); |
| 395 | tegra_mc_write_32(MC_PCFIFO_CLIENT_CONFIG3, val); |
| 396 | |
| 397 | val = MC_PCFIFO_CLIENT_CONFIG4_RESET_VAL & |
| 398 | mc_set_pcfifo_unordered_boot_so_mss(4, SESWR) & |
| 399 | mc_set_pcfifo_unordered_boot_so_mss(4, ETRW) & |
| 400 | mc_set_pcfifo_unordered_boot_so_mss(4, AXISW) & |
| 401 | mc_set_pcfifo_unordered_boot_so_mss(4, EQOSW) & |
| 402 | mc_set_pcfifo_unordered_boot_so_mss(4, UFSHCW) & |
| 403 | mc_set_pcfifo_unordered_boot_so_mss(4, BPMPDMAW) & |
| 404 | mc_set_pcfifo_unordered_boot_so_mss(4, AONDMAW) & |
| 405 | mc_set_pcfifo_unordered_boot_so_mss(4, SCEDMAW); |
| 406 | tegra_mc_write_32(MC_PCFIFO_CLIENT_CONFIG4, val); |
| 407 | |
| 408 | val = MC_PCFIFO_CLIENT_CONFIG5_RESET_VAL & |
| 409 | mc_set_pcfifo_unordered_boot_so_mss(5, APEDMAW); |
| 410 | tegra_mc_write_32(MC_PCFIFO_CLIENT_CONFIG5, val); |
| 411 | |
| 412 | /* |
| 413 | * At this point, ordering can occur at ROC. SMMU need not |
| 414 | * reorder any requests. |
| 415 | * |
| 416 | * Change SMMU_*_ORDERED_CLIENT from ORDERED -> UNORDERED |
| 417 | * for boot and strongly ordered MSS clients |
| 418 | */ |
| 419 | val = MC_SMMU_CLIENT_CONFIG1_RESET_VAL & |
| 420 | mc_set_smmu_unordered_boot_so_mss(1, AFIW) & |
| 421 | mc_set_smmu_unordered_boot_so_mss(1, HDAW) & |
| 422 | mc_set_smmu_unordered_boot_so_mss(1, SATAW); |
| 423 | tegra_mc_write_32(MC_SMMU_CLIENT_CONFIG1, val); |
| 424 | |
| 425 | val = MC_SMMU_CLIENT_CONFIG2_RESET_VAL & |
| 426 | mc_set_smmu_unordered_boot_so_mss(2, XUSB_HOSTW) & |
| 427 | mc_set_smmu_unordered_boot_so_mss(2, XUSB_DEVW); |
| 428 | tegra_mc_write_32(MC_SMMU_CLIENT_CONFIG2, val); |
| 429 | |
| 430 | val = MC_SMMU_CLIENT_CONFIG3_RESET_VAL & |
| 431 | mc_set_smmu_unordered_boot_so_mss(3, SDMMCWAB); |
| 432 | tegra_mc_write_32(MC_SMMU_CLIENT_CONFIG3, val); |
| 433 | |
| 434 | val = MC_SMMU_CLIENT_CONFIG4_RESET_VAL & |
| 435 | mc_set_smmu_unordered_boot_so_mss(4, SESWR) & |
| 436 | mc_set_smmu_unordered_boot_so_mss(4, ETRW) & |
| 437 | mc_set_smmu_unordered_boot_so_mss(4, AXISW) & |
| 438 | mc_set_smmu_unordered_boot_so_mss(4, EQOSW) & |
| 439 | mc_set_smmu_unordered_boot_so_mss(4, UFSHCW) & |
| 440 | mc_set_smmu_unordered_boot_so_mss(4, BPMPDMAW) & |
| 441 | mc_set_smmu_unordered_boot_so_mss(4, AONDMAW) & |
| 442 | mc_set_smmu_unordered_boot_so_mss(4, SCEDMAW); |
| 443 | tegra_mc_write_32(MC_SMMU_CLIENT_CONFIG4, val); |
| 444 | |
| 445 | val = MC_SMMU_CLIENT_CONFIG5_RESET_VAL & |
| 446 | mc_set_smmu_unordered_boot_so_mss(5, APEDMAW); |
| 447 | tegra_mc_write_32(MC_SMMU_CLIENT_CONFIG5, val); |
| 448 | |
| 449 | /* |
| 450 | * Deassert HOTRESET FLUSH_ENABLE for boot and strongly ordered MSS |
| 451 | * clients to allow memory traffic from all clients to start passing |
| 452 | * through ROC |
| 453 | */ |
| 454 | val = tegra_mc_read_32(MC_CLIENT_HOTRESET_CTRL0); |
| 455 | assert(val == wdata_0); |
| 456 | |
| 457 | wdata_0 = MC_CLIENT_HOTRESET_CTRL0_RESET_VAL; |
| 458 | tegra_mc_write_32(MC_CLIENT_HOTRESET_CTRL0, wdata_0); |
| 459 | |
| 460 | /* Wait for HOTRESET STATUS to indicate FLUSH_DONE */ |
| 461 | do { |
| 462 | val = tegra_mc_read_32(MC_CLIENT_HOTRESET_STATUS0); |
| 463 | } while ((val & wdata_0) != wdata_0); |
| 464 | |
| 465 | /* Wait one more time due to SW WAR for known legacy issue */ |
| 466 | do { |
| 467 | val = tegra_mc_read_32(MC_CLIENT_HOTRESET_STATUS0); |
| 468 | } while ((val & wdata_0) != wdata_0); |
| 469 | |
| 470 | val = tegra_mc_read_32(MC_CLIENT_HOTRESET_CTRL1); |
| 471 | assert(val == wdata_1); |
| 472 | |
| 473 | wdata_1 = MC_CLIENT_HOTRESET_CTRL1_RESET_VAL; |
| 474 | tegra_mc_write_32(MC_CLIENT_HOTRESET_CTRL1, wdata_1); |
| 475 | |
| 476 | /* Wait for HOTRESET STATUS to indicate FLUSH_DONE */ |
| 477 | do { |
| 478 | val = tegra_mc_read_32(MC_CLIENT_HOTRESET_STATUS1); |
| 479 | } while ((val & wdata_1) != wdata_1); |
| 480 | |
| 481 | /* Wait one more time due to SW WAR for known legacy issue */ |
| 482 | do { |
| 483 | val = tegra_mc_read_32(MC_CLIENT_HOTRESET_STATUS1); |
| 484 | } while ((val & wdata_1) != wdata_1); |
| 485 | |
| 486 | #endif |
| 487 | } |
| 488 | |
Varun Wadekar | cd5a2f5 | 2015-09-20 15:08:22 +0530 | [diff] [blame] | 489 | /* |
Varun Wadekar | 87e44ff | 2016-03-03 13:22:39 -0800 | [diff] [blame] | 490 | * Init Memory controller during boot. |
Varun Wadekar | cd5a2f5 | 2015-09-20 15:08:22 +0530 | [diff] [blame] | 491 | */ |
| 492 | void tegra_memctrl_setup(void) |
| 493 | { |
| 494 | uint32_t val; |
| 495 | uint32_t num_overrides = sizeof(streamid_overrides) / sizeof(uint32_t); |
| 496 | uint32_t num_sec_cfgs = sizeof(sec_cfgs) / sizeof(mc_streamid_security_cfg_t); |
Varun Wadekar | c9ac3e4 | 2016-02-17 15:07:49 -0800 | [diff] [blame] | 497 | uint32_t num_txn_overrides = sizeof(mc_override_cfgs) / sizeof(mc_txn_override_cfg_t); |
| 498 | uint32_t tegra_rev; |
Varun Wadekar | cd5a2f5 | 2015-09-20 15:08:22 +0530 | [diff] [blame] | 499 | int i; |
| 500 | |
| 501 | INFO("Tegra Memory Controller (v2)\n"); |
| 502 | |
| 503 | /* Program the SMMU pagesize */ |
Varun Wadekar | 87e44ff | 2016-03-03 13:22:39 -0800 | [diff] [blame] | 504 | tegra_smmu_init(); |
Varun Wadekar | cd5a2f5 | 2015-09-20 15:08:22 +0530 | [diff] [blame] | 505 | |
| 506 | /* Program all the Stream ID overrides */ |
| 507 | for (i = 0; i < num_overrides; i++) |
| 508 | tegra_mc_streamid_write_32(streamid_overrides[i], |
| 509 | MC_STREAM_ID_MAX); |
| 510 | |
| 511 | /* Program the security config settings for all Stream IDs */ |
| 512 | for (i = 0; i < num_sec_cfgs; i++) { |
| 513 | val = sec_cfgs[i].override_enable << 16 | |
| 514 | sec_cfgs[i].override_client_inputs << 8 | |
| 515 | sec_cfgs[i].override_client_ns_flag << 0; |
| 516 | tegra_mc_streamid_write_32(sec_cfgs[i].offset, val); |
| 517 | } |
| 518 | |
| 519 | /* |
| 520 | * All requests at boot time, and certain requests during |
| 521 | * normal run time, are physically addressed and must bypass |
| 522 | * the SMMU. The client hub logic implements a hardware bypass |
| 523 | * path around the Translation Buffer Units (TBU). During |
| 524 | * boot-time, the SMMU_BYPASS_CTRL register (which defaults to |
| 525 | * TBU_BYPASS mode) will be used to steer all requests around |
| 526 | * the uninitialized TBUs. During normal operation, this register |
| 527 | * is locked into TBU_BYPASS_SID config, which routes requests |
| 528 | * with special StreamID 0x7f on the bypass path and all others |
| 529 | * through the selected TBU. This is done to disable SMMU Bypass |
| 530 | * mode, as it could be used to circumvent SMMU security checks. |
| 531 | */ |
| 532 | tegra_mc_write_32(MC_SMMU_BYPASS_CONFIG, |
| 533 | MC_SMMU_BYPASS_CONFIG_SETTINGS); |
| 534 | |
Varun Wadekar | c9ac3e4 | 2016-02-17 15:07:49 -0800 | [diff] [blame] | 535 | /* |
Varun Wadekar | a0f2697 | 2016-03-11 17:18:51 -0800 | [diff] [blame] | 536 | * Re-configure MSS to allow ROC to deal with ordering of the |
| 537 | * Memory Controller traffic. This is needed as the Memory Controller |
| 538 | * boots with MSS having all control, but ROC provides a performance |
| 539 | * boost as compared to MSS. |
| 540 | */ |
| 541 | tegra_memctrl_reconfig_mss_clients(); |
| 542 | |
| 543 | /* |
Varun Wadekar | c9ac3e4 | 2016-02-17 15:07:49 -0800 | [diff] [blame] | 544 | * Set the MC_TXN_OVERRIDE registers for write clients. |
| 545 | */ |
| 546 | tegra_rev = (mmio_read_32(TEGRA_MISC_BASE + HARDWARE_REVISION_OFFSET) & |
| 547 | HARDWARE_MINOR_REVISION_MASK) >> HARDWARE_MINOR_REVISION_SHIFT; |
| 548 | |
| 549 | if (tegra_rev == HARDWARE_REVISION_A01) { |
| 550 | |
| 551 | /* GPU and NVENC settings for rev. A01 */ |
| 552 | val = tegra_mc_read_32(MC_TXN_OVERRIDE_CONFIG_GPUSWR); |
| 553 | val &= ~MC_TXN_OVERRIDE_CGID_TAG_MASK; |
| 554 | tegra_mc_write_32(MC_TXN_OVERRIDE_CONFIG_GPUSWR, |
| 555 | val | MC_TXN_OVERRIDE_CGID_TAG_ZERO); |
| 556 | |
| 557 | val = tegra_mc_read_32(MC_TXN_OVERRIDE_CONFIG_GPUSWR2); |
| 558 | val &= ~MC_TXN_OVERRIDE_CGID_TAG_MASK; |
| 559 | tegra_mc_write_32(MC_TXN_OVERRIDE_CONFIG_GPUSWR2, |
| 560 | val | MC_TXN_OVERRIDE_CGID_TAG_ZERO); |
| 561 | |
| 562 | val = tegra_mc_read_32(MC_TXN_OVERRIDE_CONFIG_NVENCSWR); |
| 563 | val &= ~MC_TXN_OVERRIDE_CGID_TAG_MASK; |
| 564 | tegra_mc_write_32(MC_TXN_OVERRIDE_CONFIG_NVENCSWR, |
| 565 | val | MC_TXN_OVERRIDE_CGID_TAG_CLIENT_AXI_ID); |
| 566 | |
| 567 | } else { |
| 568 | |
| 569 | /* settings for rev. A02 */ |
| 570 | for (i = 0; i < num_txn_overrides; i++) { |
| 571 | val = tegra_mc_read_32(mc_override_cfgs[i].offset); |
| 572 | val &= ~MC_TXN_OVERRIDE_CGID_TAG_MASK; |
| 573 | tegra_mc_write_32(mc_override_cfgs[i].offset, |
| 574 | val | mc_override_cfgs[i].cgid_tag); |
| 575 | } |
| 576 | |
| 577 | } |
Varun Wadekar | 87e44ff | 2016-03-03 13:22:39 -0800 | [diff] [blame] | 578 | } |
Varun Wadekar | c9ac3e4 | 2016-02-17 15:07:49 -0800 | [diff] [blame] | 579 | |
Varun Wadekar | 87e44ff | 2016-03-03 13:22:39 -0800 | [diff] [blame] | 580 | /* |
| 581 | * Restore Memory Controller settings after "System Suspend" |
| 582 | */ |
| 583 | void tegra_memctrl_restore_settings(void) |
| 584 | { |
Varun Wadekar | a0f2697 | 2016-03-11 17:18:51 -0800 | [diff] [blame] | 585 | /* |
| 586 | * Re-configure MSS to allow ROC to deal with ordering of the |
| 587 | * Memory Controller traffic. This is needed as the Memory Controller |
| 588 | * resets during System Suspend with MSS having all control, but ROC |
| 589 | * provides a performance boost as compared to MSS. |
| 590 | */ |
| 591 | tegra_memctrl_reconfig_mss_clients(); |
| 592 | |
Varun Wadekar | cd5a2f5 | 2015-09-20 15:08:22 +0530 | [diff] [blame] | 593 | /* video memory carveout region */ |
| 594 | if (video_mem_base) { |
| 595 | tegra_mc_write_32(MC_VIDEO_PROTECT_BASE_LO, |
| 596 | (uint32_t)video_mem_base); |
| 597 | tegra_mc_write_32(MC_VIDEO_PROTECT_BASE_HI, |
| 598 | (uint32_t)(video_mem_base >> 32)); |
| 599 | tegra_mc_write_32(MC_VIDEO_PROTECT_SIZE_MB, video_mem_size); |
| 600 | |
| 601 | /* |
| 602 | * MCE propogates the VideoMem configuration values across the |
| 603 | * CCPLEX. |
| 604 | */ |
| 605 | mce_update_gsc_videomem(); |
| 606 | } |
| 607 | } |
| 608 | |
| 609 | /* |
| 610 | * Secure the BL31 DRAM aperture. |
| 611 | * |
| 612 | * phys_base = physical base of TZDRAM aperture |
| 613 | * size_in_bytes = size of aperture in bytes |
| 614 | */ |
| 615 | void tegra_memctrl_tzdram_setup(uint64_t phys_base, uint32_t size_in_bytes) |
| 616 | { |
| 617 | /* |
| 618 | * Setup the Memory controller to allow only secure accesses to |
| 619 | * the TZDRAM carveout |
| 620 | */ |
| 621 | INFO("Configuring TrustZone DRAM Memory Carveout\n"); |
| 622 | |
| 623 | tegra_mc_write_32(MC_SECURITY_CFG0_0, (uint32_t)phys_base); |
| 624 | tegra_mc_write_32(MC_SECURITY_CFG3_0, (uint32_t)(phys_base >> 32)); |
| 625 | tegra_mc_write_32(MC_SECURITY_CFG1_0, size_in_bytes >> 20); |
| 626 | |
| 627 | /* |
| 628 | * MCE propogates the security configuration values across the |
| 629 | * CCPLEX. |
| 630 | */ |
| 631 | mce_update_gsc_tzdram(); |
| 632 | } |
| 633 | |
| 634 | /* |
Varun Wadekar | 13e7dc4 | 2015-12-30 15:15:08 -0800 | [diff] [blame] | 635 | * Secure the BL31 TZRAM aperture. |
| 636 | * |
| 637 | * phys_base = physical base of TZRAM aperture |
| 638 | * size_in_bytes = size of aperture in bytes |
| 639 | */ |
| 640 | void tegra_memctrl_tzram_setup(uint64_t phys_base, uint32_t size_in_bytes) |
| 641 | { |
| 642 | uint64_t tzram_end = phys_base + size_in_bytes - 1; |
| 643 | uint32_t val; |
| 644 | |
| 645 | /* |
| 646 | * Check if the TZRAM is locked already. |
| 647 | */ |
| 648 | if (tegra_mc_read_32(MC_TZRAM_REG_CTRL) == DISABLE_TZRAM_ACCESS) |
| 649 | return; |
| 650 | |
| 651 | /* |
| 652 | * Setup the Memory controller to allow only secure accesses to |
| 653 | * the TZRAM carveout |
| 654 | */ |
| 655 | INFO("Configuring TrustZone RAM (SysRAM) Memory Carveout\n"); |
| 656 | |
| 657 | /* Program the base and end values */ |
| 658 | tegra_mc_write_32(MC_TZRAM_BASE, (uint32_t)phys_base); |
| 659 | tegra_mc_write_32(MC_TZRAM_END, (uint32_t)tzram_end); |
| 660 | |
| 661 | /* Extract the high address bits from the base/end values */ |
| 662 | val = (uint32_t)(phys_base >> 32) & TZRAM_ADDR_HI_BITS_MASK; |
| 663 | val |= (((uint32_t)(tzram_end >> 32) << TZRAM_END_HI_BITS_SHIFT) & |
| 664 | TZRAM_ADDR_HI_BITS_MASK); |
| 665 | tegra_mc_write_32(MC_TZRAM_HI_ADDR_BITS, val); |
| 666 | |
| 667 | /* Disable further writes to the TZRAM setup registers */ |
| 668 | tegra_mc_write_32(MC_TZRAM_REG_CTRL, DISABLE_TZRAM_ACCESS); |
| 669 | |
| 670 | /* |
| 671 | * MCE propogates the security configuration values across the |
| 672 | * CCPLEX. |
| 673 | */ |
| 674 | mce_update_gsc_tzram(); |
| 675 | } |
| 676 | |
| 677 | /* |
Varun Wadekar | cd5a2f5 | 2015-09-20 15:08:22 +0530 | [diff] [blame] | 678 | * Program the Video Memory carveout region |
| 679 | * |
| 680 | * phys_base = physical base of aperture |
| 681 | * size_in_bytes = size of aperture in bytes |
| 682 | */ |
| 683 | void tegra_memctrl_videomem_setup(uint64_t phys_base, uint32_t size_in_bytes) |
| 684 | { |
Varun Wadekar | e60f1bf | 2016-02-17 10:10:50 -0800 | [diff] [blame] | 685 | uint32_t regval; |
| 686 | |
| 687 | /* |
| 688 | * The GPU is the user of the Video Memory region. In order to |
| 689 | * transition to the new memory region smoothly, we program the |
| 690 | * new base/size ONLY if the GPU is in reset mode. |
| 691 | */ |
| 692 | regval = mmio_read_32(TEGRA_CAR_RESET_BASE + TEGRA_GPU_RESET_REG_OFFSET); |
| 693 | if ((regval & GPU_RESET_BIT) == 0) { |
| 694 | ERROR("GPU not in reset! Video Memory setup failed\n"); |
| 695 | return; |
| 696 | } |
| 697 | |
Varun Wadekar | cd5a2f5 | 2015-09-20 15:08:22 +0530 | [diff] [blame] | 698 | /* |
| 699 | * Setup the Memory controller to restrict CPU accesses to the Video |
| 700 | * Memory region |
| 701 | */ |
| 702 | INFO("Configuring Video Memory Carveout\n"); |
| 703 | |
| 704 | tegra_mc_write_32(MC_VIDEO_PROTECT_BASE_LO, (uint32_t)phys_base); |
| 705 | tegra_mc_write_32(MC_VIDEO_PROTECT_BASE_HI, |
| 706 | (uint32_t)(phys_base >> 32)); |
| 707 | tegra_mc_write_32(MC_VIDEO_PROTECT_SIZE_MB, size_in_bytes); |
| 708 | |
| 709 | /* store new values */ |
| 710 | video_mem_base = phys_base; |
| 711 | video_mem_size = size_in_bytes >> 20; |
| 712 | |
| 713 | /* |
| 714 | * MCE propogates the VideoMem configuration values across the |
| 715 | * CCPLEX. |
| 716 | */ |
| 717 | mce_update_gsc_videomem(); |
| 718 | } |