Varun Wadekar | cd5a2f5 | 2015-09-20 15:08:22 +0530 | [diff] [blame] | 1 | /* |
Varun Wadekar | 13e7dc4 | 2015-12-30 15:15:08 -0800 | [diff] [blame] | 2 | * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. |
Varun Wadekar | cd5a2f5 | 2015-09-20 15:08:22 +0530 | [diff] [blame] | 3 | * |
| 4 | * Redistribution and use in source and binary forms, with or without |
| 5 | * modification, are permitted provided that the following conditions are met: |
| 6 | * |
| 7 | * Redistributions of source code must retain the above copyright notice, this |
| 8 | * list of conditions and the following disclaimer. |
| 9 | * |
| 10 | * Redistributions in binary form must reproduce the above copyright notice, |
| 11 | * this list of conditions and the following disclaimer in the documentation |
| 12 | * and/or other materials provided with the distribution. |
| 13 | * |
| 14 | * Neither the name of ARM nor the names of its contributors may be used |
| 15 | * to endorse or promote products derived from this software without specific |
| 16 | * prior written permission. |
| 17 | * |
| 18 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 19 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 21 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
| 22 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 23 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 24 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 25 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 26 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 27 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 28 | * POSSIBILITY OF SUCH DAMAGE. |
| 29 | */ |
| 30 | |
| 31 | #include <arch_helpers.h> |
| 32 | #include <assert.h> |
| 33 | #include <debug.h> |
| 34 | #include <mce.h> |
| 35 | #include <memctrl.h> |
| 36 | #include <memctrl_v2.h> |
| 37 | #include <mmio.h> |
| 38 | #include <string.h> |
| 39 | #include <tegra_def.h> |
| 40 | #include <xlat_tables.h> |
| 41 | |
| 42 | /* Video Memory base and size (live values) */ |
| 43 | static uint64_t video_mem_base; |
| 44 | static uint64_t video_mem_size; |
| 45 | |
| 46 | /* array to hold stream_id override config register offsets */ |
| 47 | const static uint32_t streamid_overrides[] = { |
| 48 | MC_STREAMID_OVERRIDE_CFG_PTCR, |
| 49 | MC_STREAMID_OVERRIDE_CFG_AFIR, |
| 50 | MC_STREAMID_OVERRIDE_CFG_HDAR, |
| 51 | MC_STREAMID_OVERRIDE_CFG_HOST1XDMAR, |
| 52 | MC_STREAMID_OVERRIDE_CFG_NVENCSRD, |
| 53 | MC_STREAMID_OVERRIDE_CFG_SATAR, |
| 54 | MC_STREAMID_OVERRIDE_CFG_MPCORER, |
| 55 | MC_STREAMID_OVERRIDE_CFG_NVENCSWR, |
| 56 | MC_STREAMID_OVERRIDE_CFG_AFIW, |
| 57 | MC_STREAMID_OVERRIDE_CFG_SATAW, |
| 58 | MC_STREAMID_OVERRIDE_CFG_MPCOREW, |
| 59 | MC_STREAMID_OVERRIDE_CFG_SATAW, |
| 60 | MC_STREAMID_OVERRIDE_CFG_HDAW, |
| 61 | MC_STREAMID_OVERRIDE_CFG_ISPRA, |
| 62 | MC_STREAMID_OVERRIDE_CFG_ISPWA, |
| 63 | MC_STREAMID_OVERRIDE_CFG_ISPWB, |
| 64 | MC_STREAMID_OVERRIDE_CFG_XUSB_HOSTR, |
| 65 | MC_STREAMID_OVERRIDE_CFG_XUSB_HOSTW, |
| 66 | MC_STREAMID_OVERRIDE_CFG_XUSB_DEVR, |
| 67 | MC_STREAMID_OVERRIDE_CFG_XUSB_DEVW, |
| 68 | MC_STREAMID_OVERRIDE_CFG_TSECSRD, |
| 69 | MC_STREAMID_OVERRIDE_CFG_TSECSWR, |
| 70 | MC_STREAMID_OVERRIDE_CFG_GPUSRD, |
| 71 | MC_STREAMID_OVERRIDE_CFG_GPUSWR, |
| 72 | MC_STREAMID_OVERRIDE_CFG_SDMMCRA, |
| 73 | MC_STREAMID_OVERRIDE_CFG_SDMMCRAA, |
| 74 | MC_STREAMID_OVERRIDE_CFG_SDMMCR, |
| 75 | MC_STREAMID_OVERRIDE_CFG_SDMMCRAB, |
| 76 | MC_STREAMID_OVERRIDE_CFG_SDMMCWA, |
| 77 | MC_STREAMID_OVERRIDE_CFG_SDMMCWAA, |
| 78 | MC_STREAMID_OVERRIDE_CFG_SDMMCW, |
| 79 | MC_STREAMID_OVERRIDE_CFG_SDMMCWAB, |
| 80 | MC_STREAMID_OVERRIDE_CFG_VICSRD, |
| 81 | MC_STREAMID_OVERRIDE_CFG_VICSWR, |
| 82 | MC_STREAMID_OVERRIDE_CFG_VIW, |
| 83 | MC_STREAMID_OVERRIDE_CFG_NVDECSRD, |
| 84 | MC_STREAMID_OVERRIDE_CFG_NVDECSWR, |
| 85 | MC_STREAMID_OVERRIDE_CFG_APER, |
| 86 | MC_STREAMID_OVERRIDE_CFG_APEW, |
| 87 | MC_STREAMID_OVERRIDE_CFG_NVJPGSRD, |
| 88 | MC_STREAMID_OVERRIDE_CFG_NVJPGSWR, |
| 89 | MC_STREAMID_OVERRIDE_CFG_SESRD, |
| 90 | MC_STREAMID_OVERRIDE_CFG_SESWR, |
| 91 | MC_STREAMID_OVERRIDE_CFG_ETRR, |
| 92 | MC_STREAMID_OVERRIDE_CFG_ETRW, |
| 93 | MC_STREAMID_OVERRIDE_CFG_TSECSRDB, |
| 94 | MC_STREAMID_OVERRIDE_CFG_TSECSWRB, |
| 95 | MC_STREAMID_OVERRIDE_CFG_GPUSRD2, |
| 96 | MC_STREAMID_OVERRIDE_CFG_GPUSWR2, |
| 97 | MC_STREAMID_OVERRIDE_CFG_AXISR, |
| 98 | MC_STREAMID_OVERRIDE_CFG_AXISW, |
| 99 | MC_STREAMID_OVERRIDE_CFG_EQOSR, |
| 100 | MC_STREAMID_OVERRIDE_CFG_EQOSW, |
| 101 | MC_STREAMID_OVERRIDE_CFG_UFSHCR, |
| 102 | MC_STREAMID_OVERRIDE_CFG_UFSHCW, |
| 103 | MC_STREAMID_OVERRIDE_CFG_NVDISPLAYR, |
| 104 | MC_STREAMID_OVERRIDE_CFG_BPMPR, |
| 105 | MC_STREAMID_OVERRIDE_CFG_BPMPW, |
| 106 | MC_STREAMID_OVERRIDE_CFG_BPMPDMAR, |
| 107 | MC_STREAMID_OVERRIDE_CFG_BPMPDMAW, |
| 108 | MC_STREAMID_OVERRIDE_CFG_AONR, |
| 109 | MC_STREAMID_OVERRIDE_CFG_AONW, |
| 110 | MC_STREAMID_OVERRIDE_CFG_AONDMAR, |
| 111 | MC_STREAMID_OVERRIDE_CFG_AONDMAW, |
| 112 | MC_STREAMID_OVERRIDE_CFG_SCER, |
| 113 | MC_STREAMID_OVERRIDE_CFG_SCEW, |
| 114 | MC_STREAMID_OVERRIDE_CFG_SCEDMAR, |
| 115 | MC_STREAMID_OVERRIDE_CFG_SCEDMAW, |
| 116 | MC_STREAMID_OVERRIDE_CFG_APEDMAR, |
| 117 | MC_STREAMID_OVERRIDE_CFG_APEDMAW, |
| 118 | MC_STREAMID_OVERRIDE_CFG_NVDISPLAYR1, |
| 119 | MC_STREAMID_OVERRIDE_CFG_VICSRD1, |
| 120 | MC_STREAMID_OVERRIDE_CFG_NVDECSRD1 |
| 121 | }; |
| 122 | |
| 123 | /* array to hold the security configs for stream IDs */ |
| 124 | const static mc_streamid_security_cfg_t sec_cfgs[] = { |
Varun Wadekar | de729d6 | 2016-02-17 10:01:28 -0800 | [diff] [blame^] | 125 | mc_make_sec_cfg(SCEW, NON_SECURE, NO_OVERRIDE, ENABLE), |
Varun Wadekar | cd5a2f5 | 2015-09-20 15:08:22 +0530 | [diff] [blame] | 126 | mc_make_sec_cfg(AFIR, NON_SECURE, OVERRIDE, ENABLE), |
| 127 | mc_make_sec_cfg(NVDISPLAYR1, NON_SECURE, OVERRIDE, ENABLE), |
| 128 | mc_make_sec_cfg(XUSB_DEVR, NON_SECURE, OVERRIDE, ENABLE), |
| 129 | mc_make_sec_cfg(VICSRD1, NON_SECURE, NO_OVERRIDE, ENABLE), |
| 130 | mc_make_sec_cfg(NVENCSWR, NON_SECURE, NO_OVERRIDE, ENABLE), |
| 131 | mc_make_sec_cfg(TSECSRDB, NON_SECURE, NO_OVERRIDE, ENABLE), |
| 132 | mc_make_sec_cfg(AXISW, SECURE, NO_OVERRIDE, DISABLE), |
| 133 | mc_make_sec_cfg(SDMMCWAB, NON_SECURE, OVERRIDE, ENABLE), |
| 134 | mc_make_sec_cfg(AONDMAW, NON_SECURE, OVERRIDE, ENABLE), |
| 135 | mc_make_sec_cfg(GPUSWR2, SECURE, NO_OVERRIDE, DISABLE), |
| 136 | mc_make_sec_cfg(SATAW, NON_SECURE, OVERRIDE, ENABLE), |
| 137 | mc_make_sec_cfg(UFSHCW, NON_SECURE, OVERRIDE, ENABLE), |
| 138 | mc_make_sec_cfg(AFIW, NON_SECURE, OVERRIDE, ENABLE), |
| 139 | mc_make_sec_cfg(SDMMCR, NON_SECURE, OVERRIDE, ENABLE), |
Varun Wadekar | de729d6 | 2016-02-17 10:01:28 -0800 | [diff] [blame^] | 140 | mc_make_sec_cfg(SCEDMAW, NON_SECURE, NO_OVERRIDE, ENABLE), |
Varun Wadekar | cd5a2f5 | 2015-09-20 15:08:22 +0530 | [diff] [blame] | 141 | mc_make_sec_cfg(UFSHCR, NON_SECURE, OVERRIDE, ENABLE), |
| 142 | mc_make_sec_cfg(SDMMCWAA, NON_SECURE, OVERRIDE, ENABLE), |
| 143 | mc_make_sec_cfg(APEDMAW, NON_SECURE, OVERRIDE, ENABLE), |
| 144 | mc_make_sec_cfg(SESWR, NON_SECURE, OVERRIDE, ENABLE), |
| 145 | mc_make_sec_cfg(MPCORER, NON_SECURE, OVERRIDE, ENABLE), |
| 146 | mc_make_sec_cfg(PTCR, NON_SECURE, OVERRIDE, ENABLE), |
| 147 | mc_make_sec_cfg(BPMPW, NON_SECURE, NO_OVERRIDE, ENABLE), |
| 148 | mc_make_sec_cfg(ETRW, NON_SECURE, OVERRIDE, ENABLE), |
| 149 | mc_make_sec_cfg(GPUSRD, SECURE, NO_OVERRIDE, DISABLE), |
| 150 | mc_make_sec_cfg(VICSWR, NON_SECURE, NO_OVERRIDE, ENABLE), |
Varun Wadekar | de729d6 | 2016-02-17 10:01:28 -0800 | [diff] [blame^] | 151 | mc_make_sec_cfg(SCEDMAR, NON_SECURE, NO_OVERRIDE, ENABLE), |
Varun Wadekar | cd5a2f5 | 2015-09-20 15:08:22 +0530 | [diff] [blame] | 152 | mc_make_sec_cfg(HDAW, NON_SECURE, OVERRIDE, ENABLE), |
| 153 | mc_make_sec_cfg(ISPWA, NON_SECURE, OVERRIDE, ENABLE), |
| 154 | mc_make_sec_cfg(EQOSW, NON_SECURE, OVERRIDE, ENABLE), |
| 155 | mc_make_sec_cfg(XUSB_HOSTW, NON_SECURE, OVERRIDE, ENABLE), |
| 156 | mc_make_sec_cfg(TSECSWR, NON_SECURE, NO_OVERRIDE, ENABLE), |
| 157 | mc_make_sec_cfg(SDMMCRAA, NON_SECURE, OVERRIDE, ENABLE), |
| 158 | mc_make_sec_cfg(APER, NON_SECURE, OVERRIDE, ENABLE), |
| 159 | mc_make_sec_cfg(VIW, NON_SECURE, OVERRIDE, ENABLE), |
| 160 | mc_make_sec_cfg(APEW, NON_SECURE, OVERRIDE, ENABLE), |
| 161 | mc_make_sec_cfg(AXISR, SECURE, NO_OVERRIDE, DISABLE), |
| 162 | mc_make_sec_cfg(SDMMCW, NON_SECURE, OVERRIDE, ENABLE), |
| 163 | mc_make_sec_cfg(BPMPDMAW, NON_SECURE, NO_OVERRIDE, ENABLE), |
| 164 | mc_make_sec_cfg(ISPRA, NON_SECURE, OVERRIDE, ENABLE), |
| 165 | mc_make_sec_cfg(NVDECSWR, NON_SECURE, NO_OVERRIDE, ENABLE), |
| 166 | mc_make_sec_cfg(XUSB_DEVW, NON_SECURE, OVERRIDE, ENABLE), |
| 167 | mc_make_sec_cfg(NVDECSRD, NON_SECURE, NO_OVERRIDE, ENABLE), |
| 168 | mc_make_sec_cfg(MPCOREW, NON_SECURE, OVERRIDE, ENABLE), |
| 169 | mc_make_sec_cfg(NVDISPLAYR, NON_SECURE, OVERRIDE, ENABLE), |
| 170 | mc_make_sec_cfg(BPMPDMAR, NON_SECURE, NO_OVERRIDE, ENABLE), |
| 171 | mc_make_sec_cfg(NVJPGSWR, NON_SECURE, NO_OVERRIDE, ENABLE), |
| 172 | mc_make_sec_cfg(NVDECSRD1, NON_SECURE, NO_OVERRIDE, ENABLE), |
| 173 | mc_make_sec_cfg(TSECSRD, NON_SECURE, NO_OVERRIDE, ENABLE), |
| 174 | mc_make_sec_cfg(NVJPGSRD, NON_SECURE, NO_OVERRIDE, ENABLE), |
| 175 | mc_make_sec_cfg(SDMMCWA, NON_SECURE, OVERRIDE, ENABLE), |
Varun Wadekar | de729d6 | 2016-02-17 10:01:28 -0800 | [diff] [blame^] | 176 | mc_make_sec_cfg(SCER, NON_SECURE, NO_OVERRIDE, ENABLE), |
Varun Wadekar | cd5a2f5 | 2015-09-20 15:08:22 +0530 | [diff] [blame] | 177 | mc_make_sec_cfg(XUSB_HOSTR, NON_SECURE, OVERRIDE, ENABLE), |
| 178 | mc_make_sec_cfg(VICSRD, NON_SECURE, NO_OVERRIDE, ENABLE), |
| 179 | mc_make_sec_cfg(AONDMAR, NON_SECURE, OVERRIDE, ENABLE), |
| 180 | mc_make_sec_cfg(AONW, NON_SECURE, OVERRIDE, ENABLE), |
| 181 | mc_make_sec_cfg(SDMMCRA, NON_SECURE, OVERRIDE, ENABLE), |
| 182 | mc_make_sec_cfg(HOST1XDMAR, NON_SECURE, NO_OVERRIDE, ENABLE), |
| 183 | mc_make_sec_cfg(EQOSR, NON_SECURE, OVERRIDE, ENABLE), |
| 184 | mc_make_sec_cfg(SATAR, NON_SECURE, OVERRIDE, ENABLE), |
| 185 | mc_make_sec_cfg(BPMPR, NON_SECURE, NO_OVERRIDE, ENABLE), |
| 186 | mc_make_sec_cfg(HDAR, NON_SECURE, OVERRIDE, ENABLE), |
| 187 | mc_make_sec_cfg(SDMMCRAB, NON_SECURE, OVERRIDE, ENABLE), |
| 188 | mc_make_sec_cfg(ETRR, NON_SECURE, OVERRIDE, ENABLE), |
| 189 | mc_make_sec_cfg(AONR, NON_SECURE, OVERRIDE, ENABLE), |
| 190 | mc_make_sec_cfg(APEDMAR, NON_SECURE, OVERRIDE, ENABLE), |
| 191 | mc_make_sec_cfg(SESRD, NON_SECURE, OVERRIDE, ENABLE), |
| 192 | mc_make_sec_cfg(NVENCSRD, NON_SECURE, NO_OVERRIDE, ENABLE), |
| 193 | mc_make_sec_cfg(GPUSWR, SECURE, NO_OVERRIDE, DISABLE), |
| 194 | mc_make_sec_cfg(TSECSWRB, NON_SECURE, NO_OVERRIDE, ENABLE), |
| 195 | mc_make_sec_cfg(ISPWB, NON_SECURE, OVERRIDE, ENABLE), |
| 196 | mc_make_sec_cfg(GPUSRD2, SECURE, NO_OVERRIDE, DISABLE), |
| 197 | }; |
| 198 | |
| 199 | /* |
| 200 | * Init SMMU. |
| 201 | */ |
| 202 | void tegra_memctrl_setup(void) |
| 203 | { |
| 204 | uint32_t val; |
| 205 | uint32_t num_overrides = sizeof(streamid_overrides) / sizeof(uint32_t); |
| 206 | uint32_t num_sec_cfgs = sizeof(sec_cfgs) / sizeof(mc_streamid_security_cfg_t); |
| 207 | int i; |
| 208 | |
| 209 | INFO("Tegra Memory Controller (v2)\n"); |
| 210 | |
| 211 | /* Program the SMMU pagesize */ |
| 212 | val = tegra_smmu_read_32(ARM_SMMU_GSR0_SECURE_ACR); |
| 213 | val |= ARM_SMMU_GSR0_PGSIZE_64K; |
| 214 | tegra_smmu_write_32(ARM_SMMU_GSR0_SECURE_ACR, val); |
| 215 | |
| 216 | /* Program all the Stream ID overrides */ |
| 217 | for (i = 0; i < num_overrides; i++) |
| 218 | tegra_mc_streamid_write_32(streamid_overrides[i], |
| 219 | MC_STREAM_ID_MAX); |
| 220 | |
| 221 | /* Program the security config settings for all Stream IDs */ |
| 222 | for (i = 0; i < num_sec_cfgs; i++) { |
| 223 | val = sec_cfgs[i].override_enable << 16 | |
| 224 | sec_cfgs[i].override_client_inputs << 8 | |
| 225 | sec_cfgs[i].override_client_ns_flag << 0; |
| 226 | tegra_mc_streamid_write_32(sec_cfgs[i].offset, val); |
| 227 | } |
| 228 | |
| 229 | /* |
| 230 | * All requests at boot time, and certain requests during |
| 231 | * normal run time, are physically addressed and must bypass |
| 232 | * the SMMU. The client hub logic implements a hardware bypass |
| 233 | * path around the Translation Buffer Units (TBU). During |
| 234 | * boot-time, the SMMU_BYPASS_CTRL register (which defaults to |
| 235 | * TBU_BYPASS mode) will be used to steer all requests around |
| 236 | * the uninitialized TBUs. During normal operation, this register |
| 237 | * is locked into TBU_BYPASS_SID config, which routes requests |
| 238 | * with special StreamID 0x7f on the bypass path and all others |
| 239 | * through the selected TBU. This is done to disable SMMU Bypass |
| 240 | * mode, as it could be used to circumvent SMMU security checks. |
| 241 | */ |
| 242 | tegra_mc_write_32(MC_SMMU_BYPASS_CONFIG, |
| 243 | MC_SMMU_BYPASS_CONFIG_SETTINGS); |
| 244 | |
| 245 | /* video memory carveout region */ |
| 246 | if (video_mem_base) { |
| 247 | tegra_mc_write_32(MC_VIDEO_PROTECT_BASE_LO, |
| 248 | (uint32_t)video_mem_base); |
| 249 | tegra_mc_write_32(MC_VIDEO_PROTECT_BASE_HI, |
| 250 | (uint32_t)(video_mem_base >> 32)); |
| 251 | tegra_mc_write_32(MC_VIDEO_PROTECT_SIZE_MB, video_mem_size); |
| 252 | |
| 253 | /* |
| 254 | * MCE propogates the VideoMem configuration values across the |
| 255 | * CCPLEX. |
| 256 | */ |
| 257 | mce_update_gsc_videomem(); |
| 258 | } |
| 259 | } |
| 260 | |
| 261 | /* |
| 262 | * Secure the BL31 DRAM aperture. |
| 263 | * |
| 264 | * phys_base = physical base of TZDRAM aperture |
| 265 | * size_in_bytes = size of aperture in bytes |
| 266 | */ |
| 267 | void tegra_memctrl_tzdram_setup(uint64_t phys_base, uint32_t size_in_bytes) |
| 268 | { |
| 269 | /* |
| 270 | * Setup the Memory controller to allow only secure accesses to |
| 271 | * the TZDRAM carveout |
| 272 | */ |
| 273 | INFO("Configuring TrustZone DRAM Memory Carveout\n"); |
| 274 | |
| 275 | tegra_mc_write_32(MC_SECURITY_CFG0_0, (uint32_t)phys_base); |
| 276 | tegra_mc_write_32(MC_SECURITY_CFG3_0, (uint32_t)(phys_base >> 32)); |
| 277 | tegra_mc_write_32(MC_SECURITY_CFG1_0, size_in_bytes >> 20); |
| 278 | |
| 279 | /* |
| 280 | * MCE propogates the security configuration values across the |
| 281 | * CCPLEX. |
| 282 | */ |
| 283 | mce_update_gsc_tzdram(); |
| 284 | } |
| 285 | |
| 286 | /* |
Varun Wadekar | 13e7dc4 | 2015-12-30 15:15:08 -0800 | [diff] [blame] | 287 | * Secure the BL31 TZRAM aperture. |
| 288 | * |
| 289 | * phys_base = physical base of TZRAM aperture |
| 290 | * size_in_bytes = size of aperture in bytes |
| 291 | */ |
| 292 | void tegra_memctrl_tzram_setup(uint64_t phys_base, uint32_t size_in_bytes) |
| 293 | { |
| 294 | uint64_t tzram_end = phys_base + size_in_bytes - 1; |
| 295 | uint32_t val; |
| 296 | |
| 297 | /* |
| 298 | * Check if the TZRAM is locked already. |
| 299 | */ |
| 300 | if (tegra_mc_read_32(MC_TZRAM_REG_CTRL) == DISABLE_TZRAM_ACCESS) |
| 301 | return; |
| 302 | |
| 303 | /* |
| 304 | * Setup the Memory controller to allow only secure accesses to |
| 305 | * the TZRAM carveout |
| 306 | */ |
| 307 | INFO("Configuring TrustZone RAM (SysRAM) Memory Carveout\n"); |
| 308 | |
| 309 | /* Program the base and end values */ |
| 310 | tegra_mc_write_32(MC_TZRAM_BASE, (uint32_t)phys_base); |
| 311 | tegra_mc_write_32(MC_TZRAM_END, (uint32_t)tzram_end); |
| 312 | |
| 313 | /* Extract the high address bits from the base/end values */ |
| 314 | val = (uint32_t)(phys_base >> 32) & TZRAM_ADDR_HI_BITS_MASK; |
| 315 | val |= (((uint32_t)(tzram_end >> 32) << TZRAM_END_HI_BITS_SHIFT) & |
| 316 | TZRAM_ADDR_HI_BITS_MASK); |
| 317 | tegra_mc_write_32(MC_TZRAM_HI_ADDR_BITS, val); |
| 318 | |
| 319 | /* Disable further writes to the TZRAM setup registers */ |
| 320 | tegra_mc_write_32(MC_TZRAM_REG_CTRL, DISABLE_TZRAM_ACCESS); |
| 321 | |
| 322 | /* |
| 323 | * MCE propogates the security configuration values across the |
| 324 | * CCPLEX. |
| 325 | */ |
| 326 | mce_update_gsc_tzram(); |
| 327 | } |
| 328 | |
| 329 | /* |
Varun Wadekar | cd5a2f5 | 2015-09-20 15:08:22 +0530 | [diff] [blame] | 330 | * Program the Video Memory carveout region |
| 331 | * |
| 332 | * phys_base = physical base of aperture |
| 333 | * size_in_bytes = size of aperture in bytes |
| 334 | */ |
| 335 | void tegra_memctrl_videomem_setup(uint64_t phys_base, uint32_t size_in_bytes) |
| 336 | { |
| 337 | /* |
| 338 | * Setup the Memory controller to restrict CPU accesses to the Video |
| 339 | * Memory region |
| 340 | */ |
| 341 | INFO("Configuring Video Memory Carveout\n"); |
| 342 | |
| 343 | tegra_mc_write_32(MC_VIDEO_PROTECT_BASE_LO, (uint32_t)phys_base); |
| 344 | tegra_mc_write_32(MC_VIDEO_PROTECT_BASE_HI, |
| 345 | (uint32_t)(phys_base >> 32)); |
| 346 | tegra_mc_write_32(MC_VIDEO_PROTECT_SIZE_MB, size_in_bytes); |
| 347 | |
| 348 | /* store new values */ |
| 349 | video_mem_base = phys_base; |
| 350 | video_mem_size = size_in_bytes >> 20; |
| 351 | |
| 352 | /* |
| 353 | * MCE propogates the VideoMem configuration values across the |
| 354 | * CCPLEX. |
| 355 | */ |
| 356 | mce_update_gsc_videomem(); |
| 357 | } |