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git01.mediatek.com / filogic / atf / 47d8ecbeb8f592faaac7c0d89551062f5a0a6284 / . / plat / arm / board / tc / fdts / tc_spmc_manifest.dts
blob: d3a5e1a77acffa1a098a7b06ae7533965ed0201e [file] [log] [blame]
Arunachalam Ganapathyade4a202020-09-22 12:50:45 +0100[diff] [blame]1/*
Arunachalam Ganapathydfd1fb42021-05-27 16:03:58 +0100[diff] [blame]2 * Copyright (c) 2020-2021, Arm Limited. All rights reserved.
Arunachalam Ganapathyade4a202020-09-22 12:50:45 +0100[diff] [blame]3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6/dts-v1/;
7
8/ {
9 compatible = "arm,ffa-core-manifest-1.0";
10 #address-cells = <2>;
11 #size-cells = <1>;
12
13 attribute {
14 spmc_id = <0x8000>;
15 maj_ver = <0x1>;
J-Alves481c52f2021-03-11 17:46:47 +0000[diff] [blame]16 min_ver = <0x1>;
Arunachalam Ganapathyade4a202020-09-22 12:50:45 +0100[diff] [blame]17 exec_state = <0x0>;
18 load_address = <0x0 0xfd000000>;
19 entrypoint = <0x0 0xfd000000>;
20 binary_size = <0x80000>;
21 };
22
Arunachalam Ganapathyade4a202020-09-22 12:50:45 +0100[diff] [blame]23 hypervisor {
24 compatible = "hafnium,hafnium";
25 vm1 {
26 is_ffa_partition;
27 debug_name = "cactus-primary";
28 load_address = <0xfe000000>;
Avinash Mehtaf68a0842020-10-28 16:43:28 +0000[diff] [blame]29 vcpu_count = <8>;
30 mem_size = <1048576>;
Arunachalam Ganapathyade4a202020-09-22 12:50:45 +0100[diff] [blame]31 };
32 vm2 {
33 is_ffa_partition;
34 debug_name = "cactus-secondary";
35 load_address = <0xfe100000>;
Avinash Mehtaf68a0842020-10-28 16:43:28 +0000[diff] [blame]36 vcpu_count = <8>;
Arunachalam Ganapathyade4a202020-09-22 12:50:45 +0100[diff] [blame]37 mem_size = <1048576>;
38 };
39 vm3 {
40 is_ffa_partition;
41 debug_name = "cactus-tertiary";
42 load_address = <0xfe200000>;
Arunachalam Ganapathydfd1fb42021-05-27 16:03:58 +0100[diff] [blame]43 vcpu_count = <1>;
Arunachalam Ganapathyade4a202020-09-22 12:50:45 +0100[diff] [blame]44 mem_size = <1048576>;
45 };
Olivier Deprez05475992021-09-28 15:35:39 +0200[diff] [blame]46 vm4 {
47 is_ffa_partition;
48 debug_name = "ivy";
49 load_address = <0xfe600000>;
50 vcpu_count = <1>;
51 mem_size = <1048576>;
52 };
Arunachalam Ganapathyade4a202020-09-22 12:50:45 +0100[diff] [blame]53 };
54
55 cpus {
56 #address-cells = <0x2>;
57 #size-cells = <0x0>;
58
59 CPU0:cpu@0 {
60 device_type = "cpu";
61 compatible = "arm,armv8";
62 reg = <0x0 0x0>;
63 enable-method = "psci";
64 };
65
66 /*
Avinash Mehtaf68a0842020-10-28 16:43:28 +0000[diff] [blame]67 * SPMC (Hafnium) requires secondary cpu nodes are declared in
Arunachalam Ganapathyade4a202020-09-22 12:50:45 +0100[diff] [blame]68 * descending order
69 */
Avinash Mehtaf68a0842020-10-28 16:43:28 +0000[diff] [blame]70 CPU7:cpu@700 {
71 device_type = "cpu";
72 compatible = "arm,armv8";
73 reg = <0x0 0x700>;
74 enable-method = "psci";
75 };
76
77 CPU6:cpu@600 {
78 device_type = "cpu";
79 compatible = "arm,armv8";
80 reg = <0x0 0x600>;
81 enable-method = "psci";
82 };
83
84 CPU5:cpu@500 {
85 device_type = "cpu";
86 compatible = "arm,armv8";
87 reg = <0x0 0x500>;
88 enable-method = "psci";
89 };
90
91 CPU4:cpu@400 {
92 device_type = "cpu";
93 compatible = "arm,armv8";
94 reg = <0x0 0x400>;
95 enable-method = "psci";
96 };
97
Arunachalam Ganapathyade4a202020-09-22 12:50:45 +0100[diff] [blame]98 CPU3:cpu@300 {
99 device_type = "cpu";
100 compatible = "arm,armv8";
101 reg = <0x0 0x300>;
102 enable-method = "psci";
103 };
104
105 CPU2:cpu@200 {
106 device_type = "cpu";
107 compatible = "arm,armv8";
108 reg = <0x0 0x200>;
109 enable-method = "psci";
110 };
111
112 CPU1:cpu@100 {
113 device_type = "cpu";
114 compatible = "arm,armv8";
115 reg = <0x0 0x100>;
116 enable-method = "psci";
117 };
118 };
119
Usama Ariff1513622021-04-09 17:07:41 +0100[diff] [blame]120 /* 32MB of TC_TZC_DRAM1_BASE */
Arunachalam Ganapathyade4a202020-09-22 12:50:45 +0100[diff] [blame]121 memory@fd000000 {
122 device_type = "memory";
123 reg = <0x0 0xfd000000 0x2000000>;
124 };
125};