| Jayanth Dodderi Chidanand | 37de916 | 2021-12-07 17:20:10 +0000 | [diff] [blame] | 1 | /* |
| Rohit Mathew | 960a77e | 2023-12-15 12:40:41 +0000 | [diff] [blame] | 2 | * Copyright (c) 2022-2024, Arm Limited. All rights reserved. |
| Jayanth Dodderi Chidanand | 37de916 | 2021-12-07 17:20:10 +0000 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #ifndef NEOVERSE_POSEIDON_H |
| 8 | #define NEOVERSE_POSEIDON_H |
| 9 | |
| 10 | |
| Rohit Mathew | 960a77e | 2023-12-15 12:40:41 +0000 | [diff] [blame] | 11 | #define NEOVERSE_POSEIDON_VNAE_MIDR U(0x410FD830) |
| Rohit Mathew | 22d2277 | 2023-12-15 12:50:58 +0000 | [diff] [blame] | 12 | #define NEOVERSE_POSEIDON_V_MIDR U(0x410FD840) |
| Jayanth Dodderi Chidanand | 37de916 | 2021-12-07 17:20:10 +0000 | [diff] [blame] | 13 | |
| Bipin Ravi | 32464ba | 2022-05-06 16:02:30 -0500 | [diff] [blame] | 14 | /* Neoverse Poseidon loop count for CVE-2022-23960 mitigation */ |
| 15 | #define NEOVERSE_POSEIDON_BHB_LOOP_COUNT U(132) |
| 16 | |
| Jayanth Dodderi Chidanand | 37de916 | 2021-12-07 17:20:10 +0000 | [diff] [blame] | 17 | /******************************************************************************* |
| 18 | * CPU Extended Control register specific definitions. |
| 19 | ******************************************************************************/ |
| 20 | #define NEOVERSE_POSEIDON_CPUECTLR_EL1 S3_0_C15_C1_4 |
| 21 | |
| 22 | /******************************************************************************* |
| 23 | * CPU Power Control register specific definitions |
| 24 | ******************************************************************************/ |
| 25 | #define NEOVERSE_POSEIDON_CPUPWRCTLR_EL1 S3_0_C15_C2_7 |
| 26 | #define NEOVERSE_POSEIDON_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1) |
| 27 | |
| 28 | #endif /* NEOVERSE_POSEIDON_H */ |