| Jayanth Dodderi Chidanand | 37de916 | 2021-12-07 17:20:10 +0000 | [diff] [blame^] | 1 | /* |
| 2 | * Copyright (c) 2022, ARM Limited. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #ifndef NEOVERSE_POSEIDON_H |
| 8 | #define NEOVERSE_POSEIDON_H |
| 9 | |
| 10 | |
| 11 | #define NEOVERSE_POSEIDON_MIDR U(0x410FD830) |
| 12 | |
| 13 | /******************************************************************************* |
| 14 | * CPU Extended Control register specific definitions. |
| 15 | ******************************************************************************/ |
| 16 | #define NEOVERSE_POSEIDON_CPUECTLR_EL1 S3_0_C15_C1_4 |
| 17 | |
| 18 | /******************************************************************************* |
| 19 | * CPU Power Control register specific definitions |
| 20 | ******************************************************************************/ |
| 21 | #define NEOVERSE_POSEIDON_CPUPWRCTLR_EL1 S3_0_C15_C2_7 |
| 22 | #define NEOVERSE_POSEIDON_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1) |
| 23 | |
| 24 | #endif /* NEOVERSE_POSEIDON_H */ |