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Soren Brinkmann76fcae32016-03-06 20:16:27 -08001/*
Antonio Nino Diazea3c4de2018-10-17 16:46:41 +01002 * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
Soren Brinkmann76fcae32016-03-06 20:16:27 -08003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Soren Brinkmann76fcae32016-03-06 20:16:27 -08005 */
6
7#include <asm_macros.S>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00008#include <drivers/arm/gicv2.h>
Soren Brinkmann76fcae32016-03-06 20:16:27 -08009#include <platform_def.h>
10
11 .globl plat_secondary_cold_boot_setup
12 .globl plat_is_my_cpu_primary
Antonio Nino Diazea3c4de2018-10-17 16:46:41 +010013 .globl zynqmp_calc_core_pos
14 .globl plat_my_core_pos
15 .globl plat_crash_console_init
16 .globl plat_crash_console_putc
17 .globl plat_crash_console_flush
18 .globl platform_mem_init
Soren Brinkmann76fcae32016-03-06 20:16:27 -080019
20 /* -----------------------------------------------------
21 * void plat_secondary_cold_boot_setup (void);
22 *
23 * This function performs any platform specific actions
24 * needed for a secondary cpu after a cold reset e.g
25 * mark the cpu's presence, mechanism to place it in a
26 * holding pen etc.
27 * TODO: Should we read the PSYS register to make sure
28 * that the request has gone through.
29 * -----------------------------------------------------
30 */
31func plat_secondary_cold_boot_setup
32 mrs x0, mpidr_el1
33
34 /* Deactivate the gic cpu interface */
35 ldr x1, =BASE_GICC_BASE
36 mov w0, #(IRQ_BYP_DIS_GRP1 | FIQ_BYP_DIS_GRP1)
37 orr w0, w0, #(IRQ_BYP_DIS_GRP0 | FIQ_BYP_DIS_GRP0)
38 str w0, [x1, #GICC_CTLR]
39
40 /*
41 * There is no sane reason to come out of this wfi. This
42 * cpu will be powered on and reset by the cpu_on pm api
43 */
44 dsb sy
451:
Jeenu Viswambharan68aef102016-11-30 15:21:11 +000046 no_ret plat_panic_handler
Soren Brinkmann76fcae32016-03-06 20:16:27 -080047endfunc plat_secondary_cold_boot_setup
48
49func plat_is_my_cpu_primary
50 mov x9, x30
51 bl plat_my_core_pos
52 cmp x0, #ZYNQMP_PRIMARY_CPU
53 cset x0, eq
54 ret x9
55endfunc plat_is_my_cpu_primary
Antonio Nino Diazea3c4de2018-10-17 16:46:41 +010056
57 /* -----------------------------------------------------
58 * unsigned int plat_my_core_pos(void)
59 * This function uses the zynqmp_calc_core_pos()
60 * definition to get the index of the calling CPU.
61 * -----------------------------------------------------
62 */
63func plat_my_core_pos
64 mrs x0, mpidr_el1
65 b zynqmp_calc_core_pos
66endfunc plat_my_core_pos
67
68 /* -----------------------------------------------------
69 * unsigned int zynqmp_calc_core_pos(u_register_t mpidr)
70 * Helper function to calculate the core position.
71 * With this function: CorePos = (ClusterId * 4) +
72 * CoreId
73 * -----------------------------------------------------
74 */
75func zynqmp_calc_core_pos
76 and x1, x0, #MPIDR_CPU_MASK
77 and x0, x0, #MPIDR_CLUSTER_MASK
78 add x0, x1, x0, LSR #6
79 ret
80endfunc zynqmp_calc_core_pos
81
82 /* ---------------------------------------------
83 * int plat_crash_console_init(void)
84 * Function to initialize the crash console
85 * without a C Runtime to print crash report.
86 * Clobber list : x0 - x4
87 * ---------------------------------------------
88 */
89func plat_crash_console_init
90 mov_imm x0, ZYNQMP_CRASH_UART_BASE
91 mov_imm x1, ZYNQMP_CRASH_UART_CLK_IN_HZ
92 mov_imm x2, ZYNQMP_UART_BAUDRATE
93 b console_core_init
94endfunc plat_crash_console_init
95
96 /* ---------------------------------------------
97 * int plat_crash_console_putc(int c)
98 * Function to print a character on the crash
99 * console without a C Runtime.
100 * Clobber list : x1, x2
101 * ---------------------------------------------
102 */
103func plat_crash_console_putc
104 mov_imm x1, ZYNQMP_CRASH_UART_BASE
105 b console_core_putc
106endfunc plat_crash_console_putc
107
108 /* ---------------------------------------------
109 * int plat_crash_console_flush()
110 * Function to force a write of all buffered
111 * data that hasn't been output.
112 * Out : return -1 on error else return 0.
113 * Clobber list : r0
114 * ---------------------------------------------
115 */
116func plat_crash_console_flush
117 mov_imm x0, ZYNQMP_CRASH_UART_BASE
118 b console_core_flush
119endfunc plat_crash_console_flush
120
121 /* ---------------------------------------------------------------------
122 * We don't need to carry out any memory initialization on ARM
123 * platforms. The Secure RAM is accessible straight away.
124 * ---------------------------------------------------------------------
125 */
126func platform_mem_init
127 ret
128endfunc platform_mem_init