Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1 | /* |
Marek Vasut | b0eb988 | 2019-06-14 01:22:38 +0200 | [diff] [blame] | 2 | * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved. |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #include <stdint.h> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 8 | |
| 9 | #include <common/debug.h> |
| 10 | |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 11 | #include <rcar_def.h> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 12 | |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 13 | #include "../qos_common.h" |
Marek Vasut | b0eb988 | 2019-06-14 01:22:38 +0200 | [diff] [blame] | 14 | #include "../qos_reg.h" |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 15 | #include "qos_init_h3_v11.h" |
| 16 | |
| 17 | #define RCAR_QOS_VERSION "rev.0.37" |
| 18 | |
Marek Vasut | 436bd7a | 2019-06-14 01:25:01 +0200 | [diff] [blame] | 19 | #include "qos_init_h3_v11_mstat.h" |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 20 | |
| 21 | static void dbsc_setting(void) |
| 22 | { |
| 23 | uint32_t md = 0; |
| 24 | |
| 25 | /* BUFCAM settings */ |
| 26 | /* DBSC_DBCAM0CNF0 not set */ |
Marek Vasut | 4690621 | 2019-06-14 01:32:53 +0200 | [diff] [blame^] | 27 | io_write_32(DBSC_DBCAM0CNF1, 0x00044218); |
| 28 | io_write_32(DBSC_DBCAM0CNF2, 0x000000F4); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 29 | /* DBSC_DBCAM0CNF3 not set */ |
Marek Vasut | 4690621 | 2019-06-14 01:32:53 +0200 | [diff] [blame^] | 30 | io_write_32(DBSC_DBSCHCNT0, 0x080F0037); |
| 31 | io_write_32(DBSC_DBSCHCNT1, 0x00001010); |
| 32 | io_write_32(DBSC_DBSCHSZ0, 0x00000001); |
| 33 | io_write_32(DBSC_DBSCHRW0, 0x22421111); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 34 | |
| 35 | md = (*((volatile uint32_t *)RST_MODEMR) & 0x000A0000) >> 17; |
| 36 | |
| 37 | switch (md) { |
| 38 | case 0x0: |
| 39 | /* DDR3200 */ |
| 40 | io_write_32(DBSC_SCFCTST2, 0x012F1123); |
| 41 | break; |
| 42 | case 0x1: /* MD19=0,MD17=1 : LPDDR4-3000, 4GByte(1GByte x4) */ |
| 43 | /* DDR2800 */ |
| 44 | io_write_32(DBSC_SCFCTST2, 0x012F1123); |
| 45 | break; |
| 46 | case 0x4: /* MD19=1,MD17=0 : LPDDR4-2400, 4GByte(1GByte x4) */ |
| 47 | /* DDR2400 */ |
| 48 | io_write_32(DBSC_SCFCTST2, 0x012F1123); |
| 49 | break; |
| 50 | default: /* MD19=1,MD17=1 : LPDDR4-1600, 4GByte(1GByte x4) */ |
| 51 | /* DDR1600 */ |
| 52 | io_write_32(DBSC_SCFCTST2, 0x012F1123); |
| 53 | break; |
| 54 | } |
| 55 | |
| 56 | /* QoS Settings */ |
Marek Vasut | b0eb988 | 2019-06-14 01:22:38 +0200 | [diff] [blame] | 57 | io_write_32(DBSC_DBSCHQOS00, 0x0000F000); |
| 58 | io_write_32(DBSC_DBSCHQOS01, 0x0000E000); |
| 59 | io_write_32(DBSC_DBSCHQOS02, 0x00007000); |
| 60 | io_write_32(DBSC_DBSCHQOS03, 0x00000000); |
Marek Vasut | b0eb988 | 2019-06-14 01:22:38 +0200 | [diff] [blame] | 61 | io_write_32(DBSC_DBSCHQOS40, 0x00000E00); |
| 62 | io_write_32(DBSC_DBSCHQOS41, 0x00000DFF); |
| 63 | io_write_32(DBSC_DBSCHQOS42, 0x00000400); |
| 64 | io_write_32(DBSC_DBSCHQOS43, 0x00000200); |
Marek Vasut | b0eb988 | 2019-06-14 01:22:38 +0200 | [diff] [blame] | 65 | io_write_32(DBSC_DBSCHQOS90, 0x00000C00); |
| 66 | io_write_32(DBSC_DBSCHQOS91, 0x00000BFF); |
| 67 | io_write_32(DBSC_DBSCHQOS92, 0x00000400); |
| 68 | io_write_32(DBSC_DBSCHQOS93, 0x00000200); |
Marek Vasut | b0eb988 | 2019-06-14 01:22:38 +0200 | [diff] [blame] | 69 | io_write_32(DBSC_DBSCHQOS130, 0x00000980); |
| 70 | io_write_32(DBSC_DBSCHQOS131, 0x0000097F); |
| 71 | io_write_32(DBSC_DBSCHQOS132, 0x00000300); |
| 72 | io_write_32(DBSC_DBSCHQOS133, 0x00000180); |
| 73 | io_write_32(DBSC_DBSCHQOS140, 0x00000800); |
| 74 | io_write_32(DBSC_DBSCHQOS141, 0x000007FF); |
| 75 | io_write_32(DBSC_DBSCHQOS142, 0x00000300); |
| 76 | io_write_32(DBSC_DBSCHQOS143, 0x00000180); |
| 77 | io_write_32(DBSC_DBSCHQOS150, 0x000007D0); |
| 78 | io_write_32(DBSC_DBSCHQOS151, 0x000007CF); |
| 79 | io_write_32(DBSC_DBSCHQOS152, 0x000005D0); |
| 80 | io_write_32(DBSC_DBSCHQOS153, 0x000003D0); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 81 | } |
| 82 | |
| 83 | void qos_init_h3_v11(void) |
| 84 | { |
| 85 | dbsc_setting(); |
| 86 | |
| 87 | /* DRAM Split Address mapping */ |
| 88 | #if (RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_4CH) || \ |
| 89 | (RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_AUTO) |
| 90 | NOTICE("BL2: DRAM Split is 4ch\n"); |
| 91 | io_write_32(AXI_ADSPLCR0, ADSPLCR0_ADRMODE_DEFAULT |
| 92 | | ADSPLCR0_SPLITSEL(0xFFU) |
| 93 | | ADSPLCR0_AREA(0x1BU) |
| 94 | | ADSPLCR0_SWP); |
| 95 | io_write_32(AXI_ADSPLCR1, 0x00000000U); |
| 96 | io_write_32(AXI_ADSPLCR2, 0xA8A90000U); |
| 97 | io_write_32(AXI_ADSPLCR3, 0x00000000U); |
| 98 | #elif RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_2CH |
| 99 | NOTICE("BL2: DRAM Split is 2ch\n"); |
| 100 | io_write_32(AXI_ADSPLCR0, 0x00000000U); |
| 101 | io_write_32(AXI_ADSPLCR1, ADSPLCR0_ADRMODE_DEFAULT |
| 102 | | ADSPLCR0_SPLITSEL(0xFFU) |
| 103 | | ADSPLCR0_AREA(0x1BU) |
| 104 | | ADSPLCR0_SWP); |
| 105 | io_write_32(AXI_ADSPLCR2, 0x00000000U); |
| 106 | io_write_32(AXI_ADSPLCR3, 0x00000000U); |
| 107 | #else |
| 108 | NOTICE("BL2: DRAM Split is OFF\n"); |
| 109 | #endif |
| 110 | |
| 111 | #if !(RCAR_QOS_TYPE == RCAR_QOS_NONE) |
| 112 | #if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT |
| 113 | NOTICE("BL2: QoS is default setting(%s)\n", RCAR_QOS_VERSION); |
| 114 | #endif |
| 115 | |
| 116 | /* AR Cache setting */ |
| 117 | io_write_32(0xE67D1000U, 0x00000100U); |
| 118 | io_write_32(0xE67D1008U, 0x00000100U); |
| 119 | |
| 120 | /* Resource Alloc setting */ |
| 121 | #if RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_2CH |
Marek Vasut | b0eb988 | 2019-06-14 01:22:38 +0200 | [diff] [blame] | 122 | io_write_32(QOSCTRL_RAS, 0x00000020U); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 123 | #else |
Marek Vasut | b0eb988 | 2019-06-14 01:22:38 +0200 | [diff] [blame] | 124 | io_write_32(QOSCTRL_RAS, 0x00000040U); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 125 | #endif |
Marek Vasut | b0eb988 | 2019-06-14 01:22:38 +0200 | [diff] [blame] | 126 | io_write_32(QOSCTRL_FIXTH, 0x000F0005U); |
| 127 | io_write_32(QOSCTRL_REGGD, 0x00000000U); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 128 | #if RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_2CH |
Marek Vasut | b0eb988 | 2019-06-14 01:22:38 +0200 | [diff] [blame] | 129 | io_write_64(QOSCTRL_DANN, 0x0101010102020201UL); |
| 130 | io_write_32(QOSCTRL_DANT, 0x00181008U); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 131 | #else |
Marek Vasut | b0eb988 | 2019-06-14 01:22:38 +0200 | [diff] [blame] | 132 | io_write_64(QOSCTRL_DANN, 0x0101000004040401UL); |
| 133 | io_write_32(QOSCTRL_DANT, 0x003C2010U); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 134 | #endif |
Marek Vasut | b0eb988 | 2019-06-14 01:22:38 +0200 | [diff] [blame] | 135 | io_write_32(QOSCTRL_EC, 0x00080001U); /* need for H3 v1.* */ |
| 136 | io_write_64(QOSCTRL_EMS, 0x0000000000000000UL); |
| 137 | io_write_32(QOSCTRL_INSFC, 0xC7840001U); |
| 138 | io_write_32(QOSCTRL_BERR, 0x00000000U); |
| 139 | io_write_32(QOSCTRL_RACNT0, 0x00000000U); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 140 | |
Marek Vasut | b0eb988 | 2019-06-14 01:22:38 +0200 | [diff] [blame] | 141 | /* QOSBW setting */ |
| 142 | io_write_32(QOSCTRL_SL_INIT, |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 143 | SL_INIT_REFFSSLOT | SL_INIT_SLOTSSLOT | SL_INIT_SSLOTCLK); |
Marek Vasut | b0eb988 | 2019-06-14 01:22:38 +0200 | [diff] [blame] | 144 | io_write_32(QOSCTRL_REF_ARS, 0x00330000U); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 145 | |
Marek Vasut | b0eb988 | 2019-06-14 01:22:38 +0200 | [diff] [blame] | 146 | /* QOSBW SRAM setting */ |
Marek Vasut | 32ccc2c | 2019-06-14 01:27:27 +0200 | [diff] [blame] | 147 | uint32_t i; |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 148 | |
Marek Vasut | 32ccc2c | 2019-06-14 01:27:27 +0200 | [diff] [blame] | 149 | for (i = 0U; i < ARRAY_SIZE(mstat_fix); i++) { |
| 150 | io_write_64(QOSBW_FIX_QOS_BANK0 + i * 8, mstat_fix[i]); |
| 151 | io_write_64(QOSBW_FIX_QOS_BANK1 + i * 8, mstat_fix[i]); |
| 152 | } |
| 153 | for (i = 0U; i < ARRAY_SIZE(mstat_be); i++) { |
| 154 | io_write_64(QOSBW_BE_QOS_BANK0 + i * 8, mstat_be[i]); |
| 155 | io_write_64(QOSBW_BE_QOS_BANK1 + i * 8, mstat_be[i]); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 156 | } |
| 157 | |
| 158 | /* 3DG bus Leaf setting */ |
| 159 | io_write_32(0xFD820808U, 0x00001234U); |
| 160 | io_write_32(0xFD820800U, 0x0000003FU); |
| 161 | io_write_32(0xFD821800U, 0x0000003FU); |
| 162 | io_write_32(0xFD822800U, 0x0000003FU); |
| 163 | io_write_32(0xFD823800U, 0x0000003FU); |
| 164 | io_write_32(0xFD824800U, 0x0000003FU); |
| 165 | io_write_32(0xFD825800U, 0x0000003FU); |
| 166 | io_write_32(0xFD826800U, 0x0000003FU); |
| 167 | io_write_32(0xFD827800U, 0x0000003FU); |
| 168 | |
| 169 | /* VIO bus Leaf setting */ |
| 170 | io_write_32(0xFEB89800, 0x00000001U); |
| 171 | io_write_32(0xFEB8A800, 0x00000001U); |
| 172 | io_write_32(0xFEB8B800, 0x00000001U); |
| 173 | io_write_32(0xFEB8C800, 0x00000001U); |
| 174 | |
| 175 | /* HSC bus Leaf setting */ |
| 176 | io_write_32(0xE6430800, 0x00000001U); |
| 177 | io_write_32(0xE6431800, 0x00000001U); |
| 178 | io_write_32(0xE6432800, 0x00000001U); |
| 179 | io_write_32(0xE6433800, 0x00000001U); |
| 180 | |
| 181 | /* MP bus Leaf setting */ |
| 182 | io_write_32(0xEC620800, 0x00000001U); |
| 183 | io_write_32(0xEC621800, 0x00000001U); |
| 184 | |
| 185 | /* PERIE bus Leaf setting */ |
| 186 | io_write_32(0xE7760800, 0x00000001U); |
| 187 | io_write_32(0xE7768800, 0x00000001U); |
| 188 | |
| 189 | /* PERIW bus Leaf setting */ |
| 190 | io_write_32(0xE6760800, 0x00000001U); |
| 191 | io_write_32(0xE6768800, 0x00000001U); |
| 192 | |
| 193 | /* RT bus Leaf setting */ |
| 194 | io_write_32(0xFFC50800, 0x00000001U); |
| 195 | io_write_32(0xFFC51800, 0x00000001U); |
| 196 | |
| 197 | /* CCI bus Leaf setting */ |
Marek Vasut | e890021 | 2019-06-14 01:30:41 +0200 | [diff] [blame] | 198 | uint32_t modemr = io_read_32(RCAR_MODEMR); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 199 | |
Marek Vasut | e890021 | 2019-06-14 01:30:41 +0200 | [diff] [blame] | 200 | modemr &= MODEMR_BOOT_CPU_MASK; |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 201 | |
Marek Vasut | e890021 | 2019-06-14 01:30:41 +0200 | [diff] [blame] | 202 | if ((modemr == MODEMR_BOOT_CPU_CA57) || |
| 203 | (modemr == MODEMR_BOOT_CPU_CA53)) { |
| 204 | io_write_32(0xF1300800, 0x00000001U); |
| 205 | io_write_32(0xF1340800, 0x00000001U); |
| 206 | io_write_32(0xF1380800, 0x00000001U); |
| 207 | io_write_32(0xF13C0800, 0x00000001U); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 208 | } |
| 209 | |
| 210 | /* Resource Alloc start */ |
Marek Vasut | b0eb988 | 2019-06-14 01:22:38 +0200 | [diff] [blame] | 211 | io_write_32(QOSCTRL_RAEN, 0x00000001U); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 212 | |
Marek Vasut | b0eb988 | 2019-06-14 01:22:38 +0200 | [diff] [blame] | 213 | /* QOSBW start */ |
| 214 | io_write_32(QOSCTRL_STATQC, 0x00000001U); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 215 | #else |
| 216 | NOTICE("BL2: QoS is None\n"); |
| 217 | |
| 218 | /* Resource Alloc setting */ |
Marek Vasut | b0eb988 | 2019-06-14 01:22:38 +0200 | [diff] [blame] | 219 | io_write_32(QOSCTRL_EC, 0x00080001U); /* need for H3 v1.* */ |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 220 | #endif /* !(RCAR_QOS_TYPE == RCAR_QOS_NONE) */ |
| 221 | } |