Manivannan Sadhasivam | 02a66d6 | 2019-04-26 18:43:50 +0530 | [diff] [blame] | 1 | // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) |
| 2 | /* |
| 3 | * Copyright (C) Arrow Electronics 2019 - All Rights Reserved |
| 4 | * Author: Botond Kardos <botond.kardos@arroweurope.com> |
| 5 | * |
| 6 | * Copyright (C) Linaro Ltd 2019 - All Rights Reserved |
| 7 | * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> |
| 8 | */ |
| 9 | |
| 10 | /dts-v1/; |
| 11 | |
Yann Gautier | 4ede20a | 2020-09-18 15:04:14 +0200 | [diff] [blame] | 12 | #include "stm32mp157.dtsi" |
| 13 | #include "stm32mp15-pinctrl.dtsi" |
| 14 | #include "stm32mp15xxac-pinctrl.dtsi" |
| 15 | #include <dt-bindings/clock/stm32mp1-clksrc.h> |
| 16 | #include "stm32mp15-ddr3-2x4Gb-1066-binG.dtsi" |
Manivannan Sadhasivam | 02a66d6 | 2019-04-26 18:43:50 +0530 | [diff] [blame] | 17 | |
| 18 | / { |
| 19 | model = "Arrow Electronics STM32MP157A Avenger96 board"; |
Yann Gautier | 4ede20a | 2020-09-18 15:04:14 +0200 | [diff] [blame] | 20 | compatible = "arrow,stm32mp157a-avenger96", "st,stm32mp157"; |
Manivannan Sadhasivam | 02a66d6 | 2019-04-26 18:43:50 +0530 | [diff] [blame] | 21 | |
| 22 | aliases { |
Yann Gautier | 4ede20a | 2020-09-18 15:04:14 +0200 | [diff] [blame] | 23 | mmc0 = &sdmmc1; |
Manivannan Sadhasivam | 02a66d6 | 2019-04-26 18:43:50 +0530 | [diff] [blame] | 24 | serial0 = &uart4; |
Yann Gautier | 4ede20a | 2020-09-18 15:04:14 +0200 | [diff] [blame] | 25 | serial1 = &uart7; |
Manivannan Sadhasivam | 02a66d6 | 2019-04-26 18:43:50 +0530 | [diff] [blame] | 26 | }; |
| 27 | |
| 28 | chosen { |
| 29 | stdout-path = "serial0:115200n8"; |
| 30 | }; |
| 31 | |
Yann Gautier | 4ede20a | 2020-09-18 15:04:14 +0200 | [diff] [blame] | 32 | memory@c0000000 { |
| 33 | device_type = "memory"; |
| 34 | reg = <0xc0000000 0x40000000>; |
| 35 | }; |
Manivannan Sadhasivam | 02a66d6 | 2019-04-26 18:43:50 +0530 | [diff] [blame] | 36 | }; |
| 37 | |
| 38 | &i2c4 { |
| 39 | pinctrl-names = "default"; |
| 40 | pinctrl-0 = <&i2c4_pins_a>; |
| 41 | i2c-scl-rising-time-ns = <185>; |
| 42 | i2c-scl-falling-time-ns = <20>; |
| 43 | status = "okay"; |
| 44 | |
| 45 | pmic: stpmic@33 { |
| 46 | compatible = "st,stpmic1"; |
| 47 | reg = <0x33>; |
| 48 | interrupts-extended = <&exti_pwr 55 IRQ_TYPE_EDGE_FALLING>; |
| 49 | interrupt-controller; |
| 50 | #interrupt-cells = <2>; |
| 51 | status = "okay"; |
| 52 | |
| 53 | st,main-control-register = <0x04>; |
| 54 | st,vin-control-register = <0xc0>; |
Yann Gautier | 4ede20a | 2020-09-18 15:04:14 +0200 | [diff] [blame] | 55 | st,usb-control-register = <0x30>; |
Manivannan Sadhasivam | 02a66d6 | 2019-04-26 18:43:50 +0530 | [diff] [blame] | 56 | |
| 57 | regulators { |
| 58 | compatible = "st,stpmic1-regulators"; |
Manivannan Sadhasivam | 02a66d6 | 2019-04-26 18:43:50 +0530 | [diff] [blame] | 59 | ldo1-supply = <&v3v3>; |
| 60 | ldo2-supply = <&v3v3>; |
| 61 | ldo3-supply = <&vdd_ddr>; |
| 62 | ldo5-supply = <&v3v3>; |
| 63 | ldo6-supply = <&v3v3>; |
Yann Gautier | 4ede20a | 2020-09-18 15:04:14 +0200 | [diff] [blame] | 64 | pwr_sw1-supply = <&bst_out>; |
| 65 | pwr_sw2-supply = <&bst_out>; |
Manivannan Sadhasivam | 02a66d6 | 2019-04-26 18:43:50 +0530 | [diff] [blame] | 66 | |
| 67 | vddcore: buck1 { |
| 68 | regulator-name = "vddcore"; |
| 69 | regulator-min-microvolt = <1200000>; |
| 70 | regulator-max-microvolt = <1350000>; |
| 71 | regulator-always-on; |
| 72 | regulator-initial-mode = <0>; |
| 73 | regulator-over-current-protection; |
| 74 | }; |
| 75 | |
| 76 | vdd_ddr: buck2 { |
| 77 | regulator-name = "vdd_ddr"; |
| 78 | regulator-min-microvolt = <1350000>; |
| 79 | regulator-max-microvolt = <1350000>; |
| 80 | regulator-always-on; |
| 81 | regulator-initial-mode = <0>; |
| 82 | regulator-over-current-protection; |
| 83 | }; |
| 84 | |
| 85 | vdd: buck3 { |
| 86 | regulator-name = "vdd"; |
| 87 | regulator-min-microvolt = <3300000>; |
| 88 | regulator-max-microvolt = <3300000>; |
| 89 | regulator-always-on; |
| 90 | st,mask-reset; |
| 91 | regulator-initial-mode = <0>; |
| 92 | regulator-over-current-protection; |
| 93 | }; |
| 94 | |
| 95 | v3v3: buck4 { |
| 96 | regulator-name = "v3v3"; |
| 97 | regulator-min-microvolt = <3300000>; |
| 98 | regulator-max-microvolt = <3300000>; |
| 99 | regulator-always-on; |
| 100 | regulator-over-current-protection; |
| 101 | regulator-initial-mode = <0>; |
| 102 | }; |
| 103 | |
| 104 | vdda: ldo1 { |
| 105 | regulator-name = "vdda"; |
| 106 | regulator-min-microvolt = <2900000>; |
| 107 | regulator-max-microvolt = <2900000>; |
| 108 | }; |
| 109 | |
| 110 | v2v8: ldo2 { |
| 111 | regulator-name = "v2v8"; |
| 112 | regulator-min-microvolt = <2800000>; |
| 113 | regulator-max-microvolt = <2800000>; |
| 114 | }; |
| 115 | |
| 116 | vtt_ddr: ldo3 { |
| 117 | regulator-name = "vtt_ddr"; |
Manivannan Sadhasivam | 02a66d6 | 2019-04-26 18:43:50 +0530 | [diff] [blame] | 118 | regulator-always-on; |
| 119 | regulator-over-current-protection; |
Ahmad Fatoum | 9d3c53c | 2022-06-02 06:28:31 +0200 | [diff] [blame] | 120 | st,regulator-sink-source; |
Manivannan Sadhasivam | 02a66d6 | 2019-04-26 18:43:50 +0530 | [diff] [blame] | 121 | }; |
| 122 | |
| 123 | vdd_usb: ldo4 { |
| 124 | regulator-name = "vdd_usb"; |
| 125 | regulator-min-microvolt = <3300000>; |
| 126 | regulator-max-microvolt = <3300000>; |
| 127 | }; |
| 128 | |
| 129 | vdd_sd: ldo5 { |
| 130 | regulator-name = "vdd_sd"; |
| 131 | regulator-min-microvolt = <2900000>; |
| 132 | regulator-max-microvolt = <2900000>; |
| 133 | regulator-boot-on; |
| 134 | }; |
| 135 | |
| 136 | v1v8: ldo6 { |
| 137 | regulator-name = "v1v8"; |
| 138 | regulator-min-microvolt = <1800000>; |
| 139 | regulator-max-microvolt = <1800000>; |
| 140 | }; |
| 141 | |
| 142 | vref_ddr: vref_ddr { |
| 143 | regulator-name = "vref_ddr"; |
| 144 | regulator-always-on; |
Manivannan Sadhasivam | 02a66d6 | 2019-04-26 18:43:50 +0530 | [diff] [blame] | 145 | }; |
Yann Gautier | 4ede20a | 2020-09-18 15:04:14 +0200 | [diff] [blame] | 146 | |
| 147 | bst_out: boost { |
| 148 | regulator-name = "bst_out"; |
| 149 | }; |
| 150 | |
| 151 | vbus_otg: pwr_sw1 { |
| 152 | regulator-name = "vbus_otg"; |
| 153 | }; |
| 154 | |
| 155 | vbus_sw: pwr_sw2 { |
| 156 | regulator-name = "vbus_sw"; |
| 157 | regulator-active-discharge = <1>; |
| 158 | }; |
Manivannan Sadhasivam | 02a66d6 | 2019-04-26 18:43:50 +0530 | [diff] [blame] | 159 | }; |
| 160 | }; |
| 161 | }; |
| 162 | |
| 163 | &iwdg2 { |
| 164 | timeout-sec = <32>; |
| 165 | status = "okay"; |
Manivannan Sadhasivam | 02a66d6 | 2019-04-26 18:43:50 +0530 | [diff] [blame] | 166 | }; |
| 167 | |
Yann Gautier | 4ede20a | 2020-09-18 15:04:14 +0200 | [diff] [blame] | 168 | &pwr_regulators { |
| 169 | vdd-supply = <&vdd>; |
| 170 | vdd_3v3_usbfs-supply = <&vdd_usb>; |
Manivannan Sadhasivam | 02a66d6 | 2019-04-26 18:43:50 +0530 | [diff] [blame] | 171 | }; |
| 172 | |
Manivannan Sadhasivam | 02a66d6 | 2019-04-26 18:43:50 +0530 | [diff] [blame] | 173 | &rcc { |
Manivannan Sadhasivam | 02a66d6 | 2019-04-26 18:43:50 +0530 | [diff] [blame] | 174 | st,clksrc = < |
| 175 | CLK_MPU_PLL1P |
| 176 | CLK_AXI_PLL2P |
| 177 | CLK_MCU_PLL3P |
Manivannan Sadhasivam | 02a66d6 | 2019-04-26 18:43:50 +0530 | [diff] [blame] | 178 | CLK_RTC_LSE |
| 179 | CLK_MCO1_DISABLED |
| 180 | CLK_MCO2_DISABLED |
Manivannan Sadhasivam | 02a66d6 | 2019-04-26 18:43:50 +0530 | [diff] [blame] | 181 | CLK_CKPER_HSE |
| 182 | CLK_FMC_ACLK |
| 183 | CLK_QSPI_ACLK |
| 184 | CLK_ETH_DISABLED |
| 185 | CLK_SDMMC12_PLL4P |
| 186 | CLK_DSI_DSIPLL |
| 187 | CLK_STGEN_HSE |
| 188 | CLK_USBPHY_HSE |
| 189 | CLK_SPI2S1_PLL3Q |
| 190 | CLK_SPI2S23_PLL3Q |
| 191 | CLK_SPI45_HSI |
| 192 | CLK_SPI6_HSI |
| 193 | CLK_I2C46_HSI |
| 194 | CLK_SDMMC3_PLL4P |
| 195 | CLK_USBO_USBPHY |
| 196 | CLK_ADC_CKPER |
| 197 | CLK_CEC_LSE |
| 198 | CLK_I2C12_HSI |
| 199 | CLK_I2C35_HSI |
| 200 | CLK_UART1_HSI |
| 201 | CLK_UART24_HSI |
| 202 | CLK_UART35_HSI |
| 203 | CLK_UART6_HSI |
| 204 | CLK_UART78_HSI |
| 205 | CLK_SPDIF_PLL4P |
Antonio Borneo | dd445ab | 2019-07-29 14:46:16 +0200 | [diff] [blame] | 206 | CLK_FDCAN_PLL4R |
Manivannan Sadhasivam | 02a66d6 | 2019-04-26 18:43:50 +0530 | [diff] [blame] | 207 | CLK_SAI1_PLL3Q |
| 208 | CLK_SAI2_PLL3Q |
| 209 | CLK_SAI3_PLL3Q |
| 210 | CLK_SAI4_PLL3Q |
Lionel Debieve | 7a4308f | 2022-02-23 00:05:51 +0100 | [diff] [blame] | 211 | CLK_RNG1_CSI |
Manivannan Sadhasivam | 02a66d6 | 2019-04-26 18:43:50 +0530 | [diff] [blame] | 212 | CLK_RNG2_LSI |
| 213 | CLK_LPTIM1_PCLK1 |
| 214 | CLK_LPTIM23_PCLK3 |
| 215 | CLK_LPTIM45_LSE |
| 216 | >; |
| 217 | |
Gabriel Fernandez | df4be52 | 2022-08-16 11:40:03 +0200 | [diff] [blame] | 218 | st,clkdiv = < |
| 219 | DIV(DIV_MPU, 1) |
| 220 | DIV(DIV_AXI, 0) |
| 221 | DIV(DIV_MCU, 0) |
| 222 | DIV(DIV_APB1, 1) |
| 223 | DIV(DIV_APB2, 1) |
| 224 | DIV(DIV_APB3, 1) |
| 225 | DIV(DIV_APB4, 1) |
| 226 | DIV(DIV_APB5, 2) |
| 227 | DIV(DIV_RTC, 23) |
| 228 | DIV(DIV_MCO1, 0) |
| 229 | DIV(DIV_MCO2, 0) |
| 230 | >; |
| 231 | |
| 232 | st,pll_vco { |
Gabriel Fernandez | df4be52 | 2022-08-16 11:40:03 +0200 | [diff] [blame] | 233 | pll2_vco_1066Mhz: pll2-vco-1066Mhz { |
| 234 | src = <CLK_PLL12_HSE>; |
| 235 | divmn = <2 65>; |
| 236 | frac = <0x1400>; |
| 237 | }; |
| 238 | |
| 239 | pll3_vco_417Mhz: pll3-vco-417Mhz { |
| 240 | src = <CLK_PLL3_HSE>; |
| 241 | divmn = <1 33>; |
| 242 | frac = <0x1a04>; |
| 243 | }; |
| 244 | |
| 245 | pll4_vco_480Mhz: pll4-vco-480Mhz { |
| 246 | src = <CLK_PLL4_HSE>; |
| 247 | divmn = <1 39>; |
| 248 | }; |
| 249 | }; |
| 250 | |
Manivannan Sadhasivam | 02a66d6 | 2019-04-26 18:43:50 +0530 | [diff] [blame] | 251 | /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */ |
| 252 | pll2: st,pll@1 { |
Yann Gautier | 4ede20a | 2020-09-18 15:04:14 +0200 | [diff] [blame] | 253 | compatible = "st,stm32mp1-pll"; |
| 254 | reg = <1>; |
Gabriel Fernandez | df4be52 | 2022-08-16 11:40:03 +0200 | [diff] [blame] | 255 | |
| 256 | st,pll = <&pll2_cfg1>; |
| 257 | |
| 258 | pll2_cfg1: pll2_cfg1 { |
| 259 | st,pll_vco = <&pll2_vco_1066Mhz>; |
| 260 | st,pll_div_pqr = <1 0 0>; |
| 261 | }; |
Manivannan Sadhasivam | 02a66d6 | 2019-04-26 18:43:50 +0530 | [diff] [blame] | 262 | }; |
| 263 | |
| 264 | /* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */ |
| 265 | pll3: st,pll@2 { |
Yann Gautier | 4ede20a | 2020-09-18 15:04:14 +0200 | [diff] [blame] | 266 | compatible = "st,stm32mp1-pll"; |
| 267 | reg = <2>; |
Gabriel Fernandez | df4be52 | 2022-08-16 11:40:03 +0200 | [diff] [blame] | 268 | |
| 269 | st,pll = <&pll3_cfg1>; |
| 270 | |
| 271 | pll3_cfg1: pll3_cfg1 { |
| 272 | st,pll_vco = <&pll3_vco_417Mhz>; |
| 273 | st,pll_div_pqr = <1 16 36>; |
| 274 | }; |
Manivannan Sadhasivam | 02a66d6 | 2019-04-26 18:43:50 +0530 | [diff] [blame] | 275 | }; |
| 276 | |
| 277 | /* VCO = 480.0 MHz => P = 120, Q = 40, R = 96 */ |
| 278 | pll4: st,pll@3 { |
Yann Gautier | 4ede20a | 2020-09-18 15:04:14 +0200 | [diff] [blame] | 279 | compatible = "st,stm32mp1-pll"; |
| 280 | reg = <3>; |
Gabriel Fernandez | df4be52 | 2022-08-16 11:40:03 +0200 | [diff] [blame] | 281 | |
| 282 | st,pll = <&pll4_cfg1>; |
| 283 | |
| 284 | pll4_cfg1: pll4_cfg1 { |
| 285 | st,pll_vco = <&pll4_vco_480Mhz>; |
| 286 | st,pll_div_pqr = <3 11 4>; |
| 287 | }; |
Manivannan Sadhasivam | 02a66d6 | 2019-04-26 18:43:50 +0530 | [diff] [blame] | 288 | }; |
| 289 | }; |
Yann Gautier | 4ede20a | 2020-09-18 15:04:14 +0200 | [diff] [blame] | 290 | |
| 291 | &rng1 { |
| 292 | status = "okay"; |
| 293 | }; |
| 294 | |
| 295 | &rtc { |
| 296 | status = "okay"; |
| 297 | }; |
| 298 | |
| 299 | &sdmmc1 { |
| 300 | pinctrl-names = "default"; |
| 301 | pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_a>; |
| 302 | st,sig-dir; |
| 303 | st,neg-edge; |
| 304 | st,use-ckin; |
| 305 | bus-width = <4>; |
| 306 | vmmc-supply = <&vdd_sd>; |
| 307 | status = "okay"; |
| 308 | }; |
| 309 | |
| 310 | &uart4 { |
| 311 | /* On Low speed expansion header */ |
| 312 | label = "LS-UART1"; |
| 313 | pinctrl-names = "default"; |
| 314 | pinctrl-0 = <&uart4_pins_b>; |
| 315 | status = "okay"; |
| 316 | }; |
| 317 | |
| 318 | &uart7 { |
| 319 | /* On Low speed expansion header */ |
| 320 | label = "LS-UART0"; |
| 321 | pinctrl-names = "default"; |
| 322 | pinctrl-0 = <&uart7_pins_a>; |
| 323 | status = "okay"; |
| 324 | }; |