fdts: stm32mp1: realign device tree with kernel
There is one dtsi file per SoC version:
- STM32MP151: common part for all version, Single Cortex-A7
- STM32MP153: Dual Cortex-A7
- STM32MP157: + GPU and DSI, but not needed for TF-A
The STM32MP15xC include a cryptography peripheral, add it in a dedicated
file.
There are 4 packages available, for which the IOs number change. Have one
file for each package. The 2 packages AB and AD are added.
STM32157A-DK1 and STM32MP157C-DK2 share most of their features, a common
dkx file is then created.
Some reordering is done in other files, and realign with kernel DT files.
The DDR files are generated with our internal tool, no changes in the
registers values.
Change-Id: I9f2ef00306310abe34b94c2f10fc7a77a10493d1
Signed-off-by: Yann Gautier <yann.gautier@st.com>
diff --git a/fdts/stm32mp157a-avenger96.dts b/fdts/stm32mp157a-avenger96.dts
index 907940c..b967736 100644
--- a/fdts/stm32mp157a-avenger96.dts
+++ b/fdts/stm32mp157a-avenger96.dts
@@ -9,21 +9,30 @@
/dts-v1/;
-#include "stm32mp157c.dtsi"
-#include "stm32mp157cac-pinctrl.dtsi"
+#include "stm32mp157.dtsi"
+#include "stm32mp15-pinctrl.dtsi"
+#include "stm32mp15xxac-pinctrl.dtsi"
+#include <dt-bindings/clock/stm32mp1-clksrc.h>
+#include "stm32mp15-ddr3-2x4Gb-1066-binG.dtsi"
/ {
model = "Arrow Electronics STM32MP157A Avenger96 board";
- compatible = "st,stm32mp157a-avenger96", "st,stm32mp157";
+ compatible = "arrow,stm32mp157a-avenger96", "st,stm32mp157";
aliases {
+ mmc0 = &sdmmc1;
serial0 = &uart4;
+ serial1 = &uart7;
};
chosen {
stdout-path = "serial0:115200n8";
};
+ memory@c0000000 {
+ device_type = "memory";
+ reg = <0xc0000000 0x40000000>;
+ };
};
&i2c4 {
@@ -43,16 +52,17 @@
st,main-control-register = <0x04>;
st,vin-control-register = <0xc0>;
- st,usb-control-register = <0x20>;
+ st,usb-control-register = <0x30>;
regulators {
compatible = "st,stpmic1-regulators";
-
ldo1-supply = <&v3v3>;
ldo2-supply = <&v3v3>;
ldo3-supply = <&vdd_ddr>;
ldo5-supply = <&v3v3>;
ldo6-supply = <&v3v3>;
+ pwr_sw1-supply = <&bst_out>;
+ pwr_sw2-supply = <&bst_out>;
vddcore: buck1 {
regulator-name = "vddcore";
@@ -135,6 +145,19 @@
regulator-always-on;
regulator-over-current-protection;
};
+
+ bst_out: boost {
+ regulator-name = "bst_out";
+ };
+
+ vbus_otg: pwr_sw1 {
+ regulator-name = "vbus_otg";
+ };
+
+ vbus_sw: pwr_sw2 {
+ regulator-name = "vbus_sw";
+ regulator-active-discharge = <1>;
+ };
};
};
};
@@ -142,56 +165,14 @@
&iwdg2 {
timeout-sec = <32>;
status = "okay";
-};
-
-&rng1 {
- status = "okay";
-};
-
-&rtc {
- status = "okay";
-};
-
-&sdmmc1 {
- pinctrl-names = "default";
- pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_a>;
- broken-cd;
- st,sig-dir;
- st,neg-edge;
- st,use-ckin;
- bus-width = <4>;
- vmmc-supply = <&vdda>;
- status = "okay";
-};
-
-&uart4 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart4_pins_b>;
- status = "okay";
+ secure-status = "okay";
};
-/* ATF Specific */
-#include <dt-bindings/clock/stm32mp1-clksrc.h>
-#include "stm32mp15-ddr3-2x4Gb-1066-binG.dtsi"
-#include "stm32mp157c-security.dtsi"
-
-/ {
- aliases {
- gpio0 = &gpioa;
- gpio1 = &gpiob;
- gpio2 = &gpioc;
- gpio3 = &gpiod;
- gpio4 = &gpioe;
- gpio5 = &gpiof;
- gpio6 = &gpiog;
- gpio7 = &gpioh;
- gpio8 = &gpioi;
- gpio25 = &gpioz;
- i2c3 = &i2c4;
- };
+&pwr_regulators {
+ vdd-supply = <&vdd>;
+ vdd_3v3_usbfs-supply = <&vdd_usb>;
};
-/* CLOCK init */
&rcc {
secure-status = "disabled";
st,clksrc = <
@@ -260,24 +241,67 @@
/* VCO = 1300.0 MHz => P = 650 (CPU) */
pll1: st,pll@0 {
- cfg = < 2 80 0 0 0 PQR(1,0,0) >;
- frac = < 0x800 >;
+ compatible = "st,stm32mp1-pll";
+ reg = <0>;
+ cfg = <2 80 0 0 0 PQR(1,0,0)>;
+ frac = <0x800>;
};
/* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
pll2: st,pll@1 {
- cfg = < 2 65 1 0 0 PQR(1,1,1) >;
- frac = < 0x1400 >;
+ compatible = "st,stm32mp1-pll";
+ reg = <1>;
+ cfg = <2 65 1 0 0 PQR(1,1,1)>;
+ frac = <0x1400>;
};
/* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
pll3: st,pll@2 {
- cfg = < 1 33 1 16 36 PQR(1,1,1) >;
- frac = < 0x1a04 >;
+ compatible = "st,stm32mp1-pll";
+ reg = <2>;
+ cfg = <1 33 1 16 36 PQR(1,1,1)>;
+ frac = <0x1a04>;
};
/* VCO = 480.0 MHz => P = 120, Q = 40, R = 96 */
pll4: st,pll@3 {
- cfg = < 1 39 3 11 4 PQR(1,1,1) >;
+ compatible = "st,stm32mp1-pll";
+ reg = <3>;
+ cfg = <1 39 3 11 4 PQR(1,1,1)>;
};
};
+
+&rng1 {
+ status = "okay";
+};
+
+&rtc {
+ status = "okay";
+};
+
+&sdmmc1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_a>;
+ st,sig-dir;
+ st,neg-edge;
+ st,use-ckin;
+ bus-width = <4>;
+ vmmc-supply = <&vdd_sd>;
+ status = "okay";
+};
+
+&uart4 {
+ /* On Low speed expansion header */
+ label = "LS-UART1";
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart4_pins_b>;
+ status = "okay";
+};
+
+&uart7 {
+ /* On Low speed expansion header */
+ label = "LS-UART0";
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart7_pins_a>;
+ status = "okay";
+};