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Yann Gautier0ed7b2a2021-05-19 18:48:16 +02001/*
Nicolas Toromanoff44adc4f2022-02-07 10:12:29 +01002 * Copyright (C) 2021-2023, STMicroelectronics - All Rights Reserved
Yann Gautier0ed7b2a2021-05-19 18:48:16 +02003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#ifndef STM32MP1_FIP_DEF_H
8#define STM32MP1_FIP_DEF_H
9
Yann Gautierbc9f0fd2022-06-30 11:33:27 +020010#if STM32MP15_OPTEE_RSV_SHM
Yann Gautier658775c2021-07-06 10:00:44 +020011#define STM32MP_DDR_S_SIZE U(0x01E00000) /* 30 MB */
12#define STM32MP_DDR_SHMEM_SIZE U(0x00200000) /* 2 MB */
Yann Gautierbc9f0fd2022-06-30 11:33:27 +020013#else
14#define STM32MP_DDR_S_SIZE U(0x02000000) /* 32 MB */
15#define STM32MP_DDR_SHMEM_SIZE U(0) /* empty */
16#endif
Yann Gautier658775c2021-07-06 10:00:44 +020017
Lionel Debieve13a668d2022-10-05 16:47:03 +020018#if TRUSTED_BOARD_BOOT && !STM32MP_USE_EXTERNAL_HEAP
19#if STM32MP15
20#define STM32MP_BL2_RO_SIZE U(0x00014000) /* 80 KB */
21#define STM32MP_BL2_SIZE U(0x0001B000) /* 108 KB for BL2 */
22#endif /* STM32MP15 */
23#else /* TRUSTED_BOARD_BOOT && !STM32MP_USE_EXTERNAL_HEAP */
Yann Gautier15e84832020-02-03 17:48:07 +010024#if STM32MP13
Lionel Debieve13a668d2022-10-05 16:47:03 +020025#if BL2_IN_XIP_MEM
Yann Gautier15e84832020-02-03 17:48:07 +010026#define STM32MP_BL2_RO_SIZE U(0x00015000) /* 84 KB */
27#define STM32MP_BL2_SIZE U(0x00017000) /* 92 KB for BL2 */
Lionel Debieve13a668d2022-10-05 16:47:03 +020028#else
29/* STM32MP_BL2_RO_SIZE not used if !BL2_IN_XIP_MEM */
30#define STM32MP_BL2_SIZE U(0x0001B000) /* 108KB for BL2 */
31 /* with 20KB for DTB, SYSRAM is full */
32#endif
Yann Gautier15e84832020-02-03 17:48:07 +010033#endif /* STM32MP13 */
34#if STM32MP15
Yann Gautier230bf912021-09-15 11:30:25 +020035#define STM32MP_BL2_RO_SIZE U(0x00011000) /* 68 KB */
36#define STM32MP_BL2_SIZE U(0x00016000) /* 88 KB for BL2 */
Lionel Debieve13a668d2022-10-05 16:47:03 +020037#endif /* STM32MP15 */
38#endif /* TRUSTED_BOARD_BOOT && !STM32MP_USE_EXTERNAL_HEAP */
39
40#if STM32MP13
41#if TRUSTED_BOARD_BOOT
42#define STM32MP_BL2_DTB_SIZE U(0x00005000) /* 20 KB for DTB */
43#else /* TRUSTED_BOARD_BOOT */
44#define STM32MP_BL2_DTB_SIZE U(0x00004000) /* 16 KB for DTB */
45#endif /* TRUSTED_BOARD_BOOT */
46#endif /* STM32MP13 */
47#if STM32MP15
Yann Gautier230bf912021-09-15 11:30:25 +020048#define STM32MP_BL2_DTB_SIZE U(0x00007000) /* 28 KB for DTB */
Yann Gautier15e84832020-02-03 17:48:07 +010049#endif /* STM32MP15 */
Yann Gautier230bf912021-09-15 11:30:25 +020050#define STM32MP_BL32_SIZE U(0x0001B000) /* 108 KB for BL32 */
Yann Gautier0ed7b2a2021-05-19 18:48:16 +020051#define STM32MP_BL32_DTB_SIZE U(0x00005000) /* 20 KB for DTB */
Yann Gautier658775c2021-07-06 10:00:44 +020052#define STM32MP_FW_CONFIG_MAX_SIZE PAGE_SIZE /* 4 KB for FCONF DTB */
Yann Gautier0ed7b2a2021-05-19 18:48:16 +020053#define STM32MP_HW_CONFIG_MAX_SIZE U(0x40000) /* 256 KB for HW config DTB */
54
Yann Gautier15e84832020-02-03 17:48:07 +010055#if STM32MP13
56#define STM32MP_BL2_BASE (STM32MP_BL2_DTB_BASE + \
57 STM32MP_BL2_DTB_SIZE)
58#endif /* STM32MP13 */
59#if STM32MP15
Yann Gautier0ed7b2a2021-05-19 18:48:16 +020060#define STM32MP_BL2_BASE (STM32MP_SEC_SYSRAM_BASE + \
61 STM32MP_SEC_SYSRAM_SIZE - \
62 STM32MP_BL2_SIZE)
Yann Gautier15e84832020-02-03 17:48:07 +010063#endif /* STM32MP15 */
Yann Gautier0ed7b2a2021-05-19 18:48:16 +020064
Yann Gautier230bf912021-09-15 11:30:25 +020065#define STM32MP_BL2_RO_BASE STM32MP_BL2_BASE
66
67#define STM32MP_BL2_RW_BASE (STM32MP_BL2_RO_BASE + \
68 STM32MP_BL2_RO_SIZE)
69
Yann Gautier15e84832020-02-03 17:48:07 +010070#if STM32MP13
71#define STM32MP_BL2_RW_SIZE (STM32MP_SYSRAM_BASE + \
72 STM32MP_SYSRAM_SIZE - \
73 STM32MP_BL2_RW_BASE)
74
75#define STM32MP_BL2_DTB_BASE STM32MP_SEC_SYSRAM_BASE
76#endif /* STM32MP13 */
77#if STM32MP15
Yann Gautier230bf912021-09-15 11:30:25 +020078#define STM32MP_BL2_RW_SIZE (STM32MP_SEC_SYSRAM_BASE + \
79 STM32MP_SEC_SYSRAM_SIZE - \
80 STM32MP_BL2_RW_BASE)
81
Yann Gautier0ed7b2a2021-05-19 18:48:16 +020082#define STM32MP_BL2_DTB_BASE (STM32MP_BL2_BASE - \
83 STM32MP_BL2_DTB_SIZE)
Yann Gautier15e84832020-02-03 17:48:07 +010084#endif /* STM32MP15 */
Yann Gautier0ed7b2a2021-05-19 18:48:16 +020085
86#define STM32MP_BL32_DTB_BASE STM32MP_SYSRAM_BASE
87
88#define STM32MP_BL32_BASE (STM32MP_BL32_DTB_BASE + \
89 STM32MP_BL32_DTB_SIZE)
90
Yann Gautier658775c2021-07-06 10:00:44 +020091
Yann Gautier0ed7b2a2021-05-19 18:48:16 +020092#if defined(IMAGE_BL2)
93#define STM32MP_DTB_SIZE STM32MP_BL2_DTB_SIZE
94#define STM32MP_DTB_BASE STM32MP_BL2_DTB_BASE
95#endif
96#if defined(IMAGE_BL32)
97#define STM32MP_DTB_SIZE STM32MP_BL32_DTB_SIZE
98#define STM32MP_DTB_BASE STM32MP_BL32_DTB_BASE
99#endif
100
101#ifdef AARCH32_SP_OPTEE
102#define STM32MP_OPTEE_BASE STM32MP_SEC_SYSRAM_BASE
103
104#define STM32MP_OPTEE_SIZE (STM32MP_BL2_DTB_BASE - \
105 STM32MP_OPTEE_BASE)
106#endif
107
Yann Gautier15e84832020-02-03 17:48:07 +0100108#if STM32MP13
109#define STM32MP_FW_CONFIG_BASE SRAM3_BASE
110#endif /* STM32MP13 */
111#if STM32MP15
Yann Gautier658775c2021-07-06 10:00:44 +0200112#define STM32MP_FW_CONFIG_BASE (STM32MP_SYSRAM_BASE + \
113 STM32MP_SYSRAM_SIZE - \
114 PAGE_SIZE)
Yann Gautier15e84832020-02-03 17:48:07 +0100115#endif /* STM32MP15 */
Yann Gautier0ed7b2a2021-05-19 18:48:16 +0200116#define STM32MP_HW_CONFIG_BASE (STM32MP_BL33_BASE + \
117 STM32MP_BL33_MAX_SIZE)
118
119/*
120 * MAX_MMAP_REGIONS is usually:
121 * BL stm32mp1_mmap size + mmap regions in *_plat_arch_setup
122 */
123#if defined(IMAGE_BL32)
124#define MAX_MMAP_REGIONS 10
125#endif
126
127/*******************************************************************************
Ahmad Fatoumbd685282022-05-19 07:42:33 +0200128 * STM32MP1 RAW partition offset for devices without GPT
Yann Gautier0ed7b2a2021-05-19 18:48:16 +0200129 ******************************************************************************/
Ahmad Fatoumbd685282022-05-19 07:42:33 +0200130#define STM32MP_EMMC_BOOT_FIP_OFFSET U(0x00040000)
Nicolas Toromanoff44adc4f2022-02-07 10:12:29 +0100131#if PSA_FWU_SUPPORT
132#define STM32MP_NOR_METADATA1_OFFSET U(0x00080000)
133#define STM32MP_NOR_METADATA2_OFFSET U(0x000C0000)
134#define STM32MP_NOR_FIP_A_OFFSET U(0x00100000)
135#define STM32MP_NOR_FIP_A_GUID (const struct efi_guid)EFI_GUID(0x4fd84c93, \
136 0x54ef, 0x463f, 0xa7, 0xef, 0xae, 0x25, 0xff,\
137 0x88, 0x70, 0x87)
138
139#define STM32MP_NOR_FIP_B_OFFSET U(0x00500000)
140#define STM32MP_NOR_FIP_B_GUID (const struct efi_guid)EFI_GUID(0x09c54952, \
141 0xd5bf, 0x45af, 0xac, 0xee, 0x33, 0x53, 0x03,\
142 0x76, 0x6f, 0xb3)
143
144#else /* PSA_FWU_SUPPORT */
Lionel Debieveaf199382021-01-13 07:59:59 +0100145#ifndef STM32MP_NOR_FIP_OFFSET
Yann Gautier0ed7b2a2021-05-19 18:48:16 +0200146#define STM32MP_NOR_FIP_OFFSET U(0x00080000)
Lionel Debieveaf199382021-01-13 07:59:59 +0100147#endif
148#ifndef STM32MP_NAND_FIP_OFFSET
Yann Gautier0ed7b2a2021-05-19 18:48:16 +0200149#define STM32MP_NAND_FIP_OFFSET U(0x00200000)
Lionel Debieveaf199382021-01-13 07:59:59 +0100150#endif
Nicolas Toromanoff44adc4f2022-02-07 10:12:29 +0100151#endif /* PSA_FWU_SUPPORT */
Yann Gautier0ed7b2a2021-05-19 18:48:16 +0200152
153#endif /* STM32MP1_FIP_DEF_H */