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Dan Handley9df48042015-03-19 18:58:55 +00001/*
Madhukar Pappireddyd7419442020-01-27 15:38:26 -06002 * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
Dan Handley9df48042015-03-19 18:58:55 +00003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Dan Handley9df48042015-03-19 18:58:55 +00005 */
Antonio Nino Diaz6f3ccc52018-07-20 09:17:26 +01006#ifndef ARM_DEF_H
7#define ARM_DEF_H
Dan Handley9df48042015-03-19 18:58:55 +00008
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00009#include <arch.h>
10#include <common/interrupt_props.h>
11#include <common/tbbr/tbbr_img_def.h>
12#include <drivers/arm/gic_common.h>
13#include <lib/utils_def.h>
14#include <lib/xlat_tables/xlat_tables_defs.h>
Manish V Badarkhe55861512020-03-27 13:25:51 +000015#include <plat/arm/common/smccc_def.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000016#include <plat/common/common_def.h>
Dan Handley9df48042015-03-19 18:58:55 +000017
18/******************************************************************************
19 * Definitions common to all ARM standard platforms
20 *****************************************************************************/
21
Max Shvetsov06dba292019-12-06 11:50:12 +000022/*
23 * Root of trust key hash lengths
24 */
25#define ARM_ROTPK_HEADER_LEN 19
26#define ARM_ROTPK_HASH_LEN 32
27
Juan Castillo7d199412015-12-14 09:35:25 +000028/* Special value used to verify platform parameters from BL2 to BL31 */
Antonio Nino Diazab5d2b12018-10-30 16:12:32 +000029#define ARM_BL31_PLAT_PARAM_VAL ULL(0x0f1e2d3c4b5a6978)
Dan Handley9df48042015-03-19 18:58:55 +000030
Deepika Bhavnani4287c0c2019-12-13 10:23:18 -060031#define ARM_SYSTEM_COUNT U(1)
Dan Handley9df48042015-03-19 18:58:55 +000032
33#define ARM_CACHE_WRITEBACK_SHIFT 6
34
Soby Mathewfec4eb72015-07-01 16:16:20 +010035/*
36 * Macros mapping the MPIDR Affinity levels to ARM Platform Power levels. The
37 * power levels have a 1:1 mapping with the MPIDR affinity levels.
38 */
39#define ARM_PWR_LVL0 MPIDR_AFFLVL0
40#define ARM_PWR_LVL1 MPIDR_AFFLVL1
Soby Mathewa869de12015-05-08 10:18:59 +010041#define ARM_PWR_LVL2 MPIDR_AFFLVL2
Chandni Cherukuri9ec4a112018-10-16 14:42:19 +053042#define ARM_PWR_LVL3 MPIDR_AFFLVL3
Soby Mathewfec4eb72015-07-01 16:16:20 +010043
44/*
45 * Macros for local power states in ARM platforms encoded by State-ID field
46 * within the power-state parameter.
47 */
48/* Local power state for power domains in Run state. */
Antonio Nino Diaz6f3ccc52018-07-20 09:17:26 +010049#define ARM_LOCAL_STATE_RUN U(0)
Soby Mathewfec4eb72015-07-01 16:16:20 +010050/* Local power state for retention. Valid only for CPU power domains */
Antonio Nino Diaz6f3ccc52018-07-20 09:17:26 +010051#define ARM_LOCAL_STATE_RET U(1)
Soby Mathewfec4eb72015-07-01 16:16:20 +010052/* Local power state for OFF/power-down. Valid for CPU and cluster power
53 domains */
Antonio Nino Diaz6f3ccc52018-07-20 09:17:26 +010054#define ARM_LOCAL_STATE_OFF U(2)
Soby Mathewfec4eb72015-07-01 16:16:20 +010055
Dan Handley9df48042015-03-19 18:58:55 +000056/* Memory location options for TSP */
57#define ARM_TRUSTED_SRAM_ID 0
58#define ARM_TRUSTED_DRAM_ID 1
59#define ARM_DRAM_ID 2
60
61/* The first 4KB of Trusted SRAM are used as shared memory */
Antonio Nino Diaz5f475792018-10-15 14:58:11 +010062#define ARM_TRUSTED_SRAM_BASE UL(0x04000000)
Dan Handley9df48042015-03-19 18:58:55 +000063#define ARM_SHARED_RAM_BASE ARM_TRUSTED_SRAM_BASE
Antonio Nino Diaz5f475792018-10-15 14:58:11 +010064#define ARM_SHARED_RAM_SIZE UL(0x00001000) /* 4 KB */
Dan Handley9df48042015-03-19 18:58:55 +000065
66/* The remaining Trusted SRAM is used to load the BL images */
67#define ARM_BL_RAM_BASE (ARM_SHARED_RAM_BASE + \
68 ARM_SHARED_RAM_SIZE)
69#define ARM_BL_RAM_SIZE (PLAT_ARM_TRUSTED_SRAM_SIZE - \
70 ARM_SHARED_RAM_SIZE)
71
72/*
73 * The top 16MB of DRAM1 is configured as secure access only using the TZC
74 * - SCP TZC DRAM: If present, DRAM reserved for SCP use
75 * - AP TZC DRAM: The remaining TZC secured DRAM reserved for AP use
76 */
Antonio Nino Diaz5f475792018-10-15 14:58:11 +010077#define ARM_TZC_DRAM1_SIZE UL(0x01000000)
Dan Handley9df48042015-03-19 18:58:55 +000078
79#define ARM_SCP_TZC_DRAM1_BASE (ARM_DRAM1_BASE + \
80 ARM_DRAM1_SIZE - \
81 ARM_SCP_TZC_DRAM1_SIZE)
82#define ARM_SCP_TZC_DRAM1_SIZE PLAT_ARM_SCP_TZC_DRAM1_SIZE
83#define ARM_SCP_TZC_DRAM1_END (ARM_SCP_TZC_DRAM1_BASE + \
Alexei Fedorovc7176172020-07-13 12:11:05 +010084 ARM_SCP_TZC_DRAM1_SIZE - 1U)
Dan Handley9df48042015-03-19 18:58:55 +000085
Soby Mathew3b5156e2017-10-05 12:27:33 +010086/*
87 * Define a 2MB region within the TZC secured DRAM for use by EL3 runtime
88 * firmware. This region is meant to be NOLOAD and will not be zero
89 * initialized. Data sections with the attribute `arm_el3_tzc_dram` will be
90 * placed here.
91 */
92#define ARM_EL3_TZC_DRAM1_BASE (ARM_SCP_TZC_DRAM1_BASE - ARM_EL3_TZC_DRAM1_SIZE)
Antonio Nino Diaz5f475792018-10-15 14:58:11 +010093#define ARM_EL3_TZC_DRAM1_SIZE UL(0x00200000) /* 2 MB */
Soby Mathew3b5156e2017-10-05 12:27:33 +010094#define ARM_EL3_TZC_DRAM1_END (ARM_EL3_TZC_DRAM1_BASE + \
Alexei Fedorovc7176172020-07-13 12:11:05 +010095 ARM_EL3_TZC_DRAM1_SIZE - 1U)
Soby Mathew3b5156e2017-10-05 12:27:33 +010096
Dan Handley9df48042015-03-19 18:58:55 +000097#define ARM_AP_TZC_DRAM1_BASE (ARM_DRAM1_BASE + \
98 ARM_DRAM1_SIZE - \
99 ARM_TZC_DRAM1_SIZE)
100#define ARM_AP_TZC_DRAM1_SIZE (ARM_TZC_DRAM1_SIZE - \
Soby Mathew3b5156e2017-10-05 12:27:33 +0100101 (ARM_SCP_TZC_DRAM1_SIZE + \
102 ARM_EL3_TZC_DRAM1_SIZE))
Dan Handley9df48042015-03-19 18:58:55 +0000103#define ARM_AP_TZC_DRAM1_END (ARM_AP_TZC_DRAM1_BASE + \
Alexei Fedorovc7176172020-07-13 12:11:05 +0100104 ARM_AP_TZC_DRAM1_SIZE - 1U)
Dan Handley9df48042015-03-19 18:58:55 +0000105
Soby Mathew7e4d6652017-05-10 11:50:30 +0100106/* Define the Access permissions for Secure peripherals to NS_DRAM */
107#if ARM_CRYPTOCELL_INTEG
108/*
109 * Allow Secure peripheral to read NS DRAM when integrated with CryptoCell.
110 * This is required by CryptoCell to authenticate BL33 which is loaded
111 * into the Non Secure DDR.
112 */
113#define ARM_TZC_NS_DRAM_S_ACCESS TZC_REGION_S_RD
114#else
115#define ARM_TZC_NS_DRAM_S_ACCESS TZC_REGION_S_NONE
116#endif
117
Summer Qin9db8f2e2017-04-24 16:49:28 +0100118#ifdef SPD_opteed
119/*
Jens Wiklanderae73b162017-08-24 15:39:09 +0200120 * BL2 needs to map 4MB at the end of TZC_DRAM1 in order to
121 * load/authenticate the trusted os extra image. The first 512KB of
122 * TZC_DRAM1 are reserved for trusted os (OPTEE). The extra image loading
123 * for OPTEE is paged image which only include the paging part using
124 * virtual memory but without "init" data. OPTEE will copy the "init" data
125 * (from pager image) to the first 512KB of TZC_DRAM, and then copy the
126 * extra image behind the "init" data.
Summer Qin9db8f2e2017-04-24 16:49:28 +0100127 */
Jens Wiklanderae73b162017-08-24 15:39:09 +0200128#define ARM_OPTEE_PAGEABLE_LOAD_BASE (ARM_AP_TZC_DRAM1_BASE + \
129 ARM_AP_TZC_DRAM1_SIZE - \
130 ARM_OPTEE_PAGEABLE_LOAD_SIZE)
Antonio Nino Diaz5f475792018-10-15 14:58:11 +0100131#define ARM_OPTEE_PAGEABLE_LOAD_SIZE UL(0x400000)
Summer Qin9db8f2e2017-04-24 16:49:28 +0100132#define ARM_OPTEE_PAGEABLE_LOAD_MEM MAP_REGION_FLAT( \
133 ARM_OPTEE_PAGEABLE_LOAD_BASE, \
134 ARM_OPTEE_PAGEABLE_LOAD_SIZE, \
135 MT_MEMORY | MT_RW | MT_SECURE)
Soby Mathew874fc9e2017-09-01 13:43:50 +0100136
137/*
138 * Map the memory for the OP-TEE core (also known as OP-TEE pager when paging
139 * support is enabled).
140 */
141#define ARM_MAP_OPTEE_CORE_MEM MAP_REGION_FLAT( \
142 BL32_BASE, \
143 BL32_LIMIT - BL32_BASE, \
144 MT_MEMORY | MT_RW | MT_SECURE)
Summer Qin9db8f2e2017-04-24 16:49:28 +0100145#endif /* SPD_opteed */
Dan Handley9df48042015-03-19 18:58:55 +0000146
147#define ARM_NS_DRAM1_BASE ARM_DRAM1_BASE
148#define ARM_NS_DRAM1_SIZE (ARM_DRAM1_SIZE - \
149 ARM_TZC_DRAM1_SIZE)
150#define ARM_NS_DRAM1_END (ARM_NS_DRAM1_BASE + \
Alexei Fedorovc7176172020-07-13 12:11:05 +0100151 ARM_NS_DRAM1_SIZE - 1U)
Dan Handley9df48042015-03-19 18:58:55 +0000152
Sandrine Bailleux6c32fc72018-10-31 14:28:17 +0100153#define ARM_DRAM1_BASE ULL(0x80000000)
154#define ARM_DRAM1_SIZE ULL(0x80000000)
Dan Handley9df48042015-03-19 18:58:55 +0000155#define ARM_DRAM1_END (ARM_DRAM1_BASE + \
Alexei Fedorovc7176172020-07-13 12:11:05 +0100156 ARM_DRAM1_SIZE - 1U)
Dan Handley9df48042015-03-19 18:58:55 +0000157
Sami Mujawara43ae7c2019-05-09 13:35:02 +0100158#define ARM_DRAM2_BASE PLAT_ARM_DRAM2_BASE
Dan Handley9df48042015-03-19 18:58:55 +0000159#define ARM_DRAM2_SIZE PLAT_ARM_DRAM2_SIZE
160#define ARM_DRAM2_END (ARM_DRAM2_BASE + \
Alexei Fedorovc7176172020-07-13 12:11:05 +0100161 ARM_DRAM2_SIZE - 1U)
Dan Handley9df48042015-03-19 18:58:55 +0000162
163#define ARM_IRQ_SEC_PHY_TIMER 29
164
165#define ARM_IRQ_SEC_SGI_0 8
166#define ARM_IRQ_SEC_SGI_1 9
167#define ARM_IRQ_SEC_SGI_2 10
168#define ARM_IRQ_SEC_SGI_3 11
169#define ARM_IRQ_SEC_SGI_4 12
170#define ARM_IRQ_SEC_SGI_5 13
171#define ARM_IRQ_SEC_SGI_6 14
172#define ARM_IRQ_SEC_SGI_7 15
173
Achin Gupta1fa7eb62015-11-03 14:18:34 +0000174/*
Jeenu Viswambharan723dce02017-09-22 08:59:59 +0100175 * Define a list of Group 1 Secure and Group 0 interrupt properties as per GICv3
176 * terminology. On a GICv2 system or mode, the lists will be merged and treated
177 * as Group 0 interrupts.
178 */
179#define ARM_G1S_IRQ_PROPS(grp) \
Antonio Nino Diaze590fd52018-08-21 09:42:26 +0100180 INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, (grp), \
Jeenu Viswambharan723dce02017-09-22 08:59:59 +0100181 GIC_INTR_CFG_LEVEL), \
Antonio Nino Diaze590fd52018-08-21 09:42:26 +0100182 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, (grp), \
Jeenu Viswambharan723dce02017-09-22 08:59:59 +0100183 GIC_INTR_CFG_EDGE), \
Antonio Nino Diaze590fd52018-08-21 09:42:26 +0100184 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, (grp), \
Jeenu Viswambharan723dce02017-09-22 08:59:59 +0100185 GIC_INTR_CFG_EDGE), \
Antonio Nino Diaze590fd52018-08-21 09:42:26 +0100186 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, (grp), \
Jeenu Viswambharan723dce02017-09-22 08:59:59 +0100187 GIC_INTR_CFG_EDGE), \
Antonio Nino Diaze590fd52018-08-21 09:42:26 +0100188 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, (grp), \
Jeenu Viswambharan723dce02017-09-22 08:59:59 +0100189 GIC_INTR_CFG_EDGE), \
Antonio Nino Diaze590fd52018-08-21 09:42:26 +0100190 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, (grp), \
Jeenu Viswambharan723dce02017-09-22 08:59:59 +0100191 GIC_INTR_CFG_EDGE), \
Antonio Nino Diaze590fd52018-08-21 09:42:26 +0100192 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, (grp), \
Jeenu Viswambharan723dce02017-09-22 08:59:59 +0100193 GIC_INTR_CFG_EDGE)
194
195#define ARM_G0_IRQ_PROPS(grp) \
Antonio Nino Diaze590fd52018-08-21 09:42:26 +0100196 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_0, PLAT_SDEI_NORMAL_PRI, (grp), \
Jeenu Viswambharan723dce02017-09-22 08:59:59 +0100197 GIC_INTR_CFG_EDGE), \
Antonio Nino Diaze590fd52018-08-21 09:42:26 +0100198 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, (grp), \
Jeenu Viswambharan723dce02017-09-22 08:59:59 +0100199 GIC_INTR_CFG_EDGE)
200
Dan Handley9df48042015-03-19 18:58:55 +0000201#define ARM_MAP_SHARED_RAM MAP_REGION_FLAT( \
202 ARM_SHARED_RAM_BASE, \
203 ARM_SHARED_RAM_SIZE, \
Juan Castillo2e86cb12016-01-13 15:01:09 +0000204 MT_DEVICE | MT_RW | MT_SECURE)
Dan Handley9df48042015-03-19 18:58:55 +0000205
206#define ARM_MAP_NS_DRAM1 MAP_REGION_FLAT( \
207 ARM_NS_DRAM1_BASE, \
208 ARM_NS_DRAM1_SIZE, \
209 MT_MEMORY | MT_RW | MT_NS)
210
Roberto Vargasf8fda102017-08-08 11:27:20 +0100211#define ARM_MAP_DRAM2 MAP_REGION_FLAT( \
212 ARM_DRAM2_BASE, \
213 ARM_DRAM2_SIZE, \
214 MT_MEMORY | MT_RW | MT_NS)
Roberto Vargasf8fda102017-08-08 11:27:20 +0100215
Dan Handley9df48042015-03-19 18:58:55 +0000216#define ARM_MAP_TSP_SEC_MEM MAP_REGION_FLAT( \
217 TSP_SEC_MEM_BASE, \
218 TSP_SEC_MEM_SIZE, \
219 MT_MEMORY | MT_RW | MT_SECURE)
220
David Wang0ba499f2016-03-07 11:02:57 +0800221#if ARM_BL31_IN_DRAM
222#define ARM_MAP_BL31_SEC_DRAM MAP_REGION_FLAT( \
223 BL31_BASE, \
224 PLAT_ARM_MAX_BL31_SIZE, \
225 MT_MEMORY | MT_RW | MT_SECURE)
226#endif
Dan Handley9df48042015-03-19 18:58:55 +0000227
Soby Mathew3b5156e2017-10-05 12:27:33 +0100228#define ARM_MAP_EL3_TZC_DRAM MAP_REGION_FLAT( \
229 ARM_EL3_TZC_DRAM1_BASE, \
230 ARM_EL3_TZC_DRAM1_SIZE, \
231 MT_MEMORY | MT_RW | MT_SECURE)
232
Achin Guptae97351d2019-10-11 15:15:19 +0100233#if defined(SPD_spmd)
234#define ARM_MAP_TRUSTED_DRAM MAP_REGION_FLAT( \
235 PLAT_ARM_TRUSTED_DRAM_BASE, \
236 PLAT_ARM_TRUSTED_DRAM_SIZE, \
237 MT_MEMORY | MT_RW | MT_SECURE)
238#endif
239
240
Daniel Boulby4e97abd2018-07-16 14:09:15 +0100241/*
John Tsichritzisc34341a2018-07-30 13:41:52 +0100242 * Mapping for the BL1 RW region. This mapping is needed by BL2 in order to
243 * share the Mbed TLS heap. Since the heap is allocated inside BL1, it resides
244 * in the BL1 RW region. Hence, BL2 needs access to the BL1 RW region in order
245 * to be able to access the heap.
246 */
247#define ARM_MAP_BL1_RW MAP_REGION_FLAT( \
248 BL1_RW_BASE, \
249 BL1_RW_LIMIT - BL1_RW_BASE, \
250 MT_MEMORY | MT_RW | MT_SECURE)
251
252/*
Daniel Boulby4e97abd2018-07-16 14:09:15 +0100253 * If SEPARATE_CODE_AND_RODATA=1 we define a region for each section
254 * otherwise one region is defined containing both.
255 */
Daniel Boulby45a2c9e2018-07-06 16:54:44 +0100256#if SEPARATE_CODE_AND_RODATA
Daniel Boulby4e97abd2018-07-16 14:09:15 +0100257#define ARM_MAP_BL_RO MAP_REGION_FLAT( \
Daniel Boulby45a2c9e2018-07-06 16:54:44 +0100258 BL_CODE_BASE, \
259 BL_CODE_END - BL_CODE_BASE, \
Daniel Boulby4e97abd2018-07-16 14:09:15 +0100260 MT_CODE | MT_SECURE), \
261 MAP_REGION_FLAT( \
Daniel Boulby45a2c9e2018-07-06 16:54:44 +0100262 BL_RO_DATA_BASE, \
263 BL_RO_DATA_END \
264 - BL_RO_DATA_BASE, \
265 MT_RO_DATA | MT_SECURE)
Daniel Boulby4e97abd2018-07-16 14:09:15 +0100266#else
267#define ARM_MAP_BL_RO MAP_REGION_FLAT( \
268 BL_CODE_BASE, \
269 BL_CODE_END - BL_CODE_BASE, \
270 MT_CODE | MT_SECURE)
Daniel Boulby45a2c9e2018-07-06 16:54:44 +0100271#endif
272#if USE_COHERENT_MEM
273#define ARM_MAP_BL_COHERENT_RAM MAP_REGION_FLAT( \
274 BL_COHERENT_RAM_BASE, \
275 BL_COHERENT_RAM_END \
276 - BL_COHERENT_RAM_BASE, \
277 MT_DEVICE | MT_RW | MT_SECURE)
278#endif
Roberto Vargase3adc372018-05-23 09:27:06 +0100279#if USE_ROMLIB
280#define ARM_MAP_ROMLIB_CODE MAP_REGION_FLAT( \
281 ROMLIB_RO_BASE, \
282 ROMLIB_RO_LIMIT - ROMLIB_RO_BASE,\
283 MT_CODE | MT_SECURE)
284
285#define ARM_MAP_ROMLIB_DATA MAP_REGION_FLAT( \
286 ROMLIB_RW_BASE, \
287 ROMLIB_RW_END - ROMLIB_RW_BASE,\
288 MT_MEMORY | MT_RW | MT_SECURE)
289#endif
Daniel Boulby45a2c9e2018-07-06 16:54:44 +0100290
Dan Handley9df48042015-03-19 18:58:55 +0000291/*
Antonio Nino Diaz48bfb542018-10-11 13:02:34 +0100292 * Map mem_protect flash region with read and write permissions
293 */
294#define ARM_V2M_MAP_MEM_PROTECT MAP_REGION_FLAT(PLAT_ARM_MEM_PROT_ADDR, \
295 V2M_FLASH_BLOCK_SIZE, \
296 MT_DEVICE | MT_RW | MT_SECURE)
Manish V Badarkhe5e3ef6c2020-07-16 05:45:25 +0100297/*
298 * Map the region for device tree configuration with read and write permissions
299 */
300#define ARM_MAP_BL_CONFIG_REGION MAP_REGION_FLAT(ARM_BL_RAM_BASE, \
301 (ARM_FW_CONFIGS_LIMIT \
302 - ARM_BL_RAM_BASE), \
303 MT_MEMORY | MT_RW | MT_SECURE)
Antonio Nino Diaz48bfb542018-10-11 13:02:34 +0100304
305/*
Daniel Boulby4e97abd2018-07-16 14:09:15 +0100306 * The max number of regions like RO(code), coherent and data required by
Dan Handley9df48042015-03-19 18:58:55 +0000307 * different BL stages which need to be mapped in the MMU.
308 */
Manish V Badarkhe5e3ef6c2020-07-16 05:45:25 +0100309#define ARM_BL_REGIONS 6
Dan Handley9df48042015-03-19 18:58:55 +0000310
311#define MAX_MMAP_REGIONS (PLAT_ARM_MMAP_ENTRIES + \
312 ARM_BL_REGIONS)
313
314/* Memory mapped Generic timer interfaces */
Antonio Nino Diaz5f475792018-10-15 14:58:11 +0100315#define ARM_SYS_CNTCTL_BASE UL(0x2a430000)
316#define ARM_SYS_CNTREAD_BASE UL(0x2a800000)
317#define ARM_SYS_TIMCTL_BASE UL(0x2a810000)
318#define ARM_SYS_CNT_BASE_S UL(0x2a820000)
319#define ARM_SYS_CNT_BASE_NS UL(0x2a830000)
Dan Handley9df48042015-03-19 18:58:55 +0000320
321#define ARM_CONSOLE_BAUDRATE 115200
322
Juan Castillob6132f12015-10-06 14:01:35 +0100323/* Trusted Watchdog constants */
Antonio Nino Diaz5f475792018-10-15 14:58:11 +0100324#define ARM_SP805_TWDG_BASE UL(0x2a490000)
Juan Castillob6132f12015-10-06 14:01:35 +0100325#define ARM_SP805_TWDG_CLK_HZ 32768
326/* The TBBR document specifies a watchdog timeout of 256 seconds. SP805
327 * asserts reset after two consecutive countdowns (2 x 128 = 256 sec) */
328#define ARM_TWDG_TIMEOUT_SEC 128
329#define ARM_TWDG_LOAD_VAL (ARM_SP805_TWDG_CLK_HZ * \
330 ARM_TWDG_TIMEOUT_SEC)
331
Dan Handley9df48042015-03-19 18:58:55 +0000332/******************************************************************************
333 * Required platform porting definitions common to all ARM standard platforms
334 *****************************************************************************/
335
Roberto Vargasf8fda102017-08-08 11:27:20 +0100336/*
Soby Mathewfec4eb72015-07-01 16:16:20 +0100337 * This macro defines the deepest retention state possible. A higher state
338 * id will represent an invalid or a power down state.
339 */
340#define PLAT_MAX_RET_STATE ARM_LOCAL_STATE_RET
341
342/*
343 * This macro defines the deepest power down states possible. Any state ID
344 * higher than this is invalid.
345 */
346#define PLAT_MAX_OFF_STATE ARM_LOCAL_STATE_OFF
347
Dan Handley9df48042015-03-19 18:58:55 +0000348/*
349 * Some data must be aligned on the biggest cache line size in the platform.
350 * This is known only to the platform as it might have a combination of
351 * integrated and external caches.
352 */
Antonio Nino Diaz5f475792018-10-15 14:58:11 +0100353#define CACHE_WRITEBACK_GRANULE (U(1) << ARM_CACHE_WRITEBACK_SHIFT)
Dan Handley9df48042015-03-19 18:58:55 +0000354
Soby Mathew7c6df5b2018-01-15 14:43:42 +0000355/*
Manish V Badarkhe1da211a2020-05-31 10:17:59 +0100356 * To enable FW_CONFIG to be loaded by BL1, define the corresponding base
Soby Mathew7c6df5b2018-01-15 14:43:42 +0000357 * and limit. Leave enough space of BL2 meminfo.
358 */
Manish V Badarkhe1da211a2020-05-31 10:17:59 +0100359#define ARM_FW_CONFIG_BASE (ARM_BL_RAM_BASE + sizeof(meminfo_t))
Manish V Badarkhe0bafa822020-06-29 11:14:07 +0100360#define ARM_FW_CONFIG_LIMIT ((ARM_BL_RAM_BASE + PAGE_SIZE) \
361 + (PAGE_SIZE / 2U))
Sathees Balya90950092018-11-15 14:22:30 +0000362
363/*
364 * Boot parameters passed from BL2 to BL31/BL32 are stored here
365 */
Manish V Badarkhe0bafa822020-06-29 11:14:07 +0100366#define ARM_BL2_MEM_DESC_BASE (ARM_FW_CONFIG_LIMIT)
367#define ARM_BL2_MEM_DESC_LIMIT (ARM_BL2_MEM_DESC_BASE \
368 + (PAGE_SIZE / 2U))
Sathees Balya90950092018-11-15 14:22:30 +0000369
370/*
371 * Define limit of firmware configuration memory:
Manish V Badarkhe1da211a2020-05-31 10:17:59 +0100372 * ARM_FW_CONFIG + ARM_BL2_MEM_DESC memory
Sathees Balya90950092018-11-15 14:22:30 +0000373 */
Manish V Badarkhefbf1fd22020-06-09 11:31:17 +0100374#define ARM_FW_CONFIGS_LIMIT (ARM_BL_RAM_BASE + (PAGE_SIZE * 2))
Dan Handley9df48042015-03-19 18:58:55 +0000375
376/*******************************************************************************
377 * BL1 specific defines.
378 * BL1 RW data is relocated from ROM to RAM at runtime so we need 2 sets of
379 * addresses.
380 ******************************************************************************/
381#define BL1_RO_BASE PLAT_ARM_TRUSTED_ROM_BASE
382#define BL1_RO_LIMIT (PLAT_ARM_TRUSTED_ROM_BASE \
Roberto Vargase3adc372018-05-23 09:27:06 +0100383 + (PLAT_ARM_TRUSTED_ROM_SIZE - \
384 PLAT_ARM_MAX_ROMLIB_RO_SIZE))
Dan Handley9df48042015-03-19 18:58:55 +0000385/*
Vikram Kanigiri5d86f2e2016-01-21 14:08:15 +0000386 * Put BL1 RW at the top of the Trusted SRAM.
Dan Handley9df48042015-03-19 18:58:55 +0000387 */
Dan Handley9df48042015-03-19 18:58:55 +0000388#define BL1_RW_BASE (ARM_BL_RAM_BASE + \
389 ARM_BL_RAM_SIZE - \
Roberto Vargase3adc372018-05-23 09:27:06 +0100390 (PLAT_ARM_MAX_BL1_RW_SIZE +\
391 PLAT_ARM_MAX_ROMLIB_RW_SIZE))
392#define BL1_RW_LIMIT (ARM_BL_RAM_BASE + \
393 (ARM_BL_RAM_SIZE - PLAT_ARM_MAX_ROMLIB_RW_SIZE))
394
395#define ROMLIB_RO_BASE BL1_RO_LIMIT
396#define ROMLIB_RO_LIMIT (PLAT_ARM_TRUSTED_ROM_BASE + PLAT_ARM_TRUSTED_ROM_SIZE)
397
398#define ROMLIB_RW_BASE (BL1_RW_BASE + PLAT_ARM_MAX_BL1_RW_SIZE)
399#define ROMLIB_RW_END (ROMLIB_RW_BASE + PLAT_ARM_MAX_ROMLIB_RW_SIZE)
Dan Handley9df48042015-03-19 18:58:55 +0000400
401/*******************************************************************************
402 * BL2 specific defines.
403 ******************************************************************************/
Soby Mathewaf14b462018-06-01 16:53:38 +0100404#if BL2_AT_EL3
Dimitris Papastamos25836492018-06-11 11:07:58 +0100405/* Put BL2 towards the middle of the Trusted SRAM */
Soby Mathewaf14b462018-06-01 16:53:38 +0100406#define BL2_BASE (ARM_TRUSTED_SRAM_BASE + \
Dimitris Papastamos25836492018-06-11 11:07:58 +0100407 (PLAT_ARM_TRUSTED_SRAM_SIZE >> 1) + 0x2000)
Roberto Vargas52207802017-11-17 13:22:18 +0000408#define BL2_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)
409
David Wang0ba499f2016-03-07 11:02:57 +0800410#else
Dan Handley9df48042015-03-19 18:58:55 +0000411/*
Soby Mathewaf14b462018-06-01 16:53:38 +0100412 * Put BL2 just below BL1.
Dan Handley9df48042015-03-19 18:58:55 +0000413 */
Soby Mathewaf14b462018-06-01 16:53:38 +0100414#define BL2_BASE (BL1_RW_BASE - PLAT_ARM_MAX_BL2_SIZE)
415#define BL2_LIMIT BL1_RW_BASE
David Wang0ba499f2016-03-07 11:02:57 +0800416#endif
Dan Handley9df48042015-03-19 18:58:55 +0000417
418/*******************************************************************************
Juan Castillo7d199412015-12-14 09:35:25 +0000419 * BL31 specific defines.
Dan Handley9df48042015-03-19 18:58:55 +0000420 ******************************************************************************/
Madhukar Pappireddyd7419442020-01-27 15:38:26 -0600421#if ARM_BL31_IN_DRAM || SEPARATE_NOBITS_REGION
David Wang0ba499f2016-03-07 11:02:57 +0800422/*
423 * Put BL31 at the bottom of TZC secured DRAM
424 */
425#define BL31_BASE ARM_AP_TZC_DRAM1_BASE
426#define BL31_LIMIT (ARM_AP_TZC_DRAM1_BASE + \
427 PLAT_ARM_MAX_BL31_SIZE)
Madhukar Pappireddyd7419442020-01-27 15:38:26 -0600428/*
429 * For SEPARATE_NOBITS_REGION, BL31 PROGBITS are loaded in TZC secured DRAM.
430 * And BL31 NOBITS are loaded in Trusted SRAM such that BL2 is overwritten.
431 */
432#if SEPARATE_NOBITS_REGION
433#define BL31_NOBITS_BASE BL2_BASE
434#define BL31_NOBITS_LIMIT BL2_LIMIT
435#endif /* SEPARATE_NOBITS_REGION */
Qixiang Xua5f72812017-08-31 11:45:32 +0800436#elif (RESET_TO_BL31)
Manish Pandey2207e932019-11-06 13:17:46 +0000437/* Ensure Position Independent support (PIE) is enabled for this config.*/
438# if !ENABLE_PIE
439# error "BL31 must be a PIE if RESET_TO_BL31=1."
440#endif
Qixiang Xua5f72812017-08-31 11:45:32 +0800441/*
Soby Mathew68e69282018-12-12 14:13:52 +0000442 * Since this is PIE, we can define BL31_BASE to 0x0 since this macro is solely
Soby Mathewc5e17452019-01-07 14:07:58 +0000443 * used for building BL31 and not used for loading BL31.
Qixiang Xua5f72812017-08-31 11:45:32 +0800444 */
Soby Mathewc5e17452019-01-07 14:07:58 +0000445# define BL31_BASE 0x0
446# define BL31_LIMIT PLAT_ARM_MAX_BL31_SIZE
David Wang0ba499f2016-03-07 11:02:57 +0800447#else
Soby Mathewaf14b462018-06-01 16:53:38 +0100448/* Put BL31 below BL2 in the Trusted SRAM.*/
449#define BL31_BASE ((ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)\
450 - PLAT_ARM_MAX_BL31_SIZE)
451#define BL31_PROGBITS_LIMIT BL2_BASE
Dimitris Papastamos25836492018-06-11 11:07:58 +0100452/*
453 * For BL2_AT_EL3 make sure the BL31 can grow up until BL2_BASE. This is
454 * because in the BL2_AT_EL3 configuration, BL2 is always resident.
455 */
456#if BL2_AT_EL3
457#define BL31_LIMIT BL2_BASE
458#else
Dan Handley9df48042015-03-19 18:58:55 +0000459#define BL31_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)
David Wang0ba499f2016-03-07 11:02:57 +0800460#endif
Dimitris Papastamos25836492018-06-11 11:07:58 +0100461#endif
Dan Handley9df48042015-03-19 18:58:55 +0000462
Julius Werner8e0ef0f2019-07-09 14:02:43 -0700463#if !defined(__aarch64__) || JUNO_AARCH32_EL3_RUNTIME
Dan Handley9df48042015-03-19 18:58:55 +0000464/*******************************************************************************
Soby Mathewbf169232017-11-14 14:10:10 +0000465 * BL32 specific defines for EL3 runtime in AArch32 mode
466 ******************************************************************************/
467# if RESET_TO_SP_MIN && !JUNO_AARCH32_EL3_RUNTIME
Manish Pandey928da862021-06-10 15:22:48 +0100468/* Ensure Position Independent support (PIE) is enabled for this config.*/
469# if !ENABLE_PIE
470# error "BL32 must be a PIE if RESET_TO_SP_MIN=1."
471#endif
Soby Mathewaf14b462018-06-01 16:53:38 +0100472/*
Manish Pandey928da862021-06-10 15:22:48 +0100473 * Since this is PIE, we can define BL32_BASE to 0x0 since this macro is solely
474 * used for building BL32 and not used for loading BL32.
Soby Mathewaf14b462018-06-01 16:53:38 +0100475 */
Manish Pandey928da862021-06-10 15:22:48 +0100476# define BL32_BASE 0x0
477# define BL32_LIMIT PLAT_ARM_MAX_BL32_SIZE
Soby Mathewbf169232017-11-14 14:10:10 +0000478# else
Soby Mathewaf14b462018-06-01 16:53:38 +0100479/* Put BL32 below BL2 in the Trusted SRAM.*/
480# define BL32_BASE ((ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)\
481 - PLAT_ARM_MAX_BL32_SIZE)
482# define BL32_PROGBITS_LIMIT BL2_BASE
Soby Mathewbf169232017-11-14 14:10:10 +0000483# define BL32_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)
484# endif /* RESET_TO_SP_MIN && !JUNO_AARCH32_EL3_RUNTIME */
485
486#else
487/*******************************************************************************
488 * BL32 specific defines for EL3 runtime in AArch64 mode
Dan Handley9df48042015-03-19 18:58:55 +0000489 ******************************************************************************/
490/*
491 * On ARM standard platforms, the TSP can execute from Trusted SRAM,
492 * Trusted DRAM (if available) or the DRAM region secured by the TrustZone
493 * controller.
494 */
Paul Beesleydb4e25a2019-10-14 15:27:12 +0000495# if SPM_MM
Soby Mathewbf169232017-11-14 14:10:10 +0000496# define TSP_SEC_MEM_BASE (ARM_AP_TZC_DRAM1_BASE + ULL(0x200000))
497# define TSP_SEC_MEM_SIZE (ARM_AP_TZC_DRAM1_SIZE - ULL(0x200000))
498# define BL32_BASE (ARM_AP_TZC_DRAM1_BASE + ULL(0x200000))
499# define BL32_LIMIT (ARM_AP_TZC_DRAM1_BASE + \
Antonio Nino Diaz7289f922017-11-09 11:34:09 +0000500 ARM_AP_TZC_DRAM1_SIZE)
Achin Guptae97351d2019-10-11 15:15:19 +0100501# elif defined(SPD_spmd)
502# define TSP_SEC_MEM_BASE (ARM_AP_TZC_DRAM1_BASE + ULL(0x200000))
503# define TSP_SEC_MEM_SIZE (ARM_AP_TZC_DRAM1_SIZE - ULL(0x200000))
Arunachalam Ganapathy40618cf2020-07-27 13:51:30 +0100504# define BL32_BASE PLAT_ARM_SPMC_BASE
505# define BL32_LIMIT (PLAT_ARM_SPMC_BASE + \
506 PLAT_ARM_SPMC_SIZE)
Soby Mathewbf169232017-11-14 14:10:10 +0000507# elif ARM_BL31_IN_DRAM
508# define TSP_SEC_MEM_BASE (ARM_AP_TZC_DRAM1_BASE + \
David Wang0ba499f2016-03-07 11:02:57 +0800509 PLAT_ARM_MAX_BL31_SIZE)
Soby Mathewbf169232017-11-14 14:10:10 +0000510# define TSP_SEC_MEM_SIZE (ARM_AP_TZC_DRAM1_SIZE - \
David Wang0ba499f2016-03-07 11:02:57 +0800511 PLAT_ARM_MAX_BL31_SIZE)
Soby Mathewbf169232017-11-14 14:10:10 +0000512# define BL32_BASE (ARM_AP_TZC_DRAM1_BASE + \
David Wang0ba499f2016-03-07 11:02:57 +0800513 PLAT_ARM_MAX_BL31_SIZE)
Soby Mathewbf169232017-11-14 14:10:10 +0000514# define BL32_LIMIT (ARM_AP_TZC_DRAM1_BASE + \
David Wang0ba499f2016-03-07 11:02:57 +0800515 ARM_AP_TZC_DRAM1_SIZE)
Soby Mathewbf169232017-11-14 14:10:10 +0000516# elif ARM_TSP_RAM_LOCATION_ID == ARM_TRUSTED_SRAM_ID
517# define TSP_SEC_MEM_BASE ARM_BL_RAM_BASE
518# define TSP_SEC_MEM_SIZE ARM_BL_RAM_SIZE
Soby Mathewaf14b462018-06-01 16:53:38 +0100519# define TSP_PROGBITS_LIMIT BL31_BASE
Manish V Badarkhe1da211a2020-05-31 10:17:59 +0100520# define BL32_BASE ARM_FW_CONFIGS_LIMIT
Soby Mathewbf169232017-11-14 14:10:10 +0000521# define BL32_LIMIT BL31_BASE
522# elif ARM_TSP_RAM_LOCATION_ID == ARM_TRUSTED_DRAM_ID
523# define TSP_SEC_MEM_BASE PLAT_ARM_TRUSTED_DRAM_BASE
524# define TSP_SEC_MEM_SIZE PLAT_ARM_TRUSTED_DRAM_SIZE
525# define BL32_BASE PLAT_ARM_TRUSTED_DRAM_BASE
526# define BL32_LIMIT (PLAT_ARM_TRUSTED_DRAM_BASE \
Antonio Nino Diazab5d2b12018-10-30 16:12:32 +0000527 + (UL(1) << 21))
Soby Mathewbf169232017-11-14 14:10:10 +0000528# elif ARM_TSP_RAM_LOCATION_ID == ARM_DRAM_ID
529# define TSP_SEC_MEM_BASE ARM_AP_TZC_DRAM1_BASE
530# define TSP_SEC_MEM_SIZE ARM_AP_TZC_DRAM1_SIZE
531# define BL32_BASE ARM_AP_TZC_DRAM1_BASE
532# define BL32_LIMIT (ARM_AP_TZC_DRAM1_BASE + \
Dan Handley9df48042015-03-19 18:58:55 +0000533 ARM_AP_TZC_DRAM1_SIZE)
Soby Mathewbf169232017-11-14 14:10:10 +0000534# else
535# error "Unsupported ARM_TSP_RAM_LOCATION_ID value"
536# endif
Julius Werner8e0ef0f2019-07-09 14:02:43 -0700537#endif /* !__aarch64__ || JUNO_AARCH32_EL3_RUNTIME */
Dan Handley9df48042015-03-19 18:58:55 +0000538
Antonio Nino Diaz7289f922017-11-09 11:34:09 +0000539/*
540 * BL32 is mandatory in AArch32. In AArch64, undefine BL32_BASE if there is no
Achin Guptae97351d2019-10-11 15:15:19 +0100541 * SPD and no SPM-MM, as they are the only ones that can be used as BL32.
Antonio Nino Diaz7289f922017-11-09 11:34:09 +0000542 */
Julius Werner8e0ef0f2019-07-09 14:02:43 -0700543#if defined(__aarch64__) && !JUNO_AARCH32_EL3_RUNTIME
Paul Beesleydb4e25a2019-10-14 15:27:12 +0000544# if defined(SPD_none) && !SPM_MM
Antonio Nino Diaz7289f922017-11-09 11:34:09 +0000545# undef BL32_BASE
Achin Guptae97351d2019-10-11 15:15:19 +0100546# endif /* defined(SPD_none) && !SPM_MM */
Julius Werner8e0ef0f2019-07-09 14:02:43 -0700547#endif /* defined(__aarch64__) && !JUNO_AARCH32_EL3_RUNTIME */
Antonio Nino Diaze4fa3702016-04-05 11:38:49 +0100548
Yatharth Kochar736a3bf2015-10-11 14:14:55 +0100549/*******************************************************************************
550 * FWU Images: NS_BL1U, BL2U & NS_BL2U defines.
551 ******************************************************************************/
552#define BL2U_BASE BL2_BASE
Soby Mathewbf169232017-11-14 14:10:10 +0000553#define BL2U_LIMIT BL2_LIMIT
554
Yatharth Kochar736a3bf2015-10-11 14:14:55 +0100555#define NS_BL2U_BASE ARM_NS_DRAM1_BASE
Antonio Nino Diazab5d2b12018-10-30 16:12:32 +0000556#define NS_BL1U_BASE (PLAT_ARM_NVM_BASE + UL(0x03EB8000))
Yatharth Kochar736a3bf2015-10-11 14:14:55 +0100557
Dan Handley9df48042015-03-19 18:58:55 +0000558/*
559 * ID of the secure physical generic timer interrupt used by the TSP.
560 */
561#define TSP_IRQ_SEC_PHY_TIMER ARM_IRQ_SEC_PHY_TIMER
562
563
Vikram Kanigirid79214c2015-09-09 10:52:13 +0100564/*
565 * One cache line needed for bakery locks on ARM platforms
566 */
567#define PLAT_PERCPU_BAKERY_LOCK_SIZE (1 * CACHE_WRITEBACK_GRANULE)
568
Jeenu Viswambharanb1837452017-10-24 11:47:13 +0100569/* Priority levels for ARM platforms */
Jeenu Viswambharana5b5b8d2018-02-06 12:21:39 +0000570#define PLAT_RAS_PRI 0x10
Jeenu Viswambharanb1837452017-10-24 11:47:13 +0100571#define PLAT_SDEI_CRITICAL_PRI 0x60
572#define PLAT_SDEI_NORMAL_PRI 0x70
573
574/* ARM platforms use 3 upper bits of secure interrupt priority */
Sandeep Tripathy1c478392020-08-12 18:42:13 +0530575#define PLAT_PRI_BITS 3
Vikram Kanigirid79214c2015-09-09 10:52:13 +0100576
Jeenu Viswambharana5acc0a2017-09-22 08:32:10 +0100577/* SGI used for SDEI signalling */
578#define ARM_SDEI_SGI ARM_IRQ_SEC_SGI_0
579
Balint Dobszayd0dbd5e2019-12-18 15:28:00 +0100580#if SDEI_IN_FCONF
581/* ARM SDEI dynamic private event max count */
582#define ARM_SDEI_DP_EVENT_MAX_CNT 3
583
584/* ARM SDEI dynamic shared event max count */
585#define ARM_SDEI_DS_EVENT_MAX_CNT 3
586#else
Jeenu Viswambharana5acc0a2017-09-22 08:32:10 +0100587/* ARM SDEI dynamic private event numbers */
588#define ARM_SDEI_DP_EVENT_0 1000
589#define ARM_SDEI_DP_EVENT_1 1001
590#define ARM_SDEI_DP_EVENT_2 1002
591
592/* ARM SDEI dynamic shared event numbers */
593#define ARM_SDEI_DS_EVENT_0 2000
594#define ARM_SDEI_DS_EVENT_1 2001
595#define ARM_SDEI_DS_EVENT_2 2002
596
Jeenu Viswambharan6e284462017-12-08 10:38:24 +0000597#define ARM_SDEI_PRIVATE_EVENTS \
598 SDEI_DEFINE_EVENT_0(ARM_SDEI_SGI), \
599 SDEI_PRIVATE_EVENT(ARM_SDEI_DP_EVENT_0, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC), \
600 SDEI_PRIVATE_EVENT(ARM_SDEI_DP_EVENT_1, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC), \
601 SDEI_PRIVATE_EVENT(ARM_SDEI_DP_EVENT_2, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC)
602
603#define ARM_SDEI_SHARED_EVENTS \
604 SDEI_SHARED_EVENT(ARM_SDEI_DS_EVENT_0, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC), \
605 SDEI_SHARED_EVENT(ARM_SDEI_DS_EVENT_1, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC), \
606 SDEI_SHARED_EVENT(ARM_SDEI_DS_EVENT_2, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC)
Balint Dobszayd0dbd5e2019-12-18 15:28:00 +0100607#endif /* SDEI_IN_FCONF */
Jeenu Viswambharan6e284462017-12-08 10:38:24 +0000608
Antonio Nino Diaz6f3ccc52018-07-20 09:17:26 +0100609#endif /* ARM_DEF_H */