blob: 3a9514bda92e9b86c311c680268c783ae315c4c7 [file] [log] [blame]
Varun Wadekarb316e242015-05-19 16:48:04 +05301/*
2 * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#include <arch.h>
32#include <arch_helpers.h>
33#include <assert.h>
34#include <bl31.h>
35#include <bl_common.h>
36#include <console.h>
37#include <cortex_a57.h>
38#include <cortex_a53.h>
39#include <debug.h>
Varun Wadekarbaf903e2015-09-22 15:00:06 +053040#include <denver.h>
Varun Wadekar7a269e22015-06-10 14:04:32 +053041#include <errno.h>
Varun Wadekarb316e242015-05-19 16:48:04 +053042#include <memctrl.h>
43#include <mmio.h>
44#include <platform.h>
45#include <platform_def.h>
46#include <stddef.h>
47#include <tegra_private.h>
48
49/*******************************************************************************
50 * Declarations of linker defined symbols which will help us find the layout
51 * of trusted SRAM
52 ******************************************************************************/
53extern unsigned long __RO_START__;
54extern unsigned long __RO_END__;
55extern unsigned long __BL31_END__;
56
Varun Wadekarb316e242015-05-19 16:48:04 +053057extern uint64_t tegra_bl31_phys_base;
Varun Wadekard2014c62015-10-29 10:37:28 +053058extern uint64_t tegra_console_base;
Varun Wadekarb316e242015-05-19 16:48:04 +053059
60/*
61 * The next 3 constants identify the extents of the code, RO data region and the
62 * limit of the BL3-1 image. These addresses are used by the MMU setup code and
63 * therefore they must be page-aligned. It is the responsibility of the linker
64 * script to ensure that __RO_START__, __RO_END__ & __BL31_END__ linker symbols
65 * refer to page-aligned addresses.
66 */
67#define BL31_RO_BASE (unsigned long)(&__RO_START__)
68#define BL31_RO_LIMIT (unsigned long)(&__RO_END__)
69#define BL31_END (unsigned long)(&__BL31_END__)
70
Varun Wadekar52a15982015-06-05 12:57:27 +053071static entry_point_info_t bl33_image_ep_info, bl32_image_ep_info;
Varun Wadekarb316e242015-05-19 16:48:04 +053072static plat_params_from_bl2_t plat_bl31_params_from_bl2 = {
Varun Wadekarc8bfe2e2015-07-31 10:03:01 +053073 .tzdram_size = (uint64_t)TZDRAM_SIZE
Varun Wadekarb316e242015-05-19 16:48:04 +053074};
75
76/*******************************************************************************
77 * This variable holds the non-secure image entry address
78 ******************************************************************************/
79extern uint64_t ns_image_entrypoint;
80
81/*******************************************************************************
82 * Return a pointer to the 'entry_point_info' structure of the next image for
83 * security state specified. BL33 corresponds to the non-secure image type
84 * while BL32 corresponds to the secure image type.
85 ******************************************************************************/
86entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
87{
88 if (type == NON_SECURE)
89 return &bl33_image_ep_info;
90
Varun Wadekar52a15982015-06-05 12:57:27 +053091 if (type == SECURE)
92 return &bl32_image_ep_info;
93
Varun Wadekarb316e242015-05-19 16:48:04 +053094 return NULL;
95}
96
97/*******************************************************************************
98 * Return a pointer to the 'plat_params_from_bl2_t' structure. The BL2 image
99 * passes this platform specific information.
100 ******************************************************************************/
101plat_params_from_bl2_t *bl31_get_plat_params(void)
102{
103 return &plat_bl31_params_from_bl2;
104}
105
106/*******************************************************************************
107 * Perform any BL31 specific platform actions. Populate the BL33 and BL32 image
108 * info.
109 ******************************************************************************/
110void bl31_early_platform_setup(bl31_params_t *from_bl2,
111 void *plat_params_from_bl2)
112{
113 plat_params_from_bl2_t *plat_params =
114 (plat_params_from_bl2_t *)plat_params_from_bl2;
Varun Wadekarbaf903e2015-09-22 15:00:06 +0530115#if DEBUG
116 int impl = (read_midr() >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK;
117#endif
Varun Wadekarbaf903e2015-09-22 15:00:06 +0530118
Varun Wadekarb316e242015-05-19 16:48:04 +0530119 /*
Varun Wadekar52a15982015-06-05 12:57:27 +0530120 * Copy BL3-3, BL3-2 entry point information.
Varun Wadekarb316e242015-05-19 16:48:04 +0530121 * They are stored in Secure RAM, in BL2's address space.
122 */
Varun Wadekar6bb62462015-10-06 12:49:31 +0530123 assert(from_bl2->bl33_ep_info);
124 bl33_image_ep_info = *from_bl2->bl33_ep_info;
Varun Wadekarbaf903e2015-09-22 15:00:06 +0530125
126 if (from_bl2->bl32_ep_info)
127 bl32_image_ep_info = *from_bl2->bl32_ep_info;
Varun Wadekarb316e242015-05-19 16:48:04 +0530128
129 /*
Varun Wadekar6bb62462015-10-06 12:49:31 +0530130 * Parse platform specific parameters - TZDRAM aperture base and size
Varun Wadekarb316e242015-05-19 16:48:04 +0530131 */
Varun Wadekar6bb62462015-10-06 12:49:31 +0530132 assert(plat_params);
133 plat_bl31_params_from_bl2.tzdram_base = plat_params->tzdram_base;
134 plat_bl31_params_from_bl2.tzdram_size = plat_params->tzdram_size;
Varun Wadekard2014c62015-10-29 10:37:28 +0530135 plat_bl31_params_from_bl2.uart_id = plat_params->uart_id;
136
137 /*
138 * Get the base address of the UART controller to be used for the
139 * console
140 */
141 assert(plat_params->uart_id);
142 tegra_console_base = plat_get_console_from_id(plat_params->uart_id);
143
144 /*
145 * Configure the UART port to be used as the console
146 */
147 assert(tegra_console_base);
148 console_init(tegra_console_base, TEGRA_BOOT_UART_CLK_IN_HZ,
149 TEGRA_CONSOLE_BAUDRATE);
150
151 /* Initialise crash console */
152 plat_crash_console_init();
153
154 INFO("BL3-1: Boot CPU: %s Processor [%lx]\n", (impl == DENVER_IMPL) ?
155 "Denver" : "ARM", read_mpidr());
Varun Wadekarb316e242015-05-19 16:48:04 +0530156}
157
158/*******************************************************************************
159 * Initialize the gic, configure the SCR.
160 ******************************************************************************/
161void bl31_platform_setup(void)
162{
163 uint32_t tmp_reg;
164
165 /*
Varun Wadekarbc74fec2015-07-16 15:47:03 +0530166 * Initialize delay timer
167 */
168 tegra_delay_timer_init();
169
170 /*
Varun Wadekarb316e242015-05-19 16:48:04 +0530171 * Setup secondary CPU POR infrastructure.
172 */
173 plat_secondary_setup();
174
175 /*
176 * Initial Memory Controller configuration.
177 */
178 tegra_memctrl_setup();
179
180 /*
181 * Do initial security configuration to allow DRAM/device access.
182 */
Varun Wadekar6bb62462015-10-06 12:49:31 +0530183 tegra_memctrl_tzdram_setup(plat_bl31_params_from_bl2.tzdram_base,
Varun Wadekarb316e242015-05-19 16:48:04 +0530184 plat_bl31_params_from_bl2.tzdram_size);
185
186 /* Set the next EL to be AArch64 */
187 tmp_reg = SCR_RES1_BITS | SCR_RW_BIT;
188 write_scr(tmp_reg);
189
190 /* Initialize the gic cpu and distributor interfaces */
191 tegra_gic_setup();
Varun Wadekarbaf903e2015-09-22 15:00:06 +0530192
193 INFO("BL3-1: Tegra platform setup complete\n");
Varun Wadekarb316e242015-05-19 16:48:04 +0530194}
195
196/*******************************************************************************
197 * Perform the very early platform specific architectural setup here. At the
198 * moment this only intializes the mmu in a quick and dirty way.
199 ******************************************************************************/
200void bl31_plat_arch_setup(void)
201{
202 unsigned long bl31_base_pa = tegra_bl31_phys_base;
203 unsigned long total_base = bl31_base_pa;
Varun Wadekare1eaf8e2015-08-11 14:20:14 +0530204 unsigned long total_size = BL32_BASE - BL31_RO_BASE;
Varun Wadekarb316e242015-05-19 16:48:04 +0530205 unsigned long ro_start = bl31_base_pa;
206 unsigned long ro_size = BL31_RO_LIMIT - BL31_RO_BASE;
Varun Wadekarb316e242015-05-19 16:48:04 +0530207 const mmap_region_t *plat_mmio_map = NULL;
Varun Wadekarb316e242015-05-19 16:48:04 +0530208#if USE_COHERENT_MEM
Varun Wadekar207cc732015-07-08 12:57:50 +0530209 unsigned long coh_start, coh_size;
Varun Wadekarb316e242015-05-19 16:48:04 +0530210#endif
211
212 /* add memory regions */
213 mmap_add_region(total_base, total_base,
214 total_size,
215 MT_MEMORY | MT_RW | MT_SECURE);
216 mmap_add_region(ro_start, ro_start,
217 ro_size,
218 MT_MEMORY | MT_RO | MT_SECURE);
Varun Wadekar207cc732015-07-08 12:57:50 +0530219
Varun Wadekarb316e242015-05-19 16:48:04 +0530220#if USE_COHERENT_MEM
Masahiro Yamada0fac5af2016-12-28 16:11:41 +0900221 coh_start = total_base + (BL_COHERENT_RAM_BASE - BL31_RO_BASE);
222 coh_size = BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE;
Varun Wadekar207cc732015-07-08 12:57:50 +0530223
Varun Wadekarb316e242015-05-19 16:48:04 +0530224 mmap_add_region(coh_start, coh_start,
225 coh_size,
226 MT_DEVICE | MT_RW | MT_SECURE);
227#endif
228
229 /* add MMIO space */
230 plat_mmio_map = plat_get_mmio_map();
231 if (plat_mmio_map)
232 mmap_add(plat_mmio_map);
233 else
234 WARN("MMIO map not available\n");
235
236 /* set up translation tables */
237 init_xlat_tables();
238
239 /* enable the MMU */
240 enable_mmu_el3(0);
Varun Wadekarbaf903e2015-09-22 15:00:06 +0530241
242 INFO("BL3-1: Tegra: MMU enabled\n");
Varun Wadekarb316e242015-05-19 16:48:04 +0530243}
Varun Wadekar7a269e22015-06-10 14:04:32 +0530244
245/*******************************************************************************
246 * Check if the given NS DRAM range is valid
247 ******************************************************************************/
248int bl31_check_ns_address(uint64_t base, uint64_t size_in_bytes)
249{
250 uint64_t end = base + size_in_bytes - 1;
251
252 /*
253 * Check if the NS DRAM address is valid
254 */
255 if ((base < TEGRA_DRAM_BASE) || (end > TEGRA_DRAM_END) ||
256 (base >= end)) {
257 ERROR("NS address is out-of-bounds!\n");
258 return -EFAULT;
259 }
260
261 /*
262 * TZDRAM aperture contains the BL31 and BL32 images, so we need
263 * to check if the NS DRAM range overlaps the TZDRAM aperture.
264 */
265 if ((base < TZDRAM_END) && (end > tegra_bl31_phys_base)) {
266 ERROR("NS address overlaps TZDRAM!\n");
267 return -ENOTSUP;
268 }
269
270 /* valid NS address */
271 return 0;
272}