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Dan Handley9df48042015-03-19 18:58:55 +00001/*
Max Shvetsov06dba292019-12-06 11:50:12 +00002 * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
Dan Handley9df48042015-03-19 18:58:55 +00003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Dan Handley9df48042015-03-19 18:58:55 +00005 */
Antonio Nino Diaz05fdb832018-10-25 16:53:04 +01006#ifndef PLAT_ARM_H
7#define PLAT_ARM_H
Dan Handley9df48042015-03-19 18:58:55 +00008
Louis Mayencourt70d7c092020-01-29 11:42:31 +00009#include <stdbool.h>
Dan Handley9df48042015-03-19 18:58:55 +000010#include <stdint.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000011
12#include <drivers/arm/tzc_common.h>
13#include <lib/bakery_lock.h>
14#include <lib/cassert.h>
15#include <lib/el3_runtime/cpu_data.h>
16#include <lib/spinlock.h>
17#include <lib/utils_def.h>
18#include <lib/xlat_tables/xlat_tables_compat.h>
Dan Handley9df48042015-03-19 18:58:55 +000019
Sandrine Bailleuxf402a522016-09-15 10:09:53 +010020/*******************************************************************************
21 * Forward declarations
22 ******************************************************************************/
Sandrine Bailleuxf402a522016-09-15 10:09:53 +010023struct meminfo;
Yatharth Kocharf9a0f162016-09-13 17:07:57 +010024struct image_info;
Soby Mathew96a1c6b2018-01-15 14:45:33 +000025struct bl_params;
Sandrine Bailleuxf402a522016-09-15 10:09:53 +010026
Summer Qin5ce394c2018-03-12 11:28:26 +080027typedef struct arm_tzc_regions_info {
28 unsigned long long base;
29 unsigned long long end;
Antonio Nino Diaz5f475792018-10-15 14:58:11 +010030 unsigned int sec_attr;
Summer Qin5ce394c2018-03-12 11:28:26 +080031 unsigned int nsaid_permissions;
32} arm_tzc_regions_info_t;
33
34/*******************************************************************************
35 * Default mapping definition of the TrustZone Controller for ARM standard
36 * platforms.
37 * Configure:
38 * - Region 0 with no access;
39 * - Region 1 with secure access only;
40 * - the remaining DRAM regions access from the given Non-Secure masters.
41 ******************************************************************************/
Paul Beesleyfe975b42019-09-16 11:29:03 +000042#if SPM_MM
Summer Qin5ce394c2018-03-12 11:28:26 +080043#define ARM_TZC_REGIONS_DEF \
44 {ARM_AP_TZC_DRAM1_BASE, ARM_EL3_TZC_DRAM1_END, \
45 TZC_REGION_S_RDWR, 0}, \
46 {ARM_NS_DRAM1_BASE, ARM_NS_DRAM1_END, ARM_TZC_NS_DRAM_S_ACCESS, \
47 PLAT_ARM_TZC_NS_DEV_ACCESS}, \
48 {ARM_DRAM2_BASE, ARM_DRAM2_END, ARM_TZC_NS_DRAM_S_ACCESS, \
49 PLAT_ARM_TZC_NS_DEV_ACCESS}, \
Ard Biesheuvel8b034fc2018-12-29 19:43:21 +010050 {PLAT_SP_IMAGE_NS_BUF_BASE, (PLAT_SP_IMAGE_NS_BUF_BASE + \
51 PLAT_SP_IMAGE_NS_BUF_SIZE) - 1, TZC_REGION_S_NONE, \
Summer Qin5ce394c2018-03-12 11:28:26 +080052 PLAT_ARM_TZC_NS_DEV_ACCESS}
53
54#else
55#define ARM_TZC_REGIONS_DEF \
56 {ARM_AP_TZC_DRAM1_BASE, ARM_EL3_TZC_DRAM1_END, \
57 TZC_REGION_S_RDWR, 0}, \
58 {ARM_NS_DRAM1_BASE, ARM_NS_DRAM1_END, ARM_TZC_NS_DRAM_S_ACCESS, \
59 PLAT_ARM_TZC_NS_DEV_ACCESS}, \
60 {ARM_DRAM2_BASE, ARM_DRAM2_END, ARM_TZC_NS_DRAM_S_ACCESS, \
61 PLAT_ARM_TZC_NS_DEV_ACCESS}
62#endif
63
Chris Kay2b54c0c2018-05-09 15:46:07 +010064#define ARM_CASSERT_MMAP \
65 CASSERT((ARRAY_SIZE(plat_arm_mmap) - 1) <= PLAT_ARM_MMAP_ENTRIES, \
66 assert_plat_arm_mmap_mismatch); \
67 CASSERT((PLAT_ARM_MMAP_ENTRIES + ARM_BL_REGIONS) \
68 <= MAX_MMAP_REGIONS, \
Dan Handley9df48042015-03-19 18:58:55 +000069 assert_max_mmap_regions);
70
Roberto Vargase3adc372018-05-23 09:27:06 +010071void arm_setup_romlib(void);
72
Julius Werner8e0ef0f2019-07-09 14:02:43 -070073#if defined(IMAGE_BL31) || (!defined(__aarch64__) && defined(IMAGE_BL32))
Dan Handley9df48042015-03-19 18:58:55 +000074/*
75 * Use this macro to instantiate lock before it is used in below
76 * arm_lock_xxx() macros
77 */
Sandrine Bailleuxceb258e2018-07-11 13:59:18 +020078#define ARM_INSTANTIATE_LOCK static DEFINE_BAKERY_LOCK(arm_lock)
Soby Mathewea26bad2016-11-14 12:25:45 +000079#define ARM_LOCK_GET_INSTANCE (&arm_lock)
Roberto Vargas00996942017-11-13 13:41:58 +000080
81#if !HW_ASSISTED_COHERENCY
82#define ARM_SCMI_INSTANTIATE_LOCK DEFINE_BAKERY_LOCK(arm_scmi_lock)
83#else
84#define ARM_SCMI_INSTANTIATE_LOCK spinlock_t arm_scmi_lock
85#endif
86#define ARM_SCMI_LOCK_GET_INSTANCE (&arm_scmi_lock)
87
Dan Handley9df48042015-03-19 18:58:55 +000088/*
89 * These are wrapper macros to the Coherent Memory Bakery Lock API.
90 */
91#define arm_lock_init() bakery_lock_init(&arm_lock)
92#define arm_lock_get() bakery_lock_get(&arm_lock)
93#define arm_lock_release() bakery_lock_release(&arm_lock)
94
95#else
96
Dan Handley9df48042015-03-19 18:58:55 +000097/*
Yatharth Kochar2694cba2016-11-14 12:00:41 +000098 * Empty macros for all other BL stages other than BL31 and BL32
Dan Handley9df48042015-03-19 18:58:55 +000099 */
Jeenu Viswambharan749d25b2017-08-23 14:12:59 +0100100#define ARM_INSTANTIATE_LOCK static int arm_lock __unused
Soby Mathewea26bad2016-11-14 12:25:45 +0000101#define ARM_LOCK_GET_INSTANCE 0
Dan Handley9df48042015-03-19 18:58:55 +0000102#define arm_lock_init()
103#define arm_lock_get()
104#define arm_lock_release()
105
Julius Werner8e0ef0f2019-07-09 14:02:43 -0700106#endif /* defined(IMAGE_BL31) || (!defined(__aarch64__) && defined(IMAGE_BL32)) */
Dan Handley9df48042015-03-19 18:58:55 +0000107
Soby Mathew7799cf72015-04-16 14:49:09 +0100108#if ARM_RECOM_STATE_ID_ENC
109/*
110 * Macros used to parse state information from State-ID if it is using the
111 * recommended encoding for State-ID.
112 */
113#define ARM_LOCAL_PSTATE_WIDTH 4
114#define ARM_LOCAL_PSTATE_MASK ((1 << ARM_LOCAL_PSTATE_WIDTH) - 1)
115
116/* Macros to construct the composite power state */
117
118/* Make composite power state parameter till power level 0 */
119#if PSCI_EXTENDED_STATE_ID
120
121#define arm_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type) \
122 (((lvl0_state) << PSTATE_ID_SHIFT) | ((type) << PSTATE_TYPE_SHIFT))
123#else
124#define arm_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type) \
125 (((lvl0_state) << PSTATE_ID_SHIFT) | \
126 ((pwr_lvl) << PSTATE_PWR_LVL_SHIFT) | \
127 ((type) << PSTATE_TYPE_SHIFT))
128#endif /* __PSCI_EXTENDED_STATE_ID__ */
129
130/* Make composite power state parameter till power level 1 */
131#define arm_make_pwrstate_lvl1(lvl1_state, lvl0_state, pwr_lvl, type) \
132 (((lvl1_state) << ARM_LOCAL_PSTATE_WIDTH) | \
133 arm_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type))
134
Soby Mathewa869de12015-05-08 10:18:59 +0100135/* Make composite power state parameter till power level 2 */
136#define arm_make_pwrstate_lvl2(lvl2_state, lvl1_state, lvl0_state, pwr_lvl, type) \
137 (((lvl2_state) << (ARM_LOCAL_PSTATE_WIDTH * 2)) | \
138 arm_make_pwrstate_lvl1(lvl1_state, lvl0_state, pwr_lvl, type))
139
Soby Mathew7799cf72015-04-16 14:49:09 +0100140#endif /* __ARM_RECOM_STATE_ID_ENC__ */
141
Jeenu Viswambharanbc1a9292017-02-16 14:55:15 +0000142/* ARM State switch error codes */
143#define STATE_SW_E_PARAM (-2)
144#define STATE_SW_E_DENIED (-3)
Dan Handley9df48042015-03-19 18:58:55 +0000145
Max Shvetsov06dba292019-12-06 11:50:12 +0000146/* plat_get_rotpk_info() flags */
147#define ARM_ROTPK_REGS_ID 1
148#define ARM_ROTPK_DEVEL_RSA_ID 2
149#define ARM_ROTPK_DEVEL_ECDSA_ID 3
150
Manish V Badarkhef809c6e2020-02-22 08:43:00 +0000151
Dan Handley9df48042015-03-19 18:58:55 +0000152/* IO storage utility functions */
Louis Mayencourt7d24ce12020-01-29 14:43:06 +0000153int arm_io_setup(void);
Dan Handley9df48042015-03-19 18:58:55 +0000154
155/* Security utility functions */
Suyash Pathakb71a9e62020-02-04 13:55:20 +0530156void arm_tzc400_setup(uintptr_t tzc_base,
157 const arm_tzc_regions_info_t *tzc_regions);
Vikram Kanigiri510d87b2016-01-29 12:32:58 +0000158struct tzc_dmc500_driver_data;
Summer Qin5ce394c2018-03-12 11:28:26 +0800159void arm_tzc_dmc500_setup(struct tzc_dmc500_driver_data *plat_driver_data,
160 const arm_tzc_regions_info_t *tzc_regions);
Dan Handley9df48042015-03-19 18:58:55 +0000161
Antonio Nino Diaz23ede6a2018-06-19 09:29:36 +0100162/* Console utility functions */
163void arm_console_boot_init(void);
164void arm_console_boot_end(void);
165void arm_console_runtime_init(void);
166void arm_console_runtime_end(void);
167
Soby Mathew61e8d0b2015-10-12 17:32:29 +0100168/* Systimer utility function */
169void arm_configure_sys_timer(void);
170
Dan Handley9df48042015-03-19 18:58:55 +0000171/* PM utility functions */
Soby Mathewfec4eb72015-07-01 16:16:20 +0100172int arm_validate_power_state(unsigned int power_state,
173 psci_power_state_t *req_state);
Jeenu Viswambharan59424d82017-09-19 09:27:18 +0100174int arm_validate_psci_entrypoint(uintptr_t entrypoint);
Soby Mathew0d9e8522015-07-15 13:36:24 +0100175int arm_validate_ns_entrypoint(uintptr_t entrypoint);
Soby Mathew9ca28062017-10-11 16:08:58 +0100176void arm_system_pwr_domain_save(void);
Soby Mathew61e8d0b2015-10-12 17:32:29 +0100177void arm_system_pwr_domain_resume(void);
Roberto Vargas1a6eed32018-02-12 12:36:17 +0000178int arm_psci_read_mem_protect(int *enabled);
Roberto Vargasa1c16b62017-08-03 09:16:43 +0100179int arm_nor_psci_write_mem_protect(int val);
Roberto Vargas550eb082018-01-05 16:00:05 +0000180void arm_nor_psci_do_static_mem_protect(void);
181void arm_nor_psci_do_dyn_mem_protect(void);
Roberto Vargasa1c16b62017-08-03 09:16:43 +0100182int arm_psci_mem_protect_chk(uintptr_t base, u_register_t length);
Soby Mathewfec4eb72015-07-01 16:16:20 +0100183
184/* Topology utility function */
185int arm_check_mpidr(u_register_t mpidr);
Dan Handley9df48042015-03-19 18:58:55 +0000186
187/* BL1 utility functions */
188void arm_bl1_early_platform_setup(void);
189void arm_bl1_platform_setup(void);
190void arm_bl1_plat_arch_setup(void);
191
192/* BL2 utility functions */
Soby Mathew96a1c6b2018-01-15 14:45:33 +0000193void arm_bl2_early_platform_setup(uintptr_t tb_fw_config, struct meminfo *mem_layout);
Dan Handley9df48042015-03-19 18:58:55 +0000194void arm_bl2_platform_setup(void);
195void arm_bl2_plat_arch_setup(void);
196uint32_t arm_get_spsr_for_bl32_entry(void);
197uint32_t arm_get_spsr_for_bl33_entry(void);
Ambroise Vincentb237bca2019-02-13 15:58:00 +0000198int arm_bl2_plat_handle_post_image_load(unsigned int image_id);
Yatharth Kocharede39cb2016-11-14 12:01:04 +0000199int arm_bl2_handle_post_image_load(unsigned int image_id);
Sathees Balya90950092018-11-15 14:22:30 +0000200struct bl_params *arm_get_next_bl_params(void);
Dan Handley9df48042015-03-19 18:58:55 +0000201
Roberto Vargas52207802017-11-17 13:22:18 +0000202/* BL2 at EL3 functions */
203void arm_bl2_el3_early_platform_setup(void);
204void arm_bl2_el3_plat_arch_setup(void);
205
Yatharth Kochar3a11eda2015-10-14 15:28:11 +0100206/* BL2U utility functions */
207void arm_bl2u_early_platform_setup(struct meminfo *mem_layout,
208 void *plat_info);
209void arm_bl2u_platform_setup(void);
210void arm_bl2u_plat_arch_setup(void);
211
Juan Castillo7d199412015-12-14 09:35:25 +0000212/* BL31 utility functions */
Soby Mathew7d5a2e72018-01-10 15:59:31 +0000213void arm_bl31_early_platform_setup(void *from_bl2, uintptr_t soc_fw_config,
214 uintptr_t hw_config, void *plat_params_from_bl2);
Dan Handley9df48042015-03-19 18:58:55 +0000215void arm_bl31_platform_setup(void);
Soby Mathew2fd66be2015-12-09 11:38:43 +0000216void arm_bl31_plat_runtime_setup(void);
Dan Handley9df48042015-03-19 18:58:55 +0000217void arm_bl31_plat_arch_setup(void);
218
219/* TSP utility functions */
220void arm_tsp_early_platform_setup(void);
221
Soby Mathew7b754182016-07-11 14:15:27 +0100222/* SP_MIN utility functions */
Soby Mathew7d5a2e72018-01-10 15:59:31 +0000223void arm_sp_min_early_platform_setup(void *from_bl2, uintptr_t tos_fw_config,
224 uintptr_t hw_config, void *plat_params_from_bl2);
Dimitris Papastamos52323b02017-06-07 13:45:41 +0100225void arm_sp_min_plat_runtime_setup(void);
Madhukar Pappireddyae9677b2020-01-27 13:37:51 -0600226void arm_sp_min_plat_arch_setup(void);
Soby Mathew7b754182016-07-11 14:15:27 +0100227
Yatharth Kochar736a3bf2015-10-11 14:14:55 +0100228/* FIP TOC validity check */
Louis Mayencourt70d7c092020-01-29 11:42:31 +0000229bool arm_io_is_toc_valid(void);
Dan Handley9df48042015-03-19 18:58:55 +0000230
Soby Mathew7c6df5b2018-01-15 14:43:42 +0000231/* Utility functions for Dynamic Config */
Soby Mathew96a1c6b2018-01-15 14:45:33 +0000232void arm_bl2_dyn_cfg_init(void);
John Tsichritzisc34341a2018-07-30 13:41:52 +0100233void arm_bl1_set_mbedtls_heap(void);
234int arm_get_mbedtls_heap(void **heap_addr, size_t *heap_size);
Soby Mathew7c6df5b2018-01-15 14:43:42 +0000235
Alexei Fedorov25d7c882020-03-20 18:38:55 +0000236#if MEASURED_BOOT
237/* Measured boot related functions */
238void arm_bl1_set_bl2_hash(image_desc_t *image_desc);
239#endif
240
Dan Handley9df48042015-03-19 18:58:55 +0000241/*
Daniel Boulbyb1b058d2018-09-18 11:52:49 +0100242 * Free the memory storing initialization code only used during an images boot
243 * time so it can be reclaimed for runtime data
244 */
245void arm_free_init_memory(void);
246
247/*
Petre-Ionut Tudore5a6fef2019-11-07 15:18:03 +0000248 * Make the higher level translation tables read-only
249 */
250void arm_xlat_make_tables_readonly(void);
251
252/*
Dan Handley9df48042015-03-19 18:58:55 +0000253 * Mandatory functions required in ARM standard platforms
254 */
Soby Mathew47e43f22016-02-01 14:04:34 +0000255unsigned int plat_arm_get_cluster_core_count(u_register_t mpidr);
Achin Gupta1fa7eb62015-11-03 14:18:34 +0000256void plat_arm_gic_driver_init(void);
Dan Handley9df48042015-03-19 18:58:55 +0000257void plat_arm_gic_init(void);
Achin Gupta1fa7eb62015-11-03 14:18:34 +0000258void plat_arm_gic_cpuif_enable(void);
259void plat_arm_gic_cpuif_disable(void);
Jeenu Viswambharan78132c92016-12-09 11:12:34 +0000260void plat_arm_gic_redistif_on(void);
261void plat_arm_gic_redistif_off(void);
Achin Gupta1fa7eb62015-11-03 14:18:34 +0000262void plat_arm_gic_pcpu_init(void);
Soby Mathew9ca28062017-10-11 16:08:58 +0100263void plat_arm_gic_save(void);
264void plat_arm_gic_resume(void);
Dan Handley9df48042015-03-19 18:58:55 +0000265void plat_arm_security_setup(void);
266void plat_arm_pwrc_setup(void);
Vikram Kanigirifbb13012016-02-15 11:54:14 +0000267void plat_arm_interconnect_init(void);
268void plat_arm_interconnect_enter_coherency(void);
269void plat_arm_interconnect_exit_coherency(void);
Dimitris Papastamosd7a36512018-06-18 13:01:06 +0100270void plat_arm_program_trusted_mailbox(uintptr_t address);
Louis Mayencourt70d7c092020-01-29 11:42:31 +0000271bool plat_arm_bl1_fwu_needed(void);
Ambroise Vincentfa42c9e2019-07-04 14:58:45 +0100272__dead2 void plat_arm_error_handler(int err);
Dan Handley9df48042015-03-19 18:58:55 +0000273
Vijayenthiran Subramaniam2dfa7642019-10-11 14:01:25 +0530274/*
Max Shvetsov06dba292019-12-06 11:50:12 +0000275 * Optional functions in ARM standard platforms
Vijayenthiran Subramaniam2dfa7642019-10-11 14:01:25 +0530276 */
277void plat_arm_override_gicr_frames(const uintptr_t *plat_gicr_frames);
Sandrine Bailleux7b7a41c2020-02-06 14:34:44 +0100278int arm_get_rotpk_info(void *cookie, void **key_ptr, unsigned int *key_len,
Max Shvetsov06dba292019-12-06 11:50:12 +0000279 unsigned int *flags);
280int arm_get_rotpk_info_regs(void **key_ptr, unsigned int *key_len,
281 unsigned int *flags);
282int arm_get_rotpk_info_cc(void **key_ptr, unsigned int *key_len,
283 unsigned int *flags);
284int arm_get_rotpk_info_dev(void **key_ptr, unsigned int *key_len,
285 unsigned int *flags);
Vijayenthiran Subramaniam2dfa7642019-10-11 14:01:25 +0530286
Summer Qin93c812f2017-02-28 16:46:17 +0000287#if ARM_PLAT_MT
288unsigned int plat_arm_get_cpu_pe_count(u_register_t mpidr);
289#endif
290
Yatharth Kocharf9a0f162016-09-13 17:07:57 +0100291/*
292 * This function is called after loading SCP_BL2 image and it is used to perform
293 * any platform-specific actions required to handle the SCP firmware.
294 */
295int plat_arm_bl2_handle_scp_bl2(struct image_info *scp_bl2_image_info);
Yatharth Kocharf9a0f162016-09-13 17:07:57 +0100296
Dan Handley9df48042015-03-19 18:58:55 +0000297/*
298 * Optional functions required in ARM standard platforms
299 */
300void plat_arm_io_setup(void);
301int plat_arm_get_alt_image_source(
Juan Castillo3a66aca2015-04-13 17:36:19 +0100302 unsigned int image_id,
303 uintptr_t *dev_handle,
304 uintptr_t *image_spec);
Soby Mathewfec4eb72015-07-01 16:16:20 +0100305unsigned int plat_arm_calc_core_pos(u_register_t mpidr);
Vikram Kanigiri07035432015-11-12 18:52:34 +0000306const mmap_region_t *plat_arm_get_mmap(void);
Dan Handley9df48042015-03-19 18:58:55 +0000307
Soby Mathew0b4c5a32016-10-21 17:51:22 +0100308/* Allow platform to override psci_pm_ops during runtime */
309const plat_psci_ops_t *plat_arm_psci_override_pm_ops(plat_psci_ops_t *ops);
310
Jeenu Viswambharanbc1a9292017-02-16 14:55:15 +0000311/* Execution state switch in ARM platforms */
312int arm_execution_state_switch(unsigned int smc_fid,
313 uint32_t pc_hi,
314 uint32_t pc_lo,
315 uint32_t cookie_hi,
316 uint32_t cookie_lo,
317 void *handle);
318
Soby Mathew6d07e672018-03-01 10:53:33 +0000319/* Optional functions for SP_MIN */
320void plat_arm_sp_min_early_platform_setup(u_register_t arg0, u_register_t arg1,
321 u_register_t arg2, u_register_t arg3);
322
Roberto Vargas2ca18d92018-02-12 12:36:17 +0000323/* global variables */
324extern plat_psci_ops_t plat_arm_psci_pm_ops;
325extern const mmap_region_t plat_arm_mmap[];
Jeenu Viswambharan4542cfe2018-07-19 08:03:46 +0100326extern const unsigned int arm_pm_idle_states[];
Roberto Vargas2ca18d92018-02-12 12:36:17 +0000327
Aditya Angadi20b48412019-04-16 11:29:14 +0530328/* secure watchdog */
329void plat_arm_secure_wdt_start(void);
330void plat_arm_secure_wdt_stop(void);
331
Manish V Badarkhef809c6e2020-02-22 08:43:00 +0000332/* Get SOC-ID of ARM platform */
333uint32_t plat_arm_get_soc_id(void);
334
Antonio Nino Diaz05fdb832018-10-25 16:53:04 +0100335#endif /* PLAT_ARM_H */