blob: 0bf18e437dc873f3b5ebecfd09a8b1afa8f61f0b [file] [log] [blame]
Usama Arifbec5afd2020-04-17 16:13:39 +01001# Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
2#
3# SPDX-License-Identifier: BSD-3-Clause
4#
5
6CSS_LOAD_SCP_IMAGES := 1
7
8CSS_USE_SCMI_SDS_DRIVER := 1
9
10RAS_EXTENSION := 0
11
12SDEI_SUPPORT := 0
13
14EL3_EXCEPTION_HANDLING := 0
15
16HANDLE_EA_EL3_FIRST := 0
17
18# System coherency is managed in hardware
19HW_ASSISTED_COHERENCY := 1
20
21# When building for systems with hardware-assisted coherency, there's no need to
22# use USE_COHERENT_MEM. Require that USE_COHERENT_MEM must be set to 0 too.
23USE_COHERENT_MEM := 0
24
25GIC_ENABLE_V4_EXTN := 1
26
27# GIC-600 configuration
Andre Przywarae1cc1302020-03-25 15:50:38 +000028GICV3_SUPPORT_GIC600 := 1
29
Usama Arifbec5afd2020-04-17 16:13:39 +010030
31# Include GICv3 driver files
32include drivers/arm/gic/v3/gicv3.mk
33
34ENT_GIC_SOURCES := ${GICV3_SOURCES} \
35 plat/common/plat_gicv3.c \
36 plat/arm/common/arm_gicv3.c
37
38override NEED_BL2U := no
39
40override ARM_PLAT_MT := 1
41
42TC0_BASE = plat/arm/board/tc0
43
44PLAT_INCLUDES += -I${TC0_BASE}/include/
45
46TC0_CPU_SOURCES := lib/cpus/aarch64/cortex_matterhorn.S
47
48INTERCONNECT_SOURCES := ${TC0_BASE}/tc0_interconnect.c
49
50PLAT_BL_COMMON_SOURCES += ${TC0_BASE}/tc0_plat.c \
51 ${TC0_BASE}/include/tc0_helpers.S
52
53BL1_SOURCES += ${INTERCONNECT_SOURCES} \
54 ${TC0_CPU_SOURCES} \
55 ${TC0_BASE}/tc0_trusted_boot.c \
56 ${TC0_BASE}/tc0_err.c \
57 drivers/arm/sbsa/sbsa.c
58
59
60BL2_SOURCES += ${TC0_BASE}/tc0_security.c \
61 ${TC0_BASE}/tc0_err.c \
62 ${TC0_BASE}/tc0_trusted_boot.c \
63 lib/utils/mem_region.c \
64 plat/arm/common/arm_nor_psci_mem_protect.c
65
66BL31_SOURCES += ${INTERCONNECT_SOURCES} \
67 ${TC0_CPU_SOURCES} \
68 ${ENT_GIC_SOURCES} \
69 ${TC0_BASE}/tc0_bl31_setup.c \
70 ${TC0_BASE}/tc0_topology.c \
71 drivers/cfi/v2m/v2m_flash.c \
72 lib/utils/mem_region.c \
73 plat/arm/common/arm_nor_psci_mem_protect.c
74
75# Add the FDT_SOURCES and options for Dynamic Config
Manish V Badarkhe64616a52020-05-31 08:53:40 +010076FDT_SOURCES += ${TC0_BASE}/fdts/${PLAT}_fw_config.dts \
77 ${TC0_BASE}/fdts/${PLAT}_tb_fw_config.dts
78FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_fw_config.dtb
79TB_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tb_fw_config.dtb
Usama Arifbec5afd2020-04-17 16:13:39 +010080
Manish V Badarkhe64616a52020-05-31 08:53:40 +010081# Add the FW_CONFIG to FIP and specify the same to certtool
82$(eval $(call TOOL_ADD_PAYLOAD,${FW_CONFIG},--fw-config))
Usama Arifbec5afd2020-04-17 16:13:39 +010083# Add the TB_FW_CONFIG to FIP and specify the same to certtool
84$(eval $(call TOOL_ADD_PAYLOAD,${TB_FW_CONFIG},--tb-fw-config))
85
86#Device tree
87TC0_HW_CONFIG_DTS := fdts/tc0.dts
88TC0_HW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}.dtb
89FDT_SOURCES += ${TC0_HW_CONFIG_DTS}
90$(eval TC0_HW_CONFIG := ${BUILD_PLAT}/$(patsubst %.dts,%.dtb,$(TC0_HW_CONFIG_DTS)))
91
92# Add the HW_CONFIG to FIP and specify the same to certtool
93$(eval $(call TOOL_ADD_PAYLOAD,${TC0_HW_CONFIG},--hw-config))
94
95override CTX_INCLUDE_AARCH32_REGS := 0
96
97override CTX_INCLUDE_PAUTH_REGS := 1
98
99include plat/arm/common/arm_common.mk
100include plat/arm/css/common/css_common.mk
101include plat/arm/soc/common/soc_css.mk
102include plat/arm/board/common/board_common.mk