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Achin Gupta4f6ad662013-10-25 09:08:21 +01001/*
Dan Handleye83b0ca2014-01-14 18:17:09 +00002 * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +01003 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#include <stdio.h>
32#include <string.h>
33#include <assert.h>
Achin Gupta0a9f7472014-02-09 17:48:12 +000034#include <debug.h>
Achin Gupta4f6ad662013-10-25 09:08:21 +010035#include <arch_helpers.h>
36#include <console.h>
37#include <platform.h>
38#include <psci.h>
39#include <psci_private.h>
40
41typedef int (*afflvl_off_handler)(unsigned long, aff_map_node *);
42
43/*******************************************************************************
44 * The next three functions implement a handler for each supported affinity
45 * level which is called when that affinity level is turned off.
46 ******************************************************************************/
47static int psci_afflvl0_off(unsigned long mpidr, aff_map_node *cpu_node)
48{
49 unsigned int index, plat_state;
50 int rc = PSCI_E_SUCCESS;
Vikram Kanigiri78a6e0c2014-03-11 17:41:00 +000051 unsigned long sctlr;
Achin Gupta4f6ad662013-10-25 09:08:21 +010052
53 assert(cpu_node->level == MPIDR_AFFLVL0);
54
Achin Gupta75f73672013-12-05 16:33:10 +000055 /* State management: mark this cpu as turned off */
56 psci_set_state(cpu_node, PSCI_STATE_OFF);
57
Achin Gupta4f6ad662013-10-25 09:08:21 +010058 /*
Achin Gupta607084e2014-02-09 18:24:19 +000059 * Generic management: Get the index for clearing any lingering re-entry
60 * information and allow the secure world to switch itself off
61 */
62
63 /*
64 * Call the cpu off handler registered by the Secure Payload Dispatcher
65 * to let it do any bookeeping. Assume that the SPD always reports an
66 * E_DENIED error if SP refuse to power down
Achin Gupta4f6ad662013-10-25 09:08:21 +010067 */
Jeenu Viswambharan7f366602014-02-20 17:11:00 +000068 if (psci_spd_pm && psci_spd_pm->svc_off) {
69 rc = psci_spd_pm->svc_off(0);
Achin Gupta607084e2014-02-09 18:24:19 +000070 if (rc)
71 return rc;
72 }
73
Achin Gupta4f6ad662013-10-25 09:08:21 +010074 index = cpu_node->data;
75 memset(&psci_ns_entry_info[index], 0, sizeof(psci_ns_entry_info[index]));
76
77 /*
78 * Arch. management. Perform the necessary steps to flush all
79 * cpu caches.
80 *
81 * TODO: This power down sequence varies across cpus so it needs to be
82 * abstracted out on the basis of the MIDR like in cpu_reset_handler().
83 * Do the bare minimal for the time being. Fix this before porting to
84 * Cortex models.
85 */
Vikram Kanigiri78a6e0c2014-03-11 17:41:00 +000086 sctlr = read_sctlr_el3();
Achin Gupta4f6ad662013-10-25 09:08:21 +010087 sctlr &= ~SCTLR_C_BIT;
Vikram Kanigiri78a6e0c2014-03-11 17:41:00 +000088 write_sctlr_el3(sctlr);
Achin Gupta4f6ad662013-10-25 09:08:21 +010089
90 /*
91 * CAUTION: This flush to the level of unification makes an assumption
92 * about the cache hierarchy at affinity level 0 (cpu) in the platform.
93 * Ideally the platform should tell psci which levels to flush to exit
94 * coherency.
95 */
96 dcsw_op_louis(DCCISW);
97
98 /*
99 * Plat. management: Perform platform specific actions to turn this
100 * cpu off e.g. exit cpu coherency, program the power controller etc.
101 */
102 if (psci_plat_pm_ops->affinst_off) {
103
104 /* Get the current physical state of this cpu */
Achin Gupta75f73672013-12-05 16:33:10 +0000105 plat_state = psci_get_phys_state(cpu_node);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100106 rc = psci_plat_pm_ops->affinst_off(mpidr,
107 cpu_node->level,
108 plat_state);
109 }
110
Achin Gupta4f6ad662013-10-25 09:08:21 +0100111 return rc;
112}
113
114static int psci_afflvl1_off(unsigned long mpidr, aff_map_node *cluster_node)
115{
116 int rc = PSCI_E_SUCCESS;
117 unsigned int plat_state;
118
119 /* Sanity check the cluster level */
120 assert(cluster_node->level == MPIDR_AFFLVL1);
121
Achin Gupta75f73672013-12-05 16:33:10 +0000122 /* State management: Decrement the cluster reference count */
123 psci_set_state(cluster_node, PSCI_STATE_OFF);
124
Achin Gupta4f6ad662013-10-25 09:08:21 +0100125 /*
126 * Keep the physical state of this cluster handy to decide
127 * what action needs to be taken
128 */
Achin Gupta75f73672013-12-05 16:33:10 +0000129 plat_state = psci_get_phys_state(cluster_node);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100130
131 /*
132 * Arch. Management. Flush all levels of caches to PoC if
133 * the cluster is to be shutdown
134 */
135 if (plat_state == PSCI_STATE_OFF)
136 dcsw_op_all(DCCISW);
137
138 /*
Achin Gupta3140a9e2013-12-02 16:23:12 +0000139 * Plat. Management. Allow the platform to do its cluster
Achin Gupta4f6ad662013-10-25 09:08:21 +0100140 * specific bookeeping e.g. turn off interconnect coherency,
141 * program the power controller etc.
142 */
143 if (psci_plat_pm_ops->affinst_off)
144 rc = psci_plat_pm_ops->affinst_off(mpidr,
145 cluster_node->level,
146 plat_state);
147
148 return rc;
149}
150
151static int psci_afflvl2_off(unsigned long mpidr, aff_map_node *system_node)
152{
153 int rc = PSCI_E_SUCCESS;
154 unsigned int plat_state;
155
156 /* Cannot go beyond this level */
157 assert(system_node->level == MPIDR_AFFLVL2);
158
Achin Gupta75f73672013-12-05 16:33:10 +0000159 /* State management: Decrement the system reference count */
160 psci_set_state(system_node, PSCI_STATE_OFF);
161
Achin Gupta4f6ad662013-10-25 09:08:21 +0100162 /*
163 * Keep the physical state of the system handy to decide what
164 * action needs to be taken
165 */
Achin Gupta75f73672013-12-05 16:33:10 +0000166 plat_state = psci_get_phys_state(system_node);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100167
168 /* No arch. and generic bookeeping to do here currently */
169
170 /*
Achin Gupta3140a9e2013-12-02 16:23:12 +0000171 * Plat. Management : Allow the platform to do its bookeeping
Achin Gupta4f6ad662013-10-25 09:08:21 +0100172 * at this affinity level
173 */
174 if (psci_plat_pm_ops->affinst_off)
175 rc = psci_plat_pm_ops->affinst_off(mpidr,
176 system_node->level,
177 plat_state);
178 return rc;
179}
180
181static const afflvl_off_handler psci_afflvl_off_handlers[] = {
182 psci_afflvl0_off,
183 psci_afflvl1_off,
184 psci_afflvl2_off,
185};
186
187/*******************************************************************************
Achin Gupta0959db52013-12-02 17:33:04 +0000188 * This function takes an array of pointers to affinity instance nodes in the
189 * topology tree and calls the off handler for the corresponding affinity
190 * levels
191 ******************************************************************************/
192static int psci_call_off_handlers(mpidr_aff_map_nodes mpidr_nodes,
193 int start_afflvl,
194 int end_afflvl,
195 unsigned long mpidr)
196{
197 int rc = PSCI_E_INVALID_PARAMS, level;
198 aff_map_node *node;
199
200 for (level = start_afflvl; level <= end_afflvl; level++) {
201 node = mpidr_nodes[level];
202 if (node == NULL)
203 continue;
204
205 /*
206 * TODO: In case of an error should there be a way
207 * of restoring what we might have torn down at
208 * lower affinity levels.
209 */
210 rc = psci_afflvl_off_handlers[level](mpidr, node);
211 if (rc != PSCI_E_SUCCESS)
212 break;
213 }
214
215 return rc;
216}
217
218/*******************************************************************************
219 * Top level handler which is called when a cpu wants to power itself down.
220 * It's assumed that along with turning the cpu off, higher affinity levels will
221 * be turned off as far as possible. It traverses through all the affinity
222 * levels performing generic, architectural, platform setup and state management
223 * e.g. for a cluster that's to be powered off, it will call the platform
224 * specific code which will disable coherency at the interconnect level if the
225 * cpu is the last in the cluster. For a cpu it could mean programming the power
226 * the power controller etc.
227 *
228 * The state of all the relevant affinity levels is changed prior to calling the
229 * affinity level specific handlers as their actions would depend upon the state
230 * the affinity level is about to enter.
231 *
232 * The affinity level specific handlers are called in ascending order i.e. from
233 * the lowest to the highest affinity level implemented by the platform because
234 * to turn off affinity level X it is neccesary to turn off affinity level X - 1
235 * first.
236 *
237 * CAUTION: This function is called with coherent stacks so that coherency can
238 * be turned off and caches can be flushed safely.
Achin Gupta4f6ad662013-10-25 09:08:21 +0100239 ******************************************************************************/
240int psci_afflvl_off(unsigned long mpidr,
Achin Gupta0959db52013-12-02 17:33:04 +0000241 int start_afflvl,
242 int end_afflvl)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100243{
Achin Gupta0959db52013-12-02 17:33:04 +0000244 int rc = PSCI_E_SUCCESS;
Achin Gupta0959db52013-12-02 17:33:04 +0000245 mpidr_aff_map_nodes mpidr_nodes;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100246
247 mpidr &= MPIDR_AFFINITY_MASK;;
248
249 /*
Achin Gupta0959db52013-12-02 17:33:04 +0000250 * Collect the pointers to the nodes in the topology tree for
251 * each affinity instance in the mpidr. If this function does
252 * not return successfully then either the mpidr or the affinity
253 * levels are incorrect. In either case, we cannot return back
254 * to the caller as it would not know what to do.
Achin Gupta4f6ad662013-10-25 09:08:21 +0100255 */
Achin Gupta0959db52013-12-02 17:33:04 +0000256 rc = psci_get_aff_map_nodes(mpidr,
257 start_afflvl,
258 end_afflvl,
259 mpidr_nodes);
260 assert (rc == PSCI_E_SUCCESS);
261
Achin Gupta4f6ad662013-10-25 09:08:21 +0100262 /*
Achin Gupta0959db52013-12-02 17:33:04 +0000263 * This function acquires the lock corresponding to each affinity
264 * level so that by the time all locks are taken, the system topology
265 * is snapshot and state management can be done safely.
Achin Gupta4f6ad662013-10-25 09:08:21 +0100266 */
Achin Gupta0959db52013-12-02 17:33:04 +0000267 psci_acquire_afflvl_locks(mpidr,
268 start_afflvl,
269 end_afflvl,
270 mpidr_nodes);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100271
Achin Gupta0959db52013-12-02 17:33:04 +0000272 /* Perform generic, architecture and platform specific handling */
273 rc = psci_call_off_handlers(mpidr_nodes,
274 start_afflvl,
275 end_afflvl,
276 mpidr);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100277
278 /*
Achin Gupta0959db52013-12-02 17:33:04 +0000279 * Release the locks corresponding to each affinity level in the
280 * reverse order to which they were acquired.
Achin Gupta4f6ad662013-10-25 09:08:21 +0100281 */
Achin Gupta0959db52013-12-02 17:33:04 +0000282 psci_release_afflvl_locks(mpidr,
283 start_afflvl,
284 end_afflvl,
285 mpidr_nodes);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100286
Achin Gupta4f6ad662013-10-25 09:08:21 +0100287 return rc;
288}