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Achin Gupta4f6ad662013-10-25 09:08:21 +01001/*
Dan Handleye83b0ca2014-01-14 18:17:09 +00002 * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +01003 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#include <stdio.h>
32#include <string.h>
33#include <assert.h>
Achin Gupta0a9f7472014-02-09 17:48:12 +000034#include <debug.h>
Achin Gupta4f6ad662013-10-25 09:08:21 +010035#include <arch_helpers.h>
36#include <console.h>
37#include <platform.h>
38#include <psci.h>
39#include <psci_private.h>
40
41typedef int (*afflvl_off_handler)(unsigned long, aff_map_node *);
42
43/*******************************************************************************
44 * The next three functions implement a handler for each supported affinity
45 * level which is called when that affinity level is turned off.
46 ******************************************************************************/
47static int psci_afflvl0_off(unsigned long mpidr, aff_map_node *cpu_node)
48{
49 unsigned int index, plat_state;
50 int rc = PSCI_E_SUCCESS;
51 unsigned long sctlr = read_sctlr();
52
53 assert(cpu_node->level == MPIDR_AFFLVL0);
54
Achin Gupta75f73672013-12-05 16:33:10 +000055 /* State management: mark this cpu as turned off */
56 psci_set_state(cpu_node, PSCI_STATE_OFF);
57
Achin Gupta4f6ad662013-10-25 09:08:21 +010058 /*
Achin Gupta607084e2014-02-09 18:24:19 +000059 * Generic management: Get the index for clearing any lingering re-entry
60 * information and allow the secure world to switch itself off
61 */
62
63 /*
64 * Call the cpu off handler registered by the Secure Payload Dispatcher
65 * to let it do any bookeeping. Assume that the SPD always reports an
66 * E_DENIED error if SP refuse to power down
Achin Gupta4f6ad662013-10-25 09:08:21 +010067 */
Achin Gupta607084e2014-02-09 18:24:19 +000068 if (spd_pm.svc_off) {
69 rc = spd_pm.svc_off(0);
70 if (rc)
71 return rc;
72 }
73
Achin Gupta4f6ad662013-10-25 09:08:21 +010074 index = cpu_node->data;
75 memset(&psci_ns_entry_info[index], 0, sizeof(psci_ns_entry_info[index]));
76
77 /*
78 * Arch. management. Perform the necessary steps to flush all
79 * cpu caches.
80 *
81 * TODO: This power down sequence varies across cpus so it needs to be
82 * abstracted out on the basis of the MIDR like in cpu_reset_handler().
83 * Do the bare minimal for the time being. Fix this before porting to
84 * Cortex models.
85 */
86 sctlr &= ~SCTLR_C_BIT;
87 write_sctlr(sctlr);
88
89 /*
90 * CAUTION: This flush to the level of unification makes an assumption
91 * about the cache hierarchy at affinity level 0 (cpu) in the platform.
92 * Ideally the platform should tell psci which levels to flush to exit
93 * coherency.
94 */
95 dcsw_op_louis(DCCISW);
96
97 /*
98 * Plat. management: Perform platform specific actions to turn this
99 * cpu off e.g. exit cpu coherency, program the power controller etc.
100 */
101 if (psci_plat_pm_ops->affinst_off) {
102
103 /* Get the current physical state of this cpu */
Achin Gupta75f73672013-12-05 16:33:10 +0000104 plat_state = psci_get_phys_state(cpu_node);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100105 rc = psci_plat_pm_ops->affinst_off(mpidr,
106 cpu_node->level,
107 plat_state);
108 }
109
Achin Gupta4f6ad662013-10-25 09:08:21 +0100110 return rc;
111}
112
113static int psci_afflvl1_off(unsigned long mpidr, aff_map_node *cluster_node)
114{
115 int rc = PSCI_E_SUCCESS;
116 unsigned int plat_state;
117
118 /* Sanity check the cluster level */
119 assert(cluster_node->level == MPIDR_AFFLVL1);
120
Achin Gupta75f73672013-12-05 16:33:10 +0000121 /* State management: Decrement the cluster reference count */
122 psci_set_state(cluster_node, PSCI_STATE_OFF);
123
Achin Gupta4f6ad662013-10-25 09:08:21 +0100124 /*
125 * Keep the physical state of this cluster handy to decide
126 * what action needs to be taken
127 */
Achin Gupta75f73672013-12-05 16:33:10 +0000128 plat_state = psci_get_phys_state(cluster_node);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100129
130 /*
131 * Arch. Management. Flush all levels of caches to PoC if
132 * the cluster is to be shutdown
133 */
134 if (plat_state == PSCI_STATE_OFF)
135 dcsw_op_all(DCCISW);
136
137 /*
Achin Gupta3140a9e2013-12-02 16:23:12 +0000138 * Plat. Management. Allow the platform to do its cluster
Achin Gupta4f6ad662013-10-25 09:08:21 +0100139 * specific bookeeping e.g. turn off interconnect coherency,
140 * program the power controller etc.
141 */
142 if (psci_plat_pm_ops->affinst_off)
143 rc = psci_plat_pm_ops->affinst_off(mpidr,
144 cluster_node->level,
145 plat_state);
146
147 return rc;
148}
149
150static int psci_afflvl2_off(unsigned long mpidr, aff_map_node *system_node)
151{
152 int rc = PSCI_E_SUCCESS;
153 unsigned int plat_state;
154
155 /* Cannot go beyond this level */
156 assert(system_node->level == MPIDR_AFFLVL2);
157
Achin Gupta75f73672013-12-05 16:33:10 +0000158 /* State management: Decrement the system reference count */
159 psci_set_state(system_node, PSCI_STATE_OFF);
160
Achin Gupta4f6ad662013-10-25 09:08:21 +0100161 /*
162 * Keep the physical state of the system handy to decide what
163 * action needs to be taken
164 */
Achin Gupta75f73672013-12-05 16:33:10 +0000165 plat_state = psci_get_phys_state(system_node);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100166
167 /* No arch. and generic bookeeping to do here currently */
168
169 /*
Achin Gupta3140a9e2013-12-02 16:23:12 +0000170 * Plat. Management : Allow the platform to do its bookeeping
Achin Gupta4f6ad662013-10-25 09:08:21 +0100171 * at this affinity level
172 */
173 if (psci_plat_pm_ops->affinst_off)
174 rc = psci_plat_pm_ops->affinst_off(mpidr,
175 system_node->level,
176 plat_state);
177 return rc;
178}
179
180static const afflvl_off_handler psci_afflvl_off_handlers[] = {
181 psci_afflvl0_off,
182 psci_afflvl1_off,
183 psci_afflvl2_off,
184};
185
186/*******************************************************************************
Achin Gupta0959db52013-12-02 17:33:04 +0000187 * This function takes an array of pointers to affinity instance nodes in the
188 * topology tree and calls the off handler for the corresponding affinity
189 * levels
190 ******************************************************************************/
191static int psci_call_off_handlers(mpidr_aff_map_nodes mpidr_nodes,
192 int start_afflvl,
193 int end_afflvl,
194 unsigned long mpidr)
195{
196 int rc = PSCI_E_INVALID_PARAMS, level;
197 aff_map_node *node;
198
199 for (level = start_afflvl; level <= end_afflvl; level++) {
200 node = mpidr_nodes[level];
201 if (node == NULL)
202 continue;
203
204 /*
205 * TODO: In case of an error should there be a way
206 * of restoring what we might have torn down at
207 * lower affinity levels.
208 */
209 rc = psci_afflvl_off_handlers[level](mpidr, node);
210 if (rc != PSCI_E_SUCCESS)
211 break;
212 }
213
214 return rc;
215}
216
217/*******************************************************************************
218 * Top level handler which is called when a cpu wants to power itself down.
219 * It's assumed that along with turning the cpu off, higher affinity levels will
220 * be turned off as far as possible. It traverses through all the affinity
221 * levels performing generic, architectural, platform setup and state management
222 * e.g. for a cluster that's to be powered off, it will call the platform
223 * specific code which will disable coherency at the interconnect level if the
224 * cpu is the last in the cluster. For a cpu it could mean programming the power
225 * the power controller etc.
226 *
227 * The state of all the relevant affinity levels is changed prior to calling the
228 * affinity level specific handlers as their actions would depend upon the state
229 * the affinity level is about to enter.
230 *
231 * The affinity level specific handlers are called in ascending order i.e. from
232 * the lowest to the highest affinity level implemented by the platform because
233 * to turn off affinity level X it is neccesary to turn off affinity level X - 1
234 * first.
235 *
236 * CAUTION: This function is called with coherent stacks so that coherency can
237 * be turned off and caches can be flushed safely.
Achin Gupta4f6ad662013-10-25 09:08:21 +0100238 ******************************************************************************/
239int psci_afflvl_off(unsigned long mpidr,
Achin Gupta0959db52013-12-02 17:33:04 +0000240 int start_afflvl,
241 int end_afflvl)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100242{
Achin Gupta0959db52013-12-02 17:33:04 +0000243 int rc = PSCI_E_SUCCESS;
Achin Gupta0959db52013-12-02 17:33:04 +0000244 mpidr_aff_map_nodes mpidr_nodes;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100245
246 mpidr &= MPIDR_AFFINITY_MASK;;
247
248 /*
Achin Gupta0959db52013-12-02 17:33:04 +0000249 * Collect the pointers to the nodes in the topology tree for
250 * each affinity instance in the mpidr. If this function does
251 * not return successfully then either the mpidr or the affinity
252 * levels are incorrect. In either case, we cannot return back
253 * to the caller as it would not know what to do.
Achin Gupta4f6ad662013-10-25 09:08:21 +0100254 */
Achin Gupta0959db52013-12-02 17:33:04 +0000255 rc = psci_get_aff_map_nodes(mpidr,
256 start_afflvl,
257 end_afflvl,
258 mpidr_nodes);
259 assert (rc == PSCI_E_SUCCESS);
260
Achin Gupta4f6ad662013-10-25 09:08:21 +0100261 /*
Achin Gupta0959db52013-12-02 17:33:04 +0000262 * This function acquires the lock corresponding to each affinity
263 * level so that by the time all locks are taken, the system topology
264 * is snapshot and state management can be done safely.
Achin Gupta4f6ad662013-10-25 09:08:21 +0100265 */
Achin Gupta0959db52013-12-02 17:33:04 +0000266 psci_acquire_afflvl_locks(mpidr,
267 start_afflvl,
268 end_afflvl,
269 mpidr_nodes);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100270
Achin Gupta0959db52013-12-02 17:33:04 +0000271 /* Perform generic, architecture and platform specific handling */
272 rc = psci_call_off_handlers(mpidr_nodes,
273 start_afflvl,
274 end_afflvl,
275 mpidr);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100276
277 /*
Achin Gupta0959db52013-12-02 17:33:04 +0000278 * Release the locks corresponding to each affinity level in the
279 * reverse order to which they were acquired.
Achin Gupta4f6ad662013-10-25 09:08:21 +0100280 */
Achin Gupta0959db52013-12-02 17:33:04 +0000281 psci_release_afflvl_locks(mpidr,
282 start_afflvl,
283 end_afflvl,
284 mpidr_nodes);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100285
Achin Gupta4f6ad662013-10-25 09:08:21 +0100286 return rc;
287}