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git01.mediatek.com / filogic / atf / 3f5be1c0a78f1c43b378a6e56919cac3151ccfdb / . / include / lib / cpus / aarch64 / cortex_makalu_elp_arm.h
blob: 9ed5ee3c7e90848d1aa96a1775ef2f7901be7c7a [file] [log] [blame]
johpow01cd38ac42021-03-15 15:07:21 -0500[diff] [blame]1/*
Bipin Ravi32464ba2022-05-06 16:02:30 -0500[diff] [blame]2 * Copyright (c) 2021-2022, Arm Limited. All rights reserved.
johpow01cd38ac42021-03-15 15:07:21 -0500[diff] [blame]3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
johpow014c42c0d2021-04-20 17:05:04 -0500[diff] [blame]7#ifndef CORTEX_MAKALU_ELP_ARM_H
8#define CORTEX_MAKALU_ELP_ARM_H
johpow01cd38ac42021-03-15 15:07:21 -0500[diff] [blame]9
johpow014c42c0d2021-04-20 17:05:04 -0500[diff] [blame]10#define CORTEX_MAKALU_ELP_ARM_MIDR U(0x410FD4E0)
johpow01cd38ac42021-03-15 15:07:21 -0500[diff] [blame]11
Bipin Ravi32464ba2022-05-06 16:02:30 -0500[diff] [blame]12/* Cortex Makalu ELP loop count for CVE-2022-23960 mitigation */
13#define CORTEX_MAKALU_ELP_ARM_BHB_LOOP_COUNT U(132)
14
johpow01cd38ac42021-03-15 15:07:21 -0500[diff] [blame]15/*******************************************************************************
16 * CPU Extended Control register specific definitions
17 ******************************************************************************/
johpow014c42c0d2021-04-20 17:05:04 -0500[diff] [blame]18#define CORTEX_MAKALU_ELP_ARM_CPUECTLR_EL1 S3_0_C15_C1_4
johpow01cd38ac42021-03-15 15:07:21 -0500[diff] [blame]19
20/*******************************************************************************
21 * CPU Power Control register specific definitions
22 ******************************************************************************/
johpow014c42c0d2021-04-20 17:05:04 -0500[diff] [blame]23#define CORTEX_MAKALU_ELP_ARM_CPUPWRCTLR_EL1 S3_0_C15_C2_7
24#define CORTEX_MAKALU_ELP_ARM_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1)
johpow01cd38ac42021-03-15 15:07:21 -0500[diff] [blame]25
johpow014c42c0d2021-04-20 17:05:04 -0500[diff] [blame]26#endif /* CORTEX_MAKALU_ELP_ARM_H */