| johpow01 | cd38ac4 | 2021-03-15 15:07:21 -0500 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2021, Arm Limited. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| johpow01 | 4c42c0d | 2021-04-20 17:05:04 -0500 | [diff] [blame^] | 7 | #ifndef CORTEX_MAKALU_ELP_ARM_H |
| 8 | #define CORTEX_MAKALU_ELP_ARM_H |
| johpow01 | cd38ac4 | 2021-03-15 15:07:21 -0500 | [diff] [blame] | 9 | |
| johpow01 | 4c42c0d | 2021-04-20 17:05:04 -0500 | [diff] [blame^] | 10 | #define CORTEX_MAKALU_ELP_ARM_MIDR U(0x410FD4E0) |
| johpow01 | cd38ac4 | 2021-03-15 15:07:21 -0500 | [diff] [blame] | 11 | |
| 12 | /******************************************************************************* |
| 13 | * CPU Extended Control register specific definitions |
| 14 | ******************************************************************************/ |
| johpow01 | 4c42c0d | 2021-04-20 17:05:04 -0500 | [diff] [blame^] | 15 | #define CORTEX_MAKALU_ELP_ARM_CPUECTLR_EL1 S3_0_C15_C1_4 |
| johpow01 | cd38ac4 | 2021-03-15 15:07:21 -0500 | [diff] [blame] | 16 | |
| 17 | /******************************************************************************* |
| 18 | * CPU Power Control register specific definitions |
| 19 | ******************************************************************************/ |
| johpow01 | 4c42c0d | 2021-04-20 17:05:04 -0500 | [diff] [blame^] | 20 | #define CORTEX_MAKALU_ELP_ARM_CPUPWRCTLR_EL1 S3_0_C15_C2_7 |
| 21 | #define CORTEX_MAKALU_ELP_ARM_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1) |
| johpow01 | cd38ac4 | 2021-03-15 15:07:21 -0500 | [diff] [blame] | 22 | |
| johpow01 | 4c42c0d | 2021-04-20 17:05:04 -0500 | [diff] [blame^] | 23 | #endif /* CORTEX_MAKALU_ELP_ARM_H */ |