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Andre Przywara6d471e12019-07-09 11:25:57 +01001#
Chris Kay523e8642023-12-04 12:03:51 +00002# Copyright (c) 2013-2024, Arm Limited and Contributors. All rights reserved.
Andre Przywara6d471e12019-07-09 11:25:57 +01003#
4# SPDX-License-Identifier: BSD-3-Clause
5#
6
7include lib/libfdt/libfdt.mk
8include lib/xlat_tables_v2/xlat_tables.mk
9
Jan Kiszkacdd95e72021-03-22 20:42:33 +010010include drivers/arm/gic/v2/gicv2.mk
11
Andre Przywara6d471e12019-07-09 11:25:57 +010012PLAT_INCLUDES := -Iplat/rpi/common/include \
13 -Iplat/rpi/rpi4/include
14
15PLAT_BL_COMMON_SOURCES := drivers/ti/uart/aarch64/16550_console.S \
Andre Przywara9ba6bb02020-03-10 12:34:56 +000016 drivers/arm/pl011/aarch64/pl011_console.S \
Andre Przywara6d471e12019-07-09 11:25:57 +010017 plat/rpi/common/rpi3_common.c \
Mario Bălănicăc258e4c2023-12-01 04:59:43 +020018 plat/rpi/common/rpi3_console_dual.c \
Andre Przywara6d471e12019-07-09 11:25:57 +010019 ${XLAT_TABLES_LIB_SRCS}
20
21BL31_SOURCES += lib/cpus/aarch64/cortex_a72.S \
Andre Przywara98e48562020-03-12 14:20:04 +000022 plat/rpi/common/aarch64/plat_helpers.S \
Mario Bălănică3a946f32023-12-01 04:30:13 +020023 plat/rpi/common/aarch64/armstub8_header.S \
Andre Przywara980556d2020-03-11 15:18:03 +000024 drivers/delay_timer/delay_timer.c \
25 drivers/gpio/gpio.c \
26 drivers/rpi3/gpio/rpi3_gpio.c \
Andre Przywara6d471e12019-07-09 11:25:57 +010027 plat/common/plat_gicv2.c \
Mario Bălănică3a946f32023-12-01 04:30:13 +020028 plat/rpi/common/rpi4_bl31_setup.c \
29 plat/rpi/rpi4/rpi4_setup.c \
Andre Przywara6d471e12019-07-09 11:25:57 +010030 plat/rpi/common/rpi3_pm.c \
31 plat/common/plat_psci_common.c \
32 plat/rpi/common/rpi3_topology.c \
Andre Przywara88c9e1d2019-07-11 01:45:39 +010033 common/fdt_fixup.c \
Jan Kiszkacdd95e72021-03-22 20:42:33 +010034 ${LIBFDT_SRCS} \
35 ${GICV2_SOURCES}
Andre Przywara6d471e12019-07-09 11:25:57 +010036
37# For now we only support BL31, using the kernel loaded by the GPU firmware.
38RESET_TO_BL31 := 1
39
40# All CPUs enter armstub8.bin.
41COLD_BOOT_SINGLE_CPU := 0
42
43# Tune compiler for Cortex-A72
Chris Kaycfba6452023-12-04 09:55:50 +000044ifeq ($($(ARCH)-cc-id),arm-clang)
Andre Przywara6d471e12019-07-09 11:25:57 +010045 TF_CFLAGS_aarch64 += -mcpu=cortex-a72
Chris Kaycfba6452023-12-04 09:55:50 +000046else ifneq ($(filter %-clang,$($(ARCH)-cc-id)),)
Andre Przywara6d471e12019-07-09 11:25:57 +010047 TF_CFLAGS_aarch64 += -mcpu=cortex-a72
48else
49 TF_CFLAGS_aarch64 += -mtune=cortex-a72
50endif
51
Andre Przywara2d8e99a2019-07-10 18:09:18 +010052# Add support for platform supplied linker script for BL31 build
53$(eval $(call add_define,PLAT_EXTRA_LD_SCRIPT))
Andre Przywara6d471e12019-07-09 11:25:57 +010054
55# Enable all errata workarounds for Cortex-A72
56ERRATA_A72_859971 := 1
57
58WORKAROUND_CVE_2017_5715 := 1
59
60# Add new default target when compiling this platform
61all: bl31
62
63# Build config flags
64# ------------------
65
66# Disable stack protector by default
67ENABLE_STACK_PROTECTOR := 0
68
69# Have different sections for code and rodata
70SEPARATE_CODE_AND_RODATA := 1
71
72# Use Coherent memory
73USE_COHERENT_MEM := 1
74
75# Platform build flags
76# --------------------
77
Andre Przywaraaa89ae42019-07-11 01:42:12 +010078# There is not much else than a Linux kernel to load at the moment.
79RPI3_DIRECT_LINUX_BOOT := 1
Andre Przywara6d471e12019-07-09 11:25:57 +010080
81# BL33 images are in AArch64 by default
82RPI3_BL33_IN_AARCH32 := 0
83
84# UART to use at runtime. -1 means the runtime UART is disabled.
85# Any other value means the default UART will be used.
86RPI3_RUNTIME_UART := 0
87
88# Use normal memory mapping for ROM, FIP, SRAM and DRAM
89RPI3_USE_UEFI_MAP := 0
90
Jeremy Linton15242d52020-11-18 10:13:30 -060091# SMCCC PCI support (should be enabled for ACPI builds)
92SMC_PCI_SUPPORT := 0
93
Andre Przywara6d471e12019-07-09 11:25:57 +010094# Process platform flags
95# ----------------------
96
97$(eval $(call add_define,RPI3_BL33_IN_AARCH32))
98$(eval $(call add_define,RPI3_DIRECT_LINUX_BOOT))
99ifdef RPI3_PRELOADED_DTB_BASE
100$(eval $(call add_define,RPI3_PRELOADED_DTB_BASE))
101endif
102$(eval $(call add_define,RPI3_RUNTIME_UART))
103$(eval $(call add_define,RPI3_USE_UEFI_MAP))
Jeremy Linton15242d52020-11-18 10:13:30 -0600104$(eval $(call add_define,SMC_PCI_SUPPORT))
Andre Przywara6d471e12019-07-09 11:25:57 +0100105
Andre Przywara6d471e12019-07-09 11:25:57 +0100106ifeq (${ARCH},aarch32)
107 $(error Error: AArch32 not supported on rpi4)
108endif
109
110ifneq ($(ENABLE_STACK_PROTECTOR), 0)
111PLAT_BL_COMMON_SOURCES += drivers/rpi3/rng/rpi3_rng.c \
112 plat/rpi/common/rpi3_stack_protector.c
113endif
Jeremy Linton15242d52020-11-18 10:13:30 -0600114
115ifeq ($(SMC_PCI_SUPPORT), 1)
Mario Bălănicăda8a3902024-03-06 06:10:52 +0200116BL31_SOURCES += plat/rpi/common/rpi_pci_svc.c
Jeremy Linton15242d52020-11-18 10:13:30 -0600117endif