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git01.mediatek.com / filogic / atf / 3df71e2a65b8b06d4541d5927660bca5b024681f / . / plat / rockchip / rk3399 / drivers / dram / dram.h
blob: 0780fc3a2627b6b4ddacf7dcaf24593530a8343d [file] [log] [blame]
Caesar Wang9740bba2016-08-25 08:37:42 +0800[diff] [blame]1/*
2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
3 *
dp-armfa3cf0b2017-05-03 09:38:09 +0100[diff] [blame]4 * SPDX-License-Identifier: BSD-3-Clause
Caesar Wang9740bba2016-08-25 08:37:42 +0800[diff] [blame]5 */
6
Caesar Wanga8456902016-10-27 01:12:34 +0800[diff] [blame]7#ifndef __SOC_ROCKCHIP_RK3399_DRAM_H__
8#define __SOC_ROCKCHIP_RK3399_DRAM_H__
Xing Zhengb4bcc1d2017-02-24 16:26:11 +0800[diff] [blame]9
10#include <dram_regs.h>
Caesar Wanga8456902016-10-27 01:12:34 +0800[diff] [blame]11#include <plat_private.h>
12#include <stdint.h>
Caesar Wang9740bba2016-08-25 08:37:42 +0800[diff] [blame]13
Caesar Wanga8456902016-10-27 01:12:34 +0800[diff] [blame]14enum {
15 DDR3 = 3,
16 LPDDR2 = 5,
17 LPDDR3 = 6,
18 LPDDR4 = 7,
19 UNUSED = 0xff
20};
Caesar Wang9740bba2016-08-25 08:37:42 +0800[diff] [blame]21
22struct rk3399_ddr_pctl_regs {
Caesar Wanga8456902016-10-27 01:12:34 +0800[diff] [blame]23 uint32_t denali_ctl[CTL_REG_NUM];
Caesar Wang9740bba2016-08-25 08:37:42 +0800[diff] [blame]24};
25
26struct rk3399_ddr_publ_regs {
Derek Basehore6af5af02017-05-05 17:53:33 -0700[diff] [blame]27 /*
Lin Huang94bdbc42017-05-26 16:17:11 +0800[diff] [blame]28 * PHY registers from 0 to 90 for slice1.
29 * These are used to restore slice1-4 on resume.
Derek Basehore6af5af02017-05-05 17:53:33 -0700[diff] [blame]30 */
Lin Huang94bdbc42017-05-26 16:17:11 +0800[diff] [blame]31 uint32_t phy0[91];
Derek Basehore6af5af02017-05-05 17:53:33 -0700[diff] [blame]32 /*
33 * PHY registers from 512 to 895.
34 * Only registers 0-37 of each 128 register range are used.
35 */
36 uint32_t phy512[3][38];
37 uint32_t phy896[63];
Caesar Wang9740bba2016-08-25 08:37:42 +0800[diff] [blame]38};
39
Caesar Wang9740bba2016-08-25 08:37:42 +0800[diff] [blame]40struct rk3399_ddr_pi_regs {
Caesar Wanga8456902016-10-27 01:12:34 +0800[diff] [blame]41 uint32_t denali_pi[PI_REG_NUM];
Caesar Wang9740bba2016-08-25 08:37:42 +0800[diff] [blame]42};
43union noc_ddrtiminga0 {
44 uint32_t d32;
45 struct {
46 unsigned acttoact : 6;
47 unsigned reserved0 : 2;
48 unsigned rdtomiss : 6;
49 unsigned reserved1 : 2;
50 unsigned wrtomiss : 6;
51 unsigned reserved2 : 2;
52 unsigned readlatency : 8;
53 } b;
54};
55
56union noc_ddrtimingb0 {
57 uint32_t d32;
58 struct {
59 unsigned rdtowr : 5;
60 unsigned reserved0 : 3;
61 unsigned wrtord : 5;
62 unsigned reserved1 : 3;
63 unsigned rrd : 4;
64 unsigned reserved2 : 4;
65 unsigned faw : 6;
66 unsigned reserved3 : 2;
67 } b;
68};
69
70union noc_ddrtimingc0 {
71 uint32_t d32;
72 struct {
73 unsigned burstpenalty : 4;
74 unsigned reserved0 : 4;
75 unsigned wrtomwr : 6;
76 unsigned reserved1 : 18;
77 } b;
78};
79
80union noc_devtodev0 {
81 uint32_t d32;
82 struct {
83 unsigned busrdtord : 3;
84 unsigned reserved0 : 1;
85 unsigned busrdtowr : 3;
86 unsigned reserved1 : 1;
87 unsigned buswrtord : 3;
88 unsigned reserved2 : 1;
89 unsigned buswrtowr : 3;
90 unsigned reserved3 : 17;
91 } b;
92};
93
94union noc_ddrmode {
95 uint32_t d32;
96 struct {
97 unsigned autoprecharge : 1;
98 unsigned bypassfiltering : 1;
99 unsigned fawbank : 1;
100 unsigned burstsize : 2;
101 unsigned mwrsize : 2;
102 unsigned reserved2 : 1;
103 unsigned forceorder : 8;
104 unsigned forceorderstate : 8;
105 unsigned reserved3 : 8;
106 } b;
107};
108
Caesar Wang9740bba2016-08-25 08:37:42 +0800[diff] [blame]109struct rk3399_msch_timings {
110 union noc_ddrtiminga0 ddrtiminga0;
111 union noc_ddrtimingb0 ddrtimingb0;
112 union noc_ddrtimingc0 ddrtimingc0;
113 union noc_devtodev0 devtodev0;
114 union noc_ddrmode ddrmode;
115 uint32_t agingx0;
116};
Caesar Wanga8456902016-10-27 01:12:34 +0800[diff] [blame]117
Caesar Wang9740bba2016-08-25 08:37:42 +0800[diff] [blame]118struct rk3399_sdram_channel {
119 unsigned char rank;
120 /* col = 0, means this channel is invalid */
121 unsigned char col;
122 /* 3:8bank, 2:4bank */
123 unsigned char bk;
124 /* channel buswidth, 2:32bit, 1:16bit, 0:8bit */
125 unsigned char bw;
126 /* die buswidth, 2:32bit, 1:16bit, 0:8bit */
127 unsigned char dbw;
128 /* row_3_4 = 1: 6Gb or 12Gb die
129 * row_3_4 = 0: normal die, power of 2
130 */
131 unsigned char row_3_4;
132 unsigned char cs0_row;
133 unsigned char cs1_row;
134 uint32_t ddrconfig;
135 struct rk3399_msch_timings noc_timings;
136};
137
138struct rk3399_sdram_params {
139 struct rk3399_sdram_channel ch[2];
140 uint32_t ddr_freq;
141 unsigned char dramtype;
142 unsigned char num_channels;
143 unsigned char stride;
144 unsigned char odt;
145 struct rk3399_ddr_pctl_regs pctl_regs;
146 struct rk3399_ddr_pi_regs pi_regs;
147 struct rk3399_ddr_publ_regs phy_regs;
Derek Basehore04c74b92017-01-31 00:20:19 -0800[diff] [blame]148 uint32_t rx_cal_dqs[2][4];
Caesar Wang9740bba2016-08-25 08:37:42 +0800[diff] [blame]149};
Caesar Wang9740bba2016-08-25 08:37:42 +0800[diff] [blame]150
Caesar Wanga8456902016-10-27 01:12:34 +0800[diff] [blame]151extern __sramdata struct rk3399_sdram_params sdram_config;
Caesar Wang9740bba2016-08-25 08:37:42 +0800[diff] [blame]152
Caesar Wanga8456902016-10-27 01:12:34 +0800[diff] [blame]153void dram_init(void);
Caesar Wang9740bba2016-08-25 08:37:42 +0800[diff] [blame]154
Caesar Wang9740bba2016-08-25 08:37:42 +0800[diff] [blame]155#endif