blob: 5cc33903746122de8642e0cfe10f87ab19733d8c [file] [log] [blame]
Yann Gautier4b0c72a2018-07-16 10:54:09 +02001/*
Nicolas Toromanoff5a937cd2022-02-07 10:12:04 +01002 * Copyright (c) 2015-2022, ARM Limited and Contributors. All rights reserved.
Yann Gautier4b0c72a2018-07-16 10:54:09 +02003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
Yann Gautier4b0c72a2018-07-16 10:54:09 +02007#include <assert.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00008#include <string.h>
9
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000010#include <arch_helpers.h>
11#include <common/debug.h>
Yann Gautiera3bd8d12021-06-18 11:33:26 +020012#include <common/desc_image_load.h>
Sughosh Ganub721f8a2021-12-01 16:45:11 +053013#include <drivers/fwu/fwu.h>
14#include <drivers/fwu/fwu_metadata.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000015#include <drivers/io/io_block.h>
16#include <drivers/io/io_driver.h>
Yann Gautier0ed7b2a2021-05-19 18:48:16 +020017#include <drivers/io/io_fip.h>
Patrick Delaunay9c5ee782021-07-06 14:07:56 +020018#include <drivers/io/io_memmap.h>
Lionel Debieve402a46b2019-11-04 12:28:15 +010019#include <drivers/io/io_mtd.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000020#include <drivers/io/io_storage.h>
21#include <drivers/mmc.h>
Sughosh Ganub721f8a2021-12-01 16:45:11 +053022#include <drivers/partition/efi.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000023#include <drivers/partition/partition.h>
Lionel Debieve402a46b2019-11-04 12:28:15 +010024#include <drivers/raw_nand.h>
Lionel Debieve186b0462019-09-24 18:30:12 +020025#include <drivers/spi_nand.h>
Lionel Debievecb0dbc42019-09-25 09:11:31 +020026#include <drivers/spi_nor.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000027#include <drivers/st/io_mmc.h>
Lionel Debieve402a46b2019-11-04 12:28:15 +010028#include <drivers/st/stm32_fmc2_nand.h>
Lionel Debieve186b0462019-09-24 18:30:12 +020029#include <drivers/st/stm32_qspi.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000030#include <drivers/st/stm32_sdmmc2.h>
Patrick Delaunay9c5ee782021-07-06 14:07:56 +020031#include <drivers/usb_device.h>
Yann Gautier29f1f942021-07-13 18:07:41 +020032#include <lib/fconf/fconf.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000033#include <lib/mmio.h>
34#include <lib/utils.h>
35#include <plat/common/platform.h>
Yann Gautier0ed7b2a2021-05-19 18:48:16 +020036#include <tools_share/firmware_image_package.h>
37
38#include <platform_def.h>
Patrick Delaunay9c5ee782021-07-06 14:07:56 +020039#include <stm32cubeprogrammer.h>
Yann Gautier29f1f942021-07-13 18:07:41 +020040#include <stm32mp_fconf_getter.h>
Patrick Delaunay9c5ee782021-07-06 14:07:56 +020041#include <usb_dfu.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000042
Yann Gautier4b0c72a2018-07-16 10:54:09 +020043/* IO devices */
Yann Gautier0ed7b2a2021-05-19 18:48:16 +020044uintptr_t fip_dev_handle;
45uintptr_t storage_dev_handle;
Yann Gautier4b0c72a2018-07-16 10:54:09 +020046
Yann Gautier0ed7b2a2021-05-19 18:48:16 +020047static const io_dev_connector_t *fip_dev_con;
Yann Gautier8244e1d2018-10-15 09:36:58 +020048
Nicolas Le Bayon3f42cad2019-09-03 09:52:05 +020049#if STM32MP_SDMMC || STM32MP_EMMC
Yann Gautierac22dd52021-03-22 14:22:14 +010050static struct mmc_device_info mmc_info;
Yann Gautier8244e1d2018-10-15 09:36:58 +020051
Yann Gautierf9af3bc2018-11-09 15:57:18 +010052static uint32_t block_buffer[MMC_BLOCK_SIZE] __aligned(MMC_BLOCK_SIZE);
Yann Gautier8244e1d2018-10-15 09:36:58 +020053
Yann Gautiera3bd8d12021-06-18 11:33:26 +020054static io_block_dev_spec_t mmc_block_dev_spec = {
Yann Gautier8244e1d2018-10-15 09:36:58 +020055 /* It's used as temp buffer in block driver */
56 .buffer = {
57 .offset = (size_t)&block_buffer,
58 .length = MMC_BLOCK_SIZE,
59 },
60 .ops = {
61 .read = mmc_read_blocks,
62 .write = NULL,
63 },
64 .block_size = MMC_BLOCK_SIZE,
65};
Vyacheslav Yurkove43a0802021-06-04 10:10:51 +020066
Yann Gautier8244e1d2018-10-15 09:36:58 +020067static const io_dev_connector_t *mmc_dev_con;
Nicolas Le Bayon3f42cad2019-09-03 09:52:05 +020068#endif /* STM32MP_SDMMC || STM32MP_EMMC */
Yann Gautier8244e1d2018-10-15 09:36:58 +020069
Lionel Debievecb0dbc42019-09-25 09:11:31 +020070#if STM32MP_SPI_NOR
71static io_mtd_dev_spec_t spi_nor_dev_spec = {
72 .ops = {
73 .init = spi_nor_init,
74 .read = spi_nor_read,
75 },
76};
77#endif
78
Lionel Debieve402a46b2019-11-04 12:28:15 +010079#if STM32MP_RAW_NAND
80static io_mtd_dev_spec_t nand_dev_spec = {
81 .ops = {
82 .init = nand_raw_init,
83 .read = nand_read,
Yann Gautier0ed7b2a2021-05-19 18:48:16 +020084 .seek = nand_seek_bb
Lionel Debieve402a46b2019-11-04 12:28:15 +010085 },
86};
87
88static const io_dev_connector_t *nand_dev_con;
89#endif
90
Lionel Debieve186b0462019-09-24 18:30:12 +020091#if STM32MP_SPI_NAND
92static io_mtd_dev_spec_t spi_nand_dev_spec = {
93 .ops = {
94 .init = spi_nand_init,
95 .read = nand_read,
Yann Gautier0ed7b2a2021-05-19 18:48:16 +020096 .seek = nand_seek_bb
Lionel Debieve186b0462019-09-24 18:30:12 +020097 },
98};
Lionel Debievecb0dbc42019-09-25 09:11:31 +020099#endif
Lionel Debieve186b0462019-09-24 18:30:12 +0200100
Lionel Debievecb0dbc42019-09-25 09:11:31 +0200101#if STM32MP_SPI_NAND || STM32MP_SPI_NOR
Lionel Debieve186b0462019-09-24 18:30:12 +0200102static const io_dev_connector_t *spi_dev_con;
103#endif
104
Patrick Delaunaye50571b2021-10-28 13:48:52 +0200105#if STM32MP_UART_PROGRAMMER || STM32MP_USB_PROGRAMMER
Patrick Delaunay9c5ee782021-07-06 14:07:56 +0200106static const io_dev_connector_t *memmap_dev_con;
107#endif
108
Yann Gautier29f1f942021-07-13 18:07:41 +0200109io_block_spec_t image_block_spec = {
Yann Gautier0ed7b2a2021-05-19 18:48:16 +0200110 .offset = 0U,
111 .length = 0U,
112};
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200113
Yann Gautier29f1f942021-07-13 18:07:41 +0200114int open_fip(const uintptr_t spec)
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200115{
Yann Gautier0ed7b2a2021-05-19 18:48:16 +0200116 return io_dev_init(fip_dev_handle, (uintptr_t)FIP_IMAGE_ID);
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200117}
Yann Gautier8244e1d2018-10-15 09:36:58 +0200118
Yann Gautier29f1f942021-07-13 18:07:41 +0200119int open_storage(const uintptr_t spec)
Yann Gautier8244e1d2018-10-15 09:36:58 +0200120{
121 return io_dev_init(storage_dev_handle, 0);
122}
Vyacheslav Yurkove43a0802021-06-04 10:10:51 +0200123
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200124static void print_boot_device(boot_api_context_t *boot_context)
125{
126 switch (boot_context->boot_interface_selected) {
127 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_SD:
128 INFO("Using SDMMC\n");
129 break;
130 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_EMMC:
131 INFO("Using EMMC\n");
132 break;
Lionel Debievecb0dbc42019-09-25 09:11:31 +0200133 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NOR_QSPI:
134 INFO("Using QSPI NOR\n");
135 break;
Lionel Debieve402a46b2019-11-04 12:28:15 +0100136 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_FMC:
137 INFO("Using FMC NAND\n");
138 break;
Lionel Debieve186b0462019-09-24 18:30:12 +0200139 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_QSPI:
140 INFO("Using SPI NAND\n");
141 break;
Patrick Delaunaye50571b2021-10-28 13:48:52 +0200142 case BOOT_API_CTX_BOOT_INTERFACE_SEL_SERIAL_UART:
143 INFO("Using UART\n");
144 break;
Patrick Delaunay9c5ee782021-07-06 14:07:56 +0200145 case BOOT_API_CTX_BOOT_INTERFACE_SEL_SERIAL_USB:
146 INFO("Using USB\n");
147 break;
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200148 default:
Yann Gautier0ed7b2a2021-05-19 18:48:16 +0200149 ERROR("Boot interface %u not found\n",
150 boot_context->boot_interface_selected);
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200151 panic();
152 break;
153 }
154
155 if (boot_context->boot_interface_instance != 0U) {
156 INFO(" Instance %d\n", boot_context->boot_interface_instance);
157 }
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200158}
159
Nicolas Le Bayon3f42cad2019-09-03 09:52:05 +0200160#if STM32MP_SDMMC || STM32MP_EMMC
Yann Gautiereae3fbf2019-04-23 13:34:03 +0200161static void boot_mmc(enum mmc_device_type mmc_dev_type,
162 uint16_t boot_interface_instance)
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200163{
164 int io_result __unused;
Yann Gautier8244e1d2018-10-15 09:36:58 +0200165 struct stm32_sdmmc2_params params;
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200166
Yann Gautiereae3fbf2019-04-23 13:34:03 +0200167 zeromem(&params, sizeof(struct stm32_sdmmc2_params));
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200168
Yann Gautierac22dd52021-03-22 14:22:14 +0100169 mmc_info.mmc_dev_type = mmc_dev_type;
Yann Gautiereae3fbf2019-04-23 13:34:03 +0200170
171 switch (boot_interface_instance) {
172 case 1:
173 params.reg_base = STM32MP_SDMMC1_BASE;
174 break;
175 case 2:
176 params.reg_base = STM32MP_SDMMC2_BASE;
177 break;
178 case 3:
179 params.reg_base = STM32MP_SDMMC3_BASE;
180 break;
181 default:
182 WARN("SDMMC instance not found, using default\n");
183 if (mmc_dev_type == MMC_IS_SD) {
184 params.reg_base = STM32MP_SDMMC1_BASE;
185 } else {
186 params.reg_base = STM32MP_SDMMC2_BASE;
187 }
188 break;
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200189 }
190
Yann Gautierac22dd52021-03-22 14:22:14 +0100191 params.device_info = &mmc_info;
Yann Gautiereae3fbf2019-04-23 13:34:03 +0200192 if (stm32_sdmmc2_mmc_init(&params) != 0) {
193 ERROR("SDMMC%u init failed\n", boot_interface_instance);
194 panic();
195 }
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200196
Yann Gautiereae3fbf2019-04-23 13:34:03 +0200197 /* Open MMC as a block device to read GPT table */
198 io_result = register_io_dev_block(&mmc_dev_con);
199 if (io_result != 0) {
200 panic();
201 }
Yann Gautier8244e1d2018-10-15 09:36:58 +0200202
Yann Gautiereae3fbf2019-04-23 13:34:03 +0200203 io_result = io_dev_open(mmc_dev_con, (uintptr_t)&mmc_block_dev_spec,
204 &storage_dev_handle);
205 assert(io_result == 0);
Yann Gautiereae3fbf2019-04-23 13:34:03 +0200206}
Nicolas Le Bayon3f42cad2019-09-03 09:52:05 +0200207#endif /* STM32MP_SDMMC || STM32MP_EMMC */
Yann Gautier8244e1d2018-10-15 09:36:58 +0200208
Lionel Debievecb0dbc42019-09-25 09:11:31 +0200209#if STM32MP_SPI_NOR
210static void boot_spi_nor(boot_api_context_t *boot_context)
211{
212 int io_result __unused;
Lionel Debievecb0dbc42019-09-25 09:11:31 +0200213
214 io_result = stm32_qspi_init();
215 assert(io_result == 0);
216
217 io_result = register_io_dev_mtd(&spi_dev_con);
218 assert(io_result == 0);
219
220 /* Open connections to device */
221 io_result = io_dev_open(spi_dev_con,
222 (uintptr_t)&spi_nor_dev_spec,
223 &storage_dev_handle);
224 assert(io_result == 0);
Lionel Debievecb0dbc42019-09-25 09:11:31 +0200225}
226#endif /* STM32MP_SPI_NOR */
227
Lionel Debieve402a46b2019-11-04 12:28:15 +0100228#if STM32MP_RAW_NAND
229static void boot_fmc2_nand(boot_api_context_t *boot_context)
230{
231 int io_result __unused;
Lionel Debieve402a46b2019-11-04 12:28:15 +0100232
233 io_result = stm32_fmc2_init();
234 assert(io_result == 0);
235
236 /* Register the IO device on this platform */
237 io_result = register_io_dev_mtd(&nand_dev_con);
238 assert(io_result == 0);
239
240 /* Open connections to device */
241 io_result = io_dev_open(nand_dev_con, (uintptr_t)&nand_dev_spec,
242 &storage_dev_handle);
243 assert(io_result == 0);
Lionel Debieve402a46b2019-11-04 12:28:15 +0100244}
245#endif /* STM32MP_RAW_NAND */
246
Lionel Debieve186b0462019-09-24 18:30:12 +0200247#if STM32MP_SPI_NAND
248static void boot_spi_nand(boot_api_context_t *boot_context)
249{
250 int io_result __unused;
Lionel Debieve186b0462019-09-24 18:30:12 +0200251
252 io_result = stm32_qspi_init();
253 assert(io_result == 0);
254
255 io_result = register_io_dev_mtd(&spi_dev_con);
256 assert(io_result == 0);
257
258 /* Open connections to device */
259 io_result = io_dev_open(spi_dev_con,
260 (uintptr_t)&spi_nand_dev_spec,
261 &storage_dev_handle);
262 assert(io_result == 0);
Lionel Debieve186b0462019-09-24 18:30:12 +0200263}
264#endif /* STM32MP_SPI_NAND */
265
Patrick Delaunaye50571b2021-10-28 13:48:52 +0200266#if STM32MP_UART_PROGRAMMER || STM32MP_USB_PROGRAMMER
Patrick Delaunay9c5ee782021-07-06 14:07:56 +0200267static void mmap_io_setup(void)
268{
269 int io_result __unused;
270
271 io_result = register_io_dev_memmap(&memmap_dev_con);
272 assert(io_result == 0);
273
274 io_result = io_dev_open(memmap_dev_con, (uintptr_t)NULL,
275 &storage_dev_handle);
276 assert(io_result == 0);
277}
278
Patrick Delaunaye50571b2021-10-28 13:48:52 +0200279#if STM32MP_UART_PROGRAMMER
280static void stm32cubeprogrammer_uart(void)
281{
282 int ret __unused;
283 boot_api_context_t *boot_context =
284 (boot_api_context_t *)stm32mp_get_boot_ctx_address();
285 uintptr_t uart_base;
286
287 uart_base = get_uart_address(boot_context->boot_interface_instance);
288 ret = stm32cubeprog_uart_load(uart_base, DWL_BUFFER_BASE, DWL_BUFFER_SIZE);
289 assert(ret == 0);
290}
291#endif
292
293#if STM32MP_USB_PROGRAMMER
Patrick Delaunay9c5ee782021-07-06 14:07:56 +0200294static void stm32cubeprogrammer_usb(void)
295{
296 int ret __unused;
297 struct usb_handle *pdev;
298
299 /* Init USB on platform */
300 pdev = usb_dfu_plat_init();
301
302 ret = stm32cubeprog_usb_load(pdev, DWL_BUFFER_BASE, DWL_BUFFER_SIZE);
303 assert(ret == 0);
304}
305#endif
Patrick Delaunaye50571b2021-10-28 13:48:52 +0200306#endif /* STM32MP_UART_PROGRAMMER || STM32MP_USB_PROGRAMMER */
307
Patrick Delaunay9c5ee782021-07-06 14:07:56 +0200308
Yann Gautiereae3fbf2019-04-23 13:34:03 +0200309void stm32mp_io_setup(void)
310{
311 int io_result __unused;
312 boot_api_context_t *boot_context =
313 (boot_api_context_t *)stm32mp_get_boot_ctx_address();
Yann Gautierf9d40d52019-01-17 14:41:46 +0100314
Yann Gautiereae3fbf2019-04-23 13:34:03 +0200315 print_boot_device(boot_context);
Yann Gautier8244e1d2018-10-15 09:36:58 +0200316
Yann Gautiereae3fbf2019-04-23 13:34:03 +0200317 if ((boot_context->boot_partition_used_toboot == 1U) ||
318 (boot_context->boot_partition_used_toboot == 2U)) {
Yann Gautier0ed7b2a2021-05-19 18:48:16 +0200319 INFO("Boot used partition fsbl%u\n",
Yann Gautiereae3fbf2019-04-23 13:34:03 +0200320 boot_context->boot_partition_used_toboot);
321 }
Yann Gautier8244e1d2018-10-15 09:36:58 +0200322
Yann Gautier0ed7b2a2021-05-19 18:48:16 +0200323 io_result = register_io_dev_fip(&fip_dev_con);
Yann Gautiereae3fbf2019-04-23 13:34:03 +0200324 assert(io_result == 0);
Yann Gautier8244e1d2018-10-15 09:36:58 +0200325
Yann Gautier0ed7b2a2021-05-19 18:48:16 +0200326 io_result = io_dev_open(fip_dev_con, (uintptr_t)NULL,
327 &fip_dev_handle);
Yann Gautier8244e1d2018-10-15 09:36:58 +0200328
Yann Gautiereae3fbf2019-04-23 13:34:03 +0200329 switch (boot_context->boot_interface_selected) {
Nicolas Le Bayon3f42cad2019-09-03 09:52:05 +0200330#if STM32MP_SDMMC
Yann Gautiereae3fbf2019-04-23 13:34:03 +0200331 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_SD:
332 dmbsy();
333 boot_mmc(MMC_IS_SD, boot_context->boot_interface_instance);
334 break;
Nicolas Le Bayon3f42cad2019-09-03 09:52:05 +0200335#endif
336#if STM32MP_EMMC
Yann Gautiereae3fbf2019-04-23 13:34:03 +0200337 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_EMMC:
338 dmbsy();
339 boot_mmc(MMC_IS_EMMC, boot_context->boot_interface_instance);
Yann Gautier8244e1d2018-10-15 09:36:58 +0200340 break;
Nicolas Le Bayon3f42cad2019-09-03 09:52:05 +0200341#endif
Lionel Debievecb0dbc42019-09-25 09:11:31 +0200342#if STM32MP_SPI_NOR
343 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NOR_QSPI:
344 dmbsy();
345 boot_spi_nor(boot_context);
346 break;
347#endif
Lionel Debieve402a46b2019-11-04 12:28:15 +0100348#if STM32MP_RAW_NAND
349 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_FMC:
350 dmbsy();
351 boot_fmc2_nand(boot_context);
352 break;
353#endif
Lionel Debieve186b0462019-09-24 18:30:12 +0200354#if STM32MP_SPI_NAND
355 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_QSPI:
356 dmbsy();
357 boot_spi_nand(boot_context);
358 break;
359#endif
Patrick Delaunaye50571b2021-10-28 13:48:52 +0200360#if STM32MP_UART_PROGRAMMER || STM32MP_USB_PROGRAMMER
361#if STM32MP_UART_PROGRAMMER
362 case BOOT_API_CTX_BOOT_INTERFACE_SEL_SERIAL_UART:
363#endif
Patrick Delaunay9c5ee782021-07-06 14:07:56 +0200364#if STM32MP_USB_PROGRAMMER
365 case BOOT_API_CTX_BOOT_INTERFACE_SEL_SERIAL_USB:
Patrick Delaunaye50571b2021-10-28 13:48:52 +0200366#endif
Patrick Delaunay9c5ee782021-07-06 14:07:56 +0200367 dmbsy();
368 mmap_io_setup();
369 break;
370#endif
Yann Gautier8244e1d2018-10-15 09:36:58 +0200371
372 default:
373 ERROR("Boot interface %d not supported\n",
374 boot_context->boot_interface_selected);
Yann Gautier4c2b73d2021-06-30 17:04:22 +0200375 panic();
Yann Gautier8244e1d2018-10-15 09:36:58 +0200376 break;
Yann Gautier0ed7b2a2021-05-19 18:48:16 +0200377 }
378}
379
380int bl2_plat_handle_pre_image_load(unsigned int image_id)
381{
382 static bool gpt_init_done __unused;
383 uint16_t boot_itf = stm32mp_get_boot_itf_selected();
384
385 switch (boot_itf) {
386#if STM32MP_SDMMC || STM32MP_EMMC
387 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_SD:
388 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_EMMC:
389 if (!gpt_init_done) {
Sughosh Ganub721f8a2021-12-01 16:45:11 +0530390/*
391 * With FWU Multi Bank feature enabled, the selection of
392 * the image to boot will be done by fwu_init calling the
393 * platform hook, plat_fwu_set_images_source.
394 */
395#if !PSA_FWU_SUPPORT
Yann Gautier0ed7b2a2021-05-19 18:48:16 +0200396 const partition_entry_t *entry;
397
398 partition_init(GPT_IMAGE_ID);
399 entry = get_partition_entry(FIP_IMAGE_NAME);
400 if (entry == NULL) {
401 ERROR("Could NOT find the %s partition!\n",
402 FIP_IMAGE_NAME);
403 return -ENOENT;
404 }
405
406 image_block_spec.offset = entry->start;
407 image_block_spec.length = entry->length;
Sughosh Ganub721f8a2021-12-01 16:45:11 +0530408#endif
Yann Gautier0ed7b2a2021-05-19 18:48:16 +0200409 gpt_init_done = true;
Yann Gautiera3bd8d12021-06-18 11:33:26 +0200410 } else {
411 bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id);
412
413 mmc_block_dev_spec.buffer.offset = bl_mem_params->image_info.image_base;
414 mmc_block_dev_spec.buffer.length = bl_mem_params->image_info.image_max_size;
Yann Gautier0ed7b2a2021-05-19 18:48:16 +0200415 }
416
417 break;
418#endif
419
420#if STM32MP_RAW_NAND || STM32MP_SPI_NAND
421#if STM32MP_RAW_NAND
422 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_FMC:
423#endif
424#if STM32MP_SPI_NAND
425 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_QSPI:
426#endif
427 image_block_spec.offset = STM32MP_NAND_FIP_OFFSET;
428 break;
429#endif
430
431#if STM32MP_SPI_NOR
432 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NOR_QSPI:
433 image_block_spec.offset = STM32MP_NOR_FIP_OFFSET;
434 break;
435#endif
436
Patrick Delaunaye50571b2021-10-28 13:48:52 +0200437#if STM32MP_UART_PROGRAMMER
438 case BOOT_API_CTX_BOOT_INTERFACE_SEL_SERIAL_UART:
439 if (image_id == FW_CONFIG_ID) {
440 stm32cubeprogrammer_uart();
441 /* FIP loaded at DWL address */
442 image_block_spec.offset = DWL_BUFFER_BASE;
443 image_block_spec.length = DWL_BUFFER_SIZE;
444 }
445 break;
446#endif
Patrick Delaunay9c5ee782021-07-06 14:07:56 +0200447#if STM32MP_USB_PROGRAMMER
448 case BOOT_API_CTX_BOOT_INTERFACE_SEL_SERIAL_USB:
449 if (image_id == FW_CONFIG_ID) {
450 stm32cubeprogrammer_usb();
451 /* FIP loaded at DWL address */
452 image_block_spec.offset = DWL_BUFFER_BASE;
453 image_block_spec.length = DWL_BUFFER_SIZE;
454 }
455 break;
456#endif
457
Yann Gautier0ed7b2a2021-05-19 18:48:16 +0200458 default:
459 ERROR("FIP Not found\n");
460 panic();
Yann Gautier8244e1d2018-10-15 09:36:58 +0200461 }
Yann Gautier0ed7b2a2021-05-19 18:48:16 +0200462
463 return 0;
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200464}
465
466/*
467 * Return an IO device handle and specification which can be used to access
468 * an image. Use this to enforce platform load policy.
469 */
470int plat_get_image_source(unsigned int image_id, uintptr_t *dev_handle,
471 uintptr_t *image_spec)
472{
473 int rc;
474 const struct plat_io_policy *policy;
475
Yann Gautier29f1f942021-07-13 18:07:41 +0200476 policy = FCONF_GET_PROPERTY(stm32mp, io_policies, image_id);
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200477 rc = policy->check(policy->image_spec);
478 if (rc == 0) {
479 *image_spec = policy->image_spec;
480 *dev_handle = *(policy->dev_handle);
481 }
482
483 return rc;
484}
Sughosh Ganub721f8a2021-12-01 16:45:11 +0530485
486#if (STM32MP_SDMMC || STM32MP_EMMC) && PSA_FWU_SUPPORT
487/*
Nicolas Toromanoff5a937cd2022-02-07 10:12:04 +0100488 * In each boot in non-trial mode, we set the BKP register to
489 * FWU_MAX_TRIAL_REBOOT, and return the active_index from metadata.
490 *
491 * As long as the update agent didn't update the "accepted" field in metadata
492 * (i.e. we are in trial mode), we select the new active_index.
493 * To avoid infinite boot loop at trial boot we decrement a BKP register.
494 * If this counter is 0:
495 * - an unexpected TAMPER event raised (that resets the BKP registers to 0)
496 * - a power-off occurs before the update agent was able to update the
497 * "accepted' field
498 * - we already boot FWU_MAX_TRIAL_REBOOT times in trial mode.
499 * we select the previous_active_index.
Sughosh Ganub721f8a2021-12-01 16:45:11 +0530500 */
Nicolas Toromanoff5a937cd2022-02-07 10:12:04 +0100501#define INVALID_BOOT_IDX 0xFFFFFFFF
502
Sughosh Ganub721f8a2021-12-01 16:45:11 +0530503uint32_t plat_fwu_get_boot_idx(void)
504{
Nicolas Toromanoff5a937cd2022-02-07 10:12:04 +0100505 /*
506 * Select boot index and update boot counter only once per boot
507 * even if this function is called several times.
508 */
509 static uint32_t boot_idx = INVALID_BOOT_IDX;
510 const struct fwu_metadata *data;
Sughosh Ganub721f8a2021-12-01 16:45:11 +0530511
Nicolas Toromanoff5a937cd2022-02-07 10:12:04 +0100512 data = fwu_get_metadata();
513
514 if (boot_idx == INVALID_BOOT_IDX) {
515 boot_idx = data->active_index;
516 if (fwu_is_trial_run_state()) {
517 if (stm32_get_and_dec_fwu_trial_boot_cnt() == 0U) {
518 WARN("Trial FWU fails %u times\n",
519 FWU_MAX_TRIAL_REBOOT);
520 boot_idx = data->previous_active_index;
521 }
522 } else {
523 stm32_set_max_fwu_trial_boot_cnt();
524 }
525 }
Sughosh Ganub721f8a2021-12-01 16:45:11 +0530526
Nicolas Toromanoff5a937cd2022-02-07 10:12:04 +0100527 return boot_idx;
Sughosh Ganub721f8a2021-12-01 16:45:11 +0530528}
529
530static void *stm32_get_image_spec(const uuid_t *img_type_uuid)
531{
532 unsigned int i;
533
534 for (i = 0U; i < MAX_NUMBER_IDS; i++) {
535 if ((guidcmp(&policies[i].img_type_guid, img_type_uuid)) == 0) {
536 return (void *)policies[i].image_spec;
537 }
538 }
539
540 return NULL;
541}
542
543void plat_fwu_set_images_source(const struct fwu_metadata *metadata)
544{
545 unsigned int i;
546 uint32_t boot_idx;
547 const partition_entry_t *entry;
548 const uuid_t *img_type_uuid, *img_uuid;
549 io_block_spec_t *image_spec;
550
551 boot_idx = plat_fwu_get_boot_idx();
552 assert(boot_idx < NR_OF_FW_BANKS);
553
554 for (i = 0U; i < NR_OF_IMAGES_IN_FW_BANK; i++) {
555 img_type_uuid = &metadata->img_entry[i].img_type_uuid;
556 image_spec = stm32_get_image_spec(img_type_uuid);
557 if (image_spec == NULL) {
558 ERROR("Unable to get image spec for the image in the metadata\n");
559 panic();
560 }
561
562 img_uuid =
563 &metadata->img_entry[i].img_props[boot_idx].img_uuid;
564
565 entry = get_partition_entry_by_uuid(img_uuid);
566 if (entry == NULL) {
567 ERROR("Unable to find the partition with the uuid mentioned in metadata\n");
568 panic();
569 }
570
571 image_spec->offset = entry->start;
572 image_spec->length = entry->length;
573 }
574}
Sughosh Ganud1f87132021-12-01 16:46:34 +0530575
576static int plat_set_image_source(unsigned int image_id,
577 uintptr_t *handle,
578 uintptr_t *image_spec,
579 const char *part_name)
580{
581 struct plat_io_policy *policy;
582 io_block_spec_t *spec;
583 const partition_entry_t *entry = get_partition_entry(part_name);
584
585 if (entry == NULL) {
586 ERROR("Unable to find the %s partition\n", part_name);
587 return -ENOENT;
588 }
589
590 policy = &policies[image_id];
591
592 spec = (io_block_spec_t *)policy->image_spec;
593 spec->offset = entry->start;
594 spec->length = entry->length;
595
596 *image_spec = policy->image_spec;
597 *handle = *policy->dev_handle;
598
599 return 0;
600}
601
602int plat_fwu_set_metadata_image_source(unsigned int image_id,
603 uintptr_t *handle,
604 uintptr_t *image_spec)
605{
606 char *part_name;
607
608 assert((image_id == FWU_METADATA_IMAGE_ID) ||
609 (image_id == BKUP_FWU_METADATA_IMAGE_ID));
610
611 partition_init(GPT_IMAGE_ID);
612
613 if (image_id == FWU_METADATA_IMAGE_ID) {
614 part_name = METADATA_PART_1;
615 } else {
616 part_name = METADATA_PART_2;
617 }
618
619 return plat_set_image_source(image_id, handle, image_spec,
620 part_name);
621}
Sughosh Ganub721f8a2021-12-01 16:45:11 +0530622#endif /* (STM32MP_SDMMC || STM32MP_EMMC) && PSA_FWU_SUPPORT */